MCXA156 NXP | Alldatasheet

Document overview

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  • PDF pages: 88

Technical content

Datasheet sections

  • 1 Feature Comparison
  • 2 Ratings
  • 2.1 Thermal handling ratings
  • 2.2 Moisture handling ratings
  • 2.3 ESD handling ratings
  • 2.4 Voltage and current maximum ratings
  • 2.5 Required Power-On-Reset (POR) Sequencing
  • 3 General
  • 3.1 AC electrical characteristics
  • 3.2 Nonswitching electrical specifications
  • 3.2.2 HVD, LVD, and POR operating requirements
  • 3.2.2.1 VDD supply HVD, LVD, and POR Operating
  • 3.2.3 Voltage and current operating behaviors
  • 3.2.4 On-chip regulator electrical specifications
  • 3.2.4.1 LDO_CORE electrical specifications
  • 3.2.6 Power consumption operating behaviors
  • 3.2.7 EMC radiated emissions operating behaviors
  • 3.2.8 Designing with radiated emissions in mind
  • 3.2.9 Capacitance attributes
  • 3.3 Switching specifications
  • 3.3.1 Device clock specs
  • 3.3.2 General switching specifications
  • 3.3.2.1 General switching specifications
  • 3.4 Thermal specifications
  • 3.4.1 Thermal operating requirements
  • 3.4.2 Thermal attributes
  • 4 Peripheral operating requirements and behaviors
  • 4.1 Core modules
  • 4.1.1 Debug trace operating behaviors
  • 4.1.2 JTAG Debug Interface Timing
  • 4.1.3 Serial Wire Debug (SWD) Timing
  • 4.2 Clock modules
  • 4.2.1 Reference Oscillator Specification
  • 4.2.1.1 System Crystal Oscillator Specification
  • 4.2.1.2 System Oscillator Crystal Specifications
  • 4.2.1.3 System Oscillator Crystal Specifications
  • 4.2.2 FRO-192M specifications
  • 4.2.3 FRO-12M specifications
  • 4.2.4 FRO16K specifications
  • 4.3 Memories and memory interfaces
  • 4.3.1 Flash electrical specifications
  • 4.3.1.1 Timing specifications
  • 4.3.1.2 Flash high voltage current behavior
  • 4.3.1.3 Flash reliability specifications
  • 4.4 Analog
  • 4.4.1 ADC electrical specifications
  • 4.4.1.1 ADC operating conditions
  • 4.4.1.2 I/O mux resistance table
  • 4.4.1.3 ADC electrical characteristics
  • 4.4.3 Comparator and 8-bit DAC electrical
  • 4.4.4 OpAmp electrical specifications
  • 4.4.5 PGA electrical specifications
  • 4.5 Timers
  • 4.6 Communication Interfaces
  • 4.6.1 LPUART
  • 4.6.2 LPSPI switching specifications
  • 4.6.2.1 LPSPI master mode timing
  • 4.6.2.2 LPSPI slave mode timing
  • 4.6.3 LPI2C timing
  • 4.6.4 I2C 1 Mbps timing
  • 4.6.5 I2C HS mode timing
  • 4.6.6 I3C Push-Pull Timing Parameters for SDR
  • 4.6.7 USB Full-speed device electrical specifications
  • 4.6.8 FlexCAN
  • 4.6.9 Flexible I/O controller (FLEXIO) electrical
  • 4.7 Human Machine Interface (HMI) modules
  • 4.7.1 General Purpose Input/Output (GPIO)
  • 5 Package dimensions
  • 5.1 Obtaining package dimensions
  • 6 Pinout
  • 6.1 MCXA156, A155, A154, A146, A145, A144
  • 6.2 MCXA156, A155, A154, A146, A145, A144
  • 6.3 Recommended connection for unused analog
  • 7 Ordering parts
  • 7.1 Determining valid orderable parts
  • 8 Part identification
  • 8.1 Description
  • 8.2 Part number format
  • 8.3 Example
  • 8.4 Small package marking
  • 8.4.1 Package marking information
  • 9 Terminology and guidelines
  • 9.1 Definitions

Features

  • Arm Cortex-M33 48MHz(A14x) or 96MHz(A15x) with 396 CoreMark (4.12 CoreMark/MHz)
  • Up to 1MB Flash, 128KB SRAM, up to 8 KB SRAM with ECC
  • All RAM can be retained down to Deep Power Down mode
  • -40 °C to 125 °C temperature range
  • Down to 64 μA/MHz Active current, 32.26 μA Deep Sleep current, 8.2 μA Power Down current, 412 nA Deep Power Down current Core
  • Arm 32-bit Cortex-M33 CPU, with FPU and DSP extension instruction set, no TrustZone, no MPU Memories
  • Single-bank Flash: Up to 1024 KB Flash with ECC (support one bit correction and two bits detection)
  • Cache Engine with 4 KB RAM
  • Up to 128 KB RAM, configurable as up to 8KB RAM with ECC (support one bit correction and two bits detection)
  • All RAM can be retained down to Deep Power Down mode
  • 16 KB ROM Security
  • 128-bit Universal Unique Identifier (UUID) per device in accordance with IETF's RFC4122 version5 specification
  • Device lifecycle management
  • Flash read/write/execute permission protect by MBC and lockable
  • Implicit-protected Flash Region (IFR)
  • Security Monitoring: — Code Watchdog for code flow integrity checking — GLIKEY enhances protection against attacks to gain unauthorized access to sensitive registers Low-Power Performance
  • Active — 64 μA/MHz in Active Mode (executing while(1) from flash, 3.3 V@25 °C)
  • Deep Sleep — 32.26 μA, 7.1 μs wake-up (3.3 V@25 °C)
  • Power Down — 8.2 μA, 16.6 μs wake-up (RAM X0/X1 and RAM A0 retained, 3.3 V@25 °C) MCXA14x MCXA15x LQFP100 14 x 14 x 1.4 mm, 0.5mm LFBGA64 5 x 5 x 1.2 mm,0.5mm VFBGA112 7 x 7x 0.86mm, 0.5mm MCXA156, A155, A154, A146, A145, A144 Data Sheet Arm® Cortex®-M33 48MHz or 96MHz 32-bit MCU, up to 1MB Flash Rev. 5 — July 2024 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

— 412 nA, 1.44 ms wake-up (wake timer disabled, reset pin enabled, all SRAM off, 3.3 V@25 °C) System and Clocks

  • 192 MHz free-running oscillator (FRO192M)
  • 12 MHz free-running oscillator (FRO12M)
  • 16 KHz free-running oscillator (FRO16K)
  • Up to 50 MHz crystal oscillator
  • Hardware and Software Watchdogs
  • Asynchronous DMA modules (8-channels) Communication Interfaces for Connectivity
  • 4x LPI2C, 2x LPSPI, 5x LPUART
  • 1x I3C
  • USB Full-speed (Device) with on-chip FS PHY
  • 1x FlexCAN with FD
  • FlexIO Advanced Motor Control
  • Up to 2x FlexPWM each with 3 sub-modules, providing 12 complementary outputs of PWM (no Nanoedge module)
  • Up to 2x Quadrature Decoder (eQDC)
  • 2x AOI (AND/OR/Invert) module support up to 4 output trigger Analog
  • 2x 16-bit ADC — Up to 3.2 Msps in 16-bit mode, and 4 Msps in 12-bit — Up to 32 ADC Input channels (depending on the package) — One integrated temperature sensor per ADC
  • 1x 12-bit DAC
  • Two Low power Comparators (LPCMP) with 8 input pins and 8-bit DAC as internal reference — 1x LPCMP is functional down to Deep Power Down mode
  • 1x OpAmp with PGA Timers
  • Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests.
  • Low power timer
  • Frequency measurement timer
  • Windowed watchdog timer
  • Wake timer
  • Micro-tick timer (UTICK)
  • OS event timer General-purpose input/output NXP Semiconductors MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 2 / 88
  • Up to 82 GPIOs
  • Up to eight 20 mA IO
  • 50 MHz IO on P1, P3 and P4
  • Up to 19-pin wake-up sources function down to Deep Power Down mode
  • Support 1.71 V~3.6 V IO supply range
  • Support 1.2V independent IO supply on P3 port Power Management
  • Integrated voltage regulator — Core LDO, other LDOs
  • Operating range: 1.71 V to 3.6 V
  • IOs: 1.71 V-3.6 V full-performance Target Applications Industrial
  • Energy Storage and Management System
  • Smart Metering
  • Factory Automation
  • Industrial HMI
  • Mobile Robotics Ecosystem
  • Motion Control and Robotics
  • Motor Drives
  • Brushless DC Motor (BLDC) Control
  • Permanent Magnet Synchronous Motor (PMSM) Smart Home
  • Home Control Panel
  • Major Home Appliances
  • Robotic Appliance
  • Smart Speaker
  • Soundbar
  • Gaming Accessories
  • Smart Lighting
  • Smart Power Socket and Light Switch

Table 1. Ordering Information Table continues on the next page...

Table 1. Ordering Information (continued) Table 2. Device Revision Number Table 3. Related Resources structure and function (operation) of a device. information for a particular device mask set.

  • LFBGA64: 98ASA02085D Table continues on the next page... NXP Semiconductors MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 4 / 88

Table 3. Related Resources (continued)

  • VFBGA112: 98ASA02081D Software development kit MCUXpresso SDK. An open source software development kit (SDK) built specifically for your processor and evaluation board selections. http://www.nxp.com/mcuxpresso 2x 16 bit ADC 1x OpAmp w/ PGA 2x LPCMP 1 x 12-bit DAC Temp sensor A n a l o g Arm ® Cortex ® - M33 48/96 MHz with FPU, SIMD C o r e M e m o r i e s S y s t e m Security monitoring (intrusion detection) Access control (memory and debug) Lifecycle management S e c u r i t y 2x FlexPWM Up to 1 MB flash w/4 KB cache Up to 128 KB SRAM (8 KB w/ECC)

16 KB ROM w/boot loader

Figure 1. Block Diagram

8 KB w/ ECC

Figure 2. Bus Architecture

9.4 Relationship between ratings and operating

9.5 Guidelines for ratings and operating

1 Feature Comparison

Table 4. Feature Comparison

48 MHz 48 MHz 48 MHz 192 MHz 192 MHz 192 MHz

12 MHz

16.384 KHz

Table continues on the next page...

Table 4. Feature Comparison (continued)

50 MHz IO 7 Up to 21

  1. Flexible data rate (CAN FD) is available on MCXA156/A155/A154
  2. FlexPWM0 is available on MCXA146/A145/A144. There‘re 3 sub-modules for each FlexPWM module.
  3. eQDC0 is available on MCXA146/A145/A144.
  1. Support 1.2V IO power supply.
  2. P3_27, P3_28 are 5V tolerant IOs.
  3. 50 MHz IOs are located on P1, P3, P4 ports.
  4. Show the package types and GPIO numbers

2 Ratings

2.1 Thermal handling ratings

Table 5. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.2 Moisture handling ratings

Table 6. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

2.3 ESD handling ratings

Table 7. ESD handling ratings

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-001-2023, For Electrostatic Discharge Sensitivity Testing,

Human Body Model (HBM) - Device Level.

  1. Determined according to ANSI/ESDA/JEDEC Standard JS-002-2022, For Electrostatic Discharge Sensitivity Testing,

Charged Device Model (CDM) - Device Level.

  1. Determined according JEDEC Standard JESD78F, IC Latch-Up Test.

2.4 Voltage and current maximum ratings

Table 8. Voltage and current maximum ratings VDIO Digital input voltage -0.3 — VDD + 0.

  1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
  2. This limit is per supply pin. It includes all power pins, including VDD, VDD_P3, VDD_ANA, VDD_USB.

2.5 Required Power-On-Reset (POR) Sequencing

  • VDD and VDD_ANA must be same voltage

3 General

3.1 AC electrical characteristics

at the 20% and 80% points, as shown in the following figure.

Figure 3. Input signal measurement reference

3.2 Nonswitching electrical specifications

3.2.1 Voltage and current operating requirement

Table 9. Voltage and current operating requirement VDD_ANA Supply voltage for ADC VDD - 0. Table continues on the next page...

Table 9. Voltage and current operating requirement (continued)

  1. All I/O pins are internally clamped to VSS and VDD through an ESD protection diode. If VIN is greater than
  2. Open drain outputs must be pulled to whichever supply voltage corresponds to that IO, VDD as appropriate.

3.2.2 HVD, LVD, and POR operating requirements

  • VDD

3.2.2.1 VDD supply HVD, LVD, and POR Operating Requirements

Table 10. VDD supply HVD, LVD, and POR Operating Requirements

3.2.3 Voltage and current operating behaviors

Table 11. Voltage and current operating behaviors Table continues on the next page...

Table 11. Voltage and current operating behaviors (continued)

0.27 V)/3

  1. For the HD pads, when setting DSE1=1, the IOH/IOL are four times higher at the same VOH/VOL.
  2. RESET_B pins are always configured in high drive mode
  3. Open drain outputs must be pulled to VDD
  4. Only I3C pins support this option
  5. Only RST pins support this option.

3.2.4 On-chip regulator electrical specifications

3.2.4.1 LDO_CORE electrical specifications

Table 12. LDO_CORE electrical specifications

3.2.5 Power mode transition operating behaviors

  • CPU clock = 48 MHz
  • AHB clock = 48 MHz
  • Clock source = FIRC NXP Semiconductors General MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 16 / 88

Table 13. Power mode transition operating behaviors

  1. Max value is mean+3 × sigma of tested values at the worst case of ambient temperature range and VDD 1.71 V to 3.6 V.

Max values are based on characterization but not covered by test limits in production.

  1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V
  2. WFE used for Low Power mode entry
  3. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x00 and the Core voltage level is configured for the same level in Active

and Low Power mode (SPC->ACTIVE_CFG[CORELDO_VDD_LVL]=SPC->LP_CFG[CORELDO_VDD_LVL]= 01b).

  1. SPC->LPWKUP_DELAY[LPWKUP_DELAY] = 0x5B and the Core voltage level is configured as different level for Active

3.2.6 Power consumption operating behaviors

  • Specifications below only include power for the MCU itself including VDD, VDD_ANA, VDD_P3.
  • VDD_USB current draw are not included
  • On top of the device's IDD current consumption, external loads applied to pins of the device need to be considered Symbol Description Condition 1 Typ Unit IDD_ACT_MD_1 2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Flash is configured to LP mode; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 3.06 mA 105 °C 3.62 mA 125 °C 4.17 mA IDD_ACT_MD_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 3.31 mA 105 °C 3.90 mA 125 °C 4.47 mA IDD_ACT_MD_CM_1 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 25 °C 3.40 mA Table continues on the next page... NXP Semiconductors General MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 17 / 88

Table continued from the previous page... 2. All peripheral clocks disabled; Flash is configured to LP mode; Cache enabled. 3. CoreMark executing from internal flash. 105 °C 3.95 mA 125 °C 4.48 mA IDD_ACT_MD_CM_2 1. CPU_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 3.66 mA 105 °C 4.23 mA 125 °C 4.79 mA IDD_ACT_SD_1 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 6.40 mA 105 °C 7.11 mA 125 °C 7.76 mA IDD_ACT_SD_2 1. CPU_CLK = 96 MHz from FRO192M, FRO192M output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. While(1) loop executing from internal flash. 25 °C 7.45 mA 105 °C 8.16 mA 125 °C 8.82 mA IDD_ACT_SD_CM_1 1. CPU_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 7.09 mA 105 °C 7.72 mA 125 °C 8.40 mA IDD_ACT_SD_CM_2 1. CPU_CLK = 96 MHz from FRO192M, FRO192M output is 192MHz; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks enabled; Cache enabled. 3. CoreMark executing from internal flash. 25 °C 8.13 mA 105 °C 8.79 mA 125 °C 9.42 mA IDD_SLEEP_SD 1. CPU_CLK = OFF, SYSTEM_CLK = 96 MHz from FRO192M; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. All peripheral clocks disabled. 25 °C 3.34 mA 105 °C 4.05 mA 125 °C 4.70 mA IDD_SLEEP_MD_1 1. CPU_CLK = OFF, SYSTEM_CLK = 48 MHz from FRO192M; VDD_CORE = 1.0 V from LDO_CORE normal drive. 2. All peripheral clocks disabled. 25 °C 1.81 mA 105 °C 2.39 mA 125 °C 2.93 mA Table continues on the next page... NXP Semiconductors General MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 18 / 88

Table continued from the previous page... IDD_SLEEP_MD_2 1. CPU_CLK = OFF, SYSTEM_CLK = 12 MHz from FRO12M; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. All peripheral clocks disabled. 25 °C 0.43 mA 105 °C 0.99 mA 125 °C 1.55 mA IDD_DEEP_SLEEP_SD 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.1 V from LDO_CORE normal drive. 2. Core domain in Deep Sleep; FRO12M disabled. 25 °C 257.98 µA 105 °C 781.14 µA 125 °C 1286.88 µA IDD_DEEP_SLEEP_MD_1 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. Core domain in Deep Sleep; FRO12M disabled. 25 °C 32.26 µA 105 °C 470.82 µA 125 °C 916.19 µA IDD_DEEP_SLEEP_MD_2 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = 1.0 V from LDO_CORE low drive. 2. Core domain in Deep Sleep; FRO12M enabled. 25 °C 104.53 µA 105 °C 542.00 µA 125 °C 988.01 µA IDD_POWER_DOWN_1 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. 2. Core domain in Power Down(Lowest power mode can retain all registers); All RAM retained; FRO16K disabled. 25 °C 9.47 µA 105 °C 257.00 µA 125 °C 520.08 µA IDD_POWER_DOWN_2 1. CPU_CLK = SYSTEM_CLK = OFF; VDD_CORE = retention voltage from LDO_CORE low drive. 2. Core domain in Power Down(Lowest power mode can retain all registers); RAM X0/X1 and RAM A0 retained; FRO16K disabled. 25 °C 8.20 µA 105 °C 222.28 µA 125 °C 443.17 µA IDD_DEEP_POWER_DO WN_1 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM OFF; FRO16K disabled; Wakeup timer disabled. 25 °C 0.41 µA 105 °C 5.62 µA 125 °C 12.88 µA IDD_DEEP_POWER_DO WN_2 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM OFF; FRO16K enabled; Wakeup timer enabled. 25 °C 0.60 µA 105 °C 5.83 µA 125 °C 13.08 µA IDD_DEEP_POWER_DO WN_3 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 2. Core domain in Deep Power Down; All RAM retained; FRO16K enabled; Wakeup timer enabled. 25 °C 2.19 µA 105 °C 47.39 µA 125 °C 105.34 µA IDD_DEEP_POWER_DO WN_4 1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is powered off. 25 °C 1.57 µA Table continues on the next page... NXP Semiconductors General MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 19 / 88

Table continued from the previous page...

  1. Core domain in Deep Power Down; RAM X0/X1
  2. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
  3. Core domain in Deep Power Down; RAM X0/X1 and
  4. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
  5. Core domain in Deep Power Down; RAM A0

retained; FRO16K enabled; Wakeup timer enabled.

  1. CPU_CLK = SYSTEM_CLK = OFF; LDO_CORE is
  2. Core domain in Deep Power Down; RAM X0/X1

retained; FRO16K enabled; Wakeup timer enabled.

  1. SD standard drive, core voltage is 1.1V. MD middle drive, core voltage is 1.0V

3.2.7 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

3.2.8 Designing with radiated emissions in mind

  1. Perform a keyword search for “EMC design”.

3.2.9 Capacitance attributes

Table 14. Capacitance attributes

3.3 Switching specifications

3.3.1 Device clock specs

Table 15. Device clock specs

3.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPUART, LPI2C, LPI3C, LPSPI functions.

3.3.2.1 General switching specifications

Refer to attached pinout spreadsheet. Table 16. General switching specifications Table continues on the next page...

Table 16. General switching specifications (continued) Table continues on the next page...

  1. The synchronous and asynchronous timing must be met.
  2. This is the shortest pulse that is guaranteed to be recognized
  3. For the HD I/O pins, setting DSE1 = 1 will support the same rise/fall time at 4x the load capacitance. For the 5VTOL I/O
  4. Assumes default values in CALIB1 and CALIB0 in PORTS
  5. Load is 25 pF for DSE=0. Load is 100 pF for DSE=2 or DSE=3. Drive strength and slew rate are configured using

PORTx_PCRn[DSE1], PORTx_PCRn[DSE], and PORTx_PCRn[SRE].

3.4 Thermal specifications

3.4.1 Thermal operating requirements

Table 17. Thermal operating requirements

  1. The device may operate at maximum TA rating as long as TJ maximum of 125 °C is not exceeded. The simplest method to

determine TJ is: TJ = TA + RθJA*chip power dissipation.

  1. Operating at maximum conditions for extended periods may affect device reliability. Refer to Product Lifetime Usage
  2. The device operating specification is not guaranteed beyond 125 °C TJ.
  3. The maximum operating requirement applies to all chapters unless otherwise specifically stated.

3.4.2 Thermal attributes

Table 18. Thermal attributes

  1. Thermal test board meets JEDEC specification for this package (JESD51-9)
  2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
  3. Junction-to-Case top thermal resistance determined using an isothermal cold plate.

4 Peripheral operating requirements and behaviors

4.1 Core modules

4.1.1 Debug trace operating behaviors

Table 19. Debug trace operating behaviors Table continues on the next page...

Table 19. Debug trace operating behaviors (continued) Figure 4. TRACE_CLKOUT specifications Figure 5. Trace data specifications

4.1.2 JTAG Debug Interface Timing

The following table gives the JTAG specifications in debug interface mode. Table 20. JTAG Debug Interface Timing Table continues on the next page...

Table 20. JTAG Debug Interface Timing (continued) TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.

Figure 6. Test clock input timing Figure 7. Boundary scan (JTAG) timing Figure 8. JTAG-DP/TAP timing

4.1.3 Serial Wire Debug (SWD) Timing

The following table gives the Serial Wire Debug specifications for the device.

Table 21. Serial Wire Debug (SWD) Timing Figure 9. Serial Wire clock input timing

Figure 10. Serial Wire data timing

4.2 Clock modules

4.2.1 Reference Oscillator Specification

temperature, mechanical, and aging excursions. The table below shows typical specifications for the Crystal Oscillator.

4.2.1.1 System Crystal Oscillator Specification

Table 22. System Crystal Oscillator Specification

  1. When a crystal is being used with the oscillator, the EXTAL and XTAL pins should only be connected to required oscillator

components and must not be connected to any other devices.

  1. This specification is for an externally supplied clock driven to EXTAL and does not apply to any other clock input.

4.2.1.2 System Oscillator Crystal Specifications. Table 23. System Oscillator Crystal Specifications.

  1. Maximum crystal equivalent series resistance for 16 MHz is 80 ohms with 2 pF shunt capacitance.
  2. Dependent on crystal specifications, proper PC board layout procedures must be followed to achieve specifications

Figure 11. Crystal Electrical Block Diagram

4.2.1.3 System Oscillator Crystal Specifications

Table 24. System Oscillator Crystal Specifications. Table continues on the next page...

Table 24. System Oscillator Crystal Specifications. (continued)

  1. This is based on simulation

4.2.2 FRO-192M specifications

Table 25. FRO-192M specifications

4.2.3 FRO-12M specifications

Table 26. FRO-12M specifications

4.2.4 FRO16K specifications

Table 27. FRO16K specifications

4.3 Memories and memory interfaces

4.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

4.3.1.1 Timing specifications

4.3.1.1.1 Flash command time specifications

Table 28. Flash command time specifications Table continues on the next page...

Table 28. Flash command time specifications (continued) Table continues on the next page...

  1. Time to abort the command may significantly impact the time to execute the command.
  2. Measured from the time FSTAT[PERDY] is cleared.

4.3.1.2 Flash high voltage current behavior

Table 29. Flash high voltage current behavior

  1. See the Power Management chapter in the reference manual for the specific VDD voltage supply powering the flash array.

4.3.1.3 Flash reliability specifications. Table 30. Flash reliability specifications. Table continues on the next page...

Table 30. Flash reliability specifications. (continued)

256 KB 2

100 K 500 K — Cycles Program Flash

  1. Sector cycling endurance represents the number of Program/Erase cycles on a single sector at -40°C ≤ Tj ≤ 125°C.
  2. For devices with a single flash block, sectors must be located within the last 256 KB of the flash main memory. For devices

4.4 Analog

4.4.1 ADC electrical specifications

ADC operating conditions apply when the ADC is used in differential mode. All other ADC channels meet the 12-bit single-ended accuracy specifications.

4.4.1.1 ADC operating conditions

Table 31. ADC operating conditions Table continues on the next page...

Table 31. ADC operating conditions (continued)

  1. Minimum VDDAD/VREFH is 2.4 V in high-speed mode
  2. For devices that do not have a dedicated VREFL and VSS_ANA pins, VREFL and VSS_ANA are tied to VSS internally.
  3. ADC selected inputs and unselected dedicated inputs must not exceed VDD_ANA during an ADC conversion. Unselected

between the source and the ADC input pin.

  1. If VREFH is less than VDD_ANA, then voltage inputs greater than VREFH but less than VDD_ANA are allowed but result
  2. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
  3. If the input come through a mux in the IO pad, add the IO Mux Resistance Adder value to the resistance for the channel
  4. There are several types of ADC inputs. To see which channels correspond to which type of ADC inputs, see channel index

4.4.1.2 I/O mux resistance table

Table 32. I/O mux resistance table

Figure 12. ADC input impedance equivalency diagram

4.4.1.3 ADC electrical characteristics

Table 33. ADC electrical characteristics

6 MHz Clock,

24 MHz clock,

Table continues on the next page...

Table 33. ADC electrical characteristics (continued)

60 MHz Clock,

60 MHz, HS=1, AVGS

Table continues on the next page...

  1. The ADC supply current depends on the ADC conversion clock speed, conversion rate, and power mode. Typical value

show is at 6 MHz, 24 MHz, and 48 MHz. For lowest power operation, PWRSEL should be set to 00.

  1. Must meet minimum TSMP requirement
  1. Required sample time is dictated by external components RAS, CAS, internal components RADIN, CADIN, CP, and
  2. Min based on 3.5 cycles @ 60 MHz
  3. Min based on 3.5 cycles @ 64 MHz
  4. Internal channel inputs are those that do not come from external source (temperature sensor, bandgap).
  5. 1 LSB = (VREFH - VREFL)/2N (N=14 bits), for 16- bit specifications, multiply by 4.
  6. All accuracy numbers assume that the ADC is calibrated with VREFH=VDD_ANA and using a high- speed- dedicated input

values are for reference only, and are not tested in production.

  1. Dynamic results assume Fin=1 kHz sinewave, no averaging unless otherwise specified
  2. Delay required if PWREN=0
  3. The temperature sensor can be calibrated to a +/- 1 % precision after board assembly by using a 3-temperature calibration
  4. T(°C) = A*[°α(Vbe8 - Vbe1)/(Vbe8 + α(Vbe8 - Vbe1))] - B where Vbe1 is the first value stored to FIFO as a result of the

Set the power-up delay (PUDLY) according to the ADC start-up time if PWREN=0. Figure 13. ENOB vs ADC (16b HS Mode)

Figure 14. ENOB vs ADC sample rate Table 34. 12-bit DAC operating requirements

  1. The DAC reference can be selected to be VDD_ANA or VREFH or VREFO PAD, keep VDD_ANA be the highest voltage.
  2. A small load capacitance (50 pF) can improve the bandwidth performance of the DAC.
  3. Sink or source current availability

Table 35. 12-bit DAC operating behaviors Table continues on the next page...

Table 35. 12-bit DAC operating behaviors (continued)

  1. Settling within ±1 LSB measured with a 47 pF load.
  2. The INL is measured for 0 + 100 mV to VDACR −100 mV
  3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
  4. Calculated by a best fit curve from VSS_ANA + 100 mV to VDACR − 100 mV
  5. VDD_ANA = 3.0 V, reference select set for VDD_ANA (DACx_CO:DACRFS = 1), high- power mode (DACx_C0:LPEN = 0),

DAC set to 0x800, temperature range is across the full range of the device.

  1. If two DACs are used and share same VREFH

Figure 15. Typical INL error vs. digital code

Figure 16. Offset at half scale vs. temperature

4.4.3 Comparator and 8-bit DAC electrical specifications

Table 36. Comparator and 8-bit DAC electrical specifications Table continues on the next page...

Table 36. Comparator and 8-bit DAC electrical specifications (continued)

  1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_ANA–0.6 V.
  2. Overdrive does not include input offset voltage or hysteresis. The propagation delay is defined as the time delay between
  3. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

and the comparator output settling to a stable level.

Figure 19. Typical hysteresis vs Vin level (VDD =3.3 V, HPMD = 0, NPMD = 1)

4.4.4 OpAmp electrical specifications

Table 37. OpAmp electrical specifications Table continues on the next page...

Table 37. OpAmp electrical specifications (continued)

3 K — — Ω —

4.4.5 PGA electrical specifications

Table 38. PGA electrical specifications

4.5 Timers

See General switching specifications.

4.6 Communication Interfaces

4.6.1 LPUART

production. See General switching specifications.

4.6.2 LPSPI switching specifications

of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes.

4.6.2.1 LPSPI master mode timing

Table 39. LPSPI master mode timing Table continues on the next page...

Table 39. LPSPI master mode timing (continued)

  1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/2, where fperiph is the LPSPI

peripheral functional clock.

  1. If configured as an output.

Figure 20. LPSPI master mode timing (CPHA = 0) Figure 21. LPSPI master mode timing (CPHA = 1)

4.6.2.2 LPSPI slave mode timing

Table 40. LPSPI slave mode timing Table continues on the next page...

Table 40. LPSPI slave mode timing (continued) Table continues on the next page...

  1. The frequency of operation is also limited to a minimum of fperiph/2048 and a max of fperiph/4, where fperiph is the LPSPI

peripheral functional clock.

  1. Time to data active from high-impedance state
  2. Hold time to high-impedance state

Figure 22. LPSPI slave mode timing (CPHA = 0)

Figure 23. LPSPI slave mode timing (CPHA = 1)

4.6.3 LPI2C timing

Table 41. LPI2C timing Table continues on the next page...

Table 41. LPI2C timing (continued)

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal
  3. Input signal Slew = 10 ns and Output Load = 50 pF
  4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

  1. Cb = total capacitance of the one bus line in pF.

4.6.4 I2C 1 Mbps timing

Table 42. I2C 1 Mbps timing first clock pulse is generated.

  1. Cb = total capacitance of the one bus line in pF for maximum value

Figure 24. Timing definition for devices on the I2C bus

4.6.5 I2C HS mode timing

Table 43. I2C HS mode timing first clock pulse is generated.

  1. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
  2. Cb = total capacitance of the one bus line in pF. The max Cb value is 50 pF. Applicable for maximum value.

Only PTB4/5, PTA18/19, PTC0/1, PTC4/5 pin can support Fast+ (3 MHz) mode.

4.6.6 I3C Push-Pull Timing Parameters for SDR Mode

Medium Clock and PUR Pads Only. I3C Standard plus Data Pads to be used with I3C standard plus Clock and PUR pads only. Table 44. I3C Push-Pull Timing Parameters for SDR Mode Table continues on the next page...

Table 44. I3C Push-Pull Timing Parameters for SDR Mode (continued)

  1. As both edges are used, the hold time needs to be satisfied for the respective edges; i.e., tCF + 3 for falling edge clocks,

and tCR + 3 for rising edge clocks.

  1. tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH (see
  2. Devices with more than 12ns of tSCO delay shall set the limitation bit in the BCR, and shall support the GETMXDS
  3. Pad delay based on 90 Ω / 4 mA driver and 50 pF load. Note that Master may be a Slave in a multi-Master system, and
  4. The clock maximum rise/fall time is capped at 60 ns. For lower frequency rise and fall the maximum value is limited at 60

ns, and is not dependent upon the clock frequency.

  1. tHD_PP is a Hold time parameter for Push-Pull Mode that has a different value for Master mode vs. Slave mode. In SDR

Mode the Hold time parameter is referred to as tHD_SDR.

Figure 28. Slave out timing Figure 29. Master SDR timing

4.6.7 USB Full-speed device electrical specifications

compliance requirements defined in the Universal Serial Bus Revision 2.0 Specification with the amendments below.

  • USB ENGINEERING CHANGE NOTICE — Title: 5 V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0
  • Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
  • USB ENGINEERING CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0
  • USB ENGINEERING CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0 NXP Semiconductors Peripheral operating requirements and behaviors MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 60 / 88

4.6.8 FlexCAN

See General switching specifications.

4.6.9 Flexible I/O controller (FLEXIO) electrical specifications

The following table shows FlexIO timing specifications. Table 45. Flexible I/O controller (FLEXIO) electrical specifications

4.7 Human Machine Interface (HMI) modules

4.7.1 General Purpose Input/Output (GPIO)

See General switching specifications.

5 Package dimensions

5.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

6 Pinout

6.1 MCXA156, A155, A154, A146, A145, A144 Signal Multiplexing and Pin Assignments

  1. Click the paperclip symbol on the left side of the PDF window.
  1. Double-click on the Excel file to open it.

The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Table 46. Pinout Table continues on the next page...

Table 46. Pinout (continued) Table continues on the next page...

12 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

Table continues on the next page...

32 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

46 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

64 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

74 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

82 D4,D5,D6,E6,F5,F

Table continues on the next page...

Table continues on the next page...

96 D4,D5,D6,E6,F5,F

  • +I3C in Pad Type represents that strong pull up resistor is implemented on the pin. PV bit is implemented in Pin Control register of the pin.
  • +I2C_FILT in Pad Type represents that I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin.
  • HD in Pad Type represents that the pin can support up to 20mA drive strength. I2C filter is implemented on the pin. PFE bit is implemented in Pin Control register of the pin.
  • 5VTOL in Pad Type represents that the pin is 5V tolerant
  • DIS in default column represents that the pin's input buffer is disabled by default
  • RST pads support passive filter and 1M ohm pull resistor. PFE and PV bits are implemented in Pin Control register of the pin.
  • PE, PS, SRE, ODE and DSE are supported in Pin Control register of all types of IO.
  • 5VTol and HD pads support two DSE bits in Pin Control register of the pin.
  • PWM1, OpAMP and DAC are not available in MCXA145 and MCXA146.
  • In LQFP100, BGA112 and BGA64, the ISPMODE_n pin is on P0_6. In 64LQFP and smaller pin count package, ISPMODE_n pin is on P3_29.
  • SLOW in Pad Type represents the IO supports 25 MHz. MED in Pad Type represents the Io supports 50 MHz. NOTE

6.2 MCXA156, A155, A154, A146, A145, A144 Pinout diagram

  1. Click the paperclip symbol on the left side of the PDF window.
  2. Double-click on the Excel file to open it.
  3. Select the respective package tab.

6.3 Recommended connection for unused analog and digital pins

Table 47. Recommended connection for unused interfaces Table continues on the next page...

Table 47. Recommended connection for unused interfaces (continued)

7 Ordering parts

7.1 Determining valid orderable parts

8 Part identification

Part numbers for the device have fields that identify the specific part. Use the values of these fields to determine the specific part.

8.1 Description

8.2 Part number format

Table 48. Part number fields descriptions

  • 2 = 2nd Device w Always On Domain
  • 3 = 3rd Device w Advance Analog C Core Features • 4 = 48 MHz, Motor PWM, USB FS
  • 5 = 96 MHz, Motor PWM, USB FS FS Flash Size • 1 = 32 KB
  • 2 = 64 KB
  • 3 = 128 KB
  • 4 = 256 KB
  • 5 = 512 KB
  • 6 = 1024 KB
  • 7 = 2 M T Junction Temperature range (°C) • V = –40 to 125
  • MP = LFBGA64
  • PJ = VFBGA112 SR Silicon Revision • A = Initial Mask set
  • B = 1st Major spin
  • C = 2nd Major spin
  • T = Tray

8.3 Example

8.4 Small package marking

8.4.1 Package marking information

Table 49. Package marking

9 Terminology and guidelines

9.1 Definitions

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: Table continues on the next page... NXP Semiconductors Terminology and guidelines MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 81 / 88

Table continued from the previous page... Term Definition

  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE

9.2 Examples

9.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V NXP Semiconductors Terminology and guidelines MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 82 / 88

9.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

9.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9.6 Specification Test Methods

Each specification is tested using one of these methods. Code Method Description P Production direct On every chip during production, testing the specification I Production indirect On every chip during production, testing parts of a module that affect whether the chip meets the specification but not testing the specification itself C Characterization on a production tester Measuring a statistically significant number of sample chips across process (matrix lot), voltage, and temperatureL Characterization on lab equipment or a nonproduction tester Table continues on the next page... NXP Semiconductors Terminology and guidelines MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 83 / 88

Table continued from the previous page... Code Method Description Typical values are not necessarily characterized across process. NOTE D Guaranteed by design Specification based on scientific and engineering principles O Other Using methods such as:

  • Performing silicon simulations
  • Performing package thermal simulations
  • Calculating specifications using reliability data The following table provides a revision history for this document.

Table 50. Revision History

5 July 2024 • Initial public release

Revision History

MCXA156, A155, A154, A146, A145, A144 Data Sheet, Rev. 5, July 2024 Data Sheet: Technical Data 84 / 88

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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: July 2024 Document identifier: MCXAP100M96FS6