MCT8316ZR

MCT8316Z_V01 TI | Alldatasheet

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Technical content

MCT8316Z Sensored Trapezoidal Integrated FET BLDC Motor Driver

1 Features

• Three-phase BLDC motor driver with integrated Sensored Trapezoidal control – Hall Sensor based Trapezodial (120°) commutation – Supports Analog or Digital Hall inputs – Configurable PWM modulation: Synchronous/ Asynchronous – Cycle-by-cycle current limit to limit phase current – Supports up to 200-kHz PWM frequency – Active Demagnetization to reduce power losses
• 4.5-V to 35-V operating voltage (40-V abs max)
• High output current capability: 8-A Peak
• Low MOSFET on-state resistance – 95-mΩ RDS(ON) (HS + LS) at TA = 25°C
• Low power sleep mode – 1.5-µA at VVM = 24-V, TA = 25°C
• Integrated built-in current sense – Doesn't require external current sense resistors
• Flexible device configuration options – MCT8316ZR: 5-MHz 16-bit SPI interface for device configuration and fault status – MCT8316ZT: Hardware pin based configuration
• Supports 1.8-V, 3.3-V, and 5-V logic inputs
• Built-in 3.3-V (5%), 30-mA LDO regulator
• Built-in 3.3-V/5-V, 200-mA buck regulator
• Delay compensation reduces duty cycle distortion
• Suite of integrated protection features – Supply undervoltage lockout (UVLO) – Charge pump undervoltage (CPUV) – Overcurrent protection (OCP) – Motor lock protection – Thermal warning and shutdown (OTW/OTSD) – Fault condition indication pin (nFAULT) – Optional fault diagnostics over SPI interface

2 Applications

• Brushless-DC (BLDC) Motor Modules
• Small home appliances
• HVAC motors
• Office automation machines
• Factory automation and robotics

3 Description

The MCT8316Z provides a single-chip code-free sensored trapezoidal solution for customers driving 12- to 24-V brushless-DC motors. The MCT8316Z integrates three 1/2-H bridges with 40-V absolute maximum capability and a very low RDS(ON) of 95 mOhms (high-side and low-side combined) to enable high power drive capability. Current is sensed using an integrated current sensing feature which eliminates the need for external sense resistors. Power management features of an adjustable buck regulator and LDO generate the necessary voltage rails for the device and can be used to power external circuits. MCT8316Z implements sensored trapezoidal control in a fixed-function state machine, so an external microcontroller is not required to spin the brushless- DC motor. The device integrates three analog hall comparators for position sensing to achieve sensored trapezoidal BLDC motor control. The control scheme is highly configurable through hardware pins or register settings ranging from motor current limiting behavior to fault response. The speed can be controlled through a PWM input. There are a large number of protection features integrated into the MCT8316Z, intended to protect the device, motor, and system against fault events. Refer Application Information for design consideration and recommendation on device usage. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) MCT8316ZR(2) VQFN (40) 7.00 mm × 5.00 mm MCT8316ZT VQFN (40) 7.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Device available for preview only. DIRECTION BRAKE SPI Only on SPI variant PWM input SPEED FGOUT Speed feecback nFAULT A B C 4.5V to 35V (40V abs max) 8-A peak output current, typically 12- to 24-V, Buck/LDO out 3.3 or 5.0 V, up to 200mA MCT8316Z MOSFETs Buck/LDO Regulator Integrated Current Sensing Buck/LDO out H H H Hall inputs support: Differenal Hall elements Differenal analog output Hall-effect sensors Digital output Hall-effect sensors Single-ended analog output Hall-effect sensors Sensored Trap Control Simplified Schematic MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

4 Revision History

Changes from , to , (from Revision * (March 2021) to Revision A (October 2021)) Page MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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5 Device Comparison Table

DEVICE PACKAGES INTERFACE BUCK REGULATOR MCT8316ZR(1) 40-pin VQFN (7x5 mm) SPI Yes MCT8316ZT Hardware (1) Device available for preview only. Table 5-1. MCT8316ZR (SPI variant) vs. MCT8316ZT (Hardware variant) configuration comparison Parameters MCT8316ZR (SPI variant) MCT8316ZT (Hardware variant) PWM control mode settings PWM_MODE (4 settings) MODE pin (7 settings) Slew rate settings SLEW (4 settings) SLEW pin (4 settings) Direction settings DIR (2 settings) DIR pin (2 settings) DRVOFF pin configuration DRV_OFF (2 settings) Enabled Current limit threshold ILIMIT pin: AVDD/2 to AVDD/2-0.4V ILIMIT pin: AVDD/2 to AVDD/2-0.4V Current limit configuration ILIM_RECIR (2 settings), PWM_100_DUTY_SEL Recirculation fixed to Brake mode and PWM frequency for 100% duty fixed to 20 kHz CSA GAIN CSA_GAIN (4 settings) Fixed to 0.15 V/A Lead angle settings ADVANCE_LVL (8 settings) ADVANCE pin (7 settings) Buck enable BUCK_DIS (2 settings) Enabled Buck threshold BUCK_SEL(4 settings) VSEL_BK pin (4 settings) Buck configuration: power sequencing, current limit and slew rate BUCK_PS_DIS (2 settings) and BUCK_CL(2 settings) Power sequencing enabled, current limit: 600 mA and slew rate: 1000 V/us FGOUT configuration FGOUT_SEL (4 settings) Fixed to commutation frequency Motor lock configuration: mode, detection and retry timing MTR_LOCK_MODE (4 settings), MTR_LOCK_TDET (4 settings), MTR_LOCK_RETRY (2 settings) Enabled with latched shutdown mode and detection time of 1000 ms Active demagnetization EN_AAR (2 settings) and EN_ASR (2 settings) MODE pin (7 settings) OCP configuration: Mode, OCP_MODE (4 settings) , OCP_LVL (4 settings) ,OCP_DEG (4 settings) and OCP_RETRY (2 settings) Enabled with latched shutdown mode, level is fixed to 16A with 0.6 us deglitch time Overvoltage protection configuration OVP_EN (2 settings) , OVP_SEL (2 settings) Enabled and level is fixed to 34V (typ) Driver delay compensation configuration DLYCMP_EN (2 settings), DLY_TARGET (16 settings) Disabled SDO pin configuration SDO_MODE (2 settings) NA SPI fault configuration SPI_PARITY(2 settings), SPI_SCLK_FLT(2 settings), SPI_ADDR_FLT(2 settings) NA www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: MCT8316Z

6 Pin Configuration and Functions

(Thermal PAD) AVDD AGND SW_BK GND_BK FB_BK CPH CPL AGND CP NC PWM BRAKE nSCS SCLK SDI SDO OUTA OUTA PGND OUTB OUTB PGND OUTC OUTC HPC HPB HPA 9VM VM VM PGND NC DRVOFF nFAULT nSLEEP Figure 6-1. MCT8316ZR 40-Pin VQFN With Exposed Thermal Pad Top View HNA HNC HNB FGOUT ILIM MCT8316ZT (Thermal Pad) AVDD AGND SW_BK GND_BK FB_BK CPH CPL AGND CP NC PWM BRAKE DIR ADVANCE SLEW MODE OUTA OUTA PGND OUTB OUTB PGND OUTC OUTC HPC HPB HPA 9VM VM VM PGND VSEL_BK DRVOFF nFAULT nSLEEP 24 Figure 6-2. MCT8316ZT 40-Pin VQFN With Exposed Thermal Pad Top View MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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TYPE(1) DESCRIPTION NAME MCT8316ZR MCT8316ZT ADVANCE — 35 I Advance angle level setting. This pin is a 7-level input pin set by an external resistor. AGND 2, 26 2, 26 GND Device analog ground. Refer Layout Guidelines for connections recommendation. AVDD 25 25 PWR O 3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30 mA externally. BRAKE 38 38 I High → Brake the motor when High by turning all low side MOSFETs ON Low → normal operation CP 8 8 PWR O Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins. CPH 7 7 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.CPL 6 6 PWR DIR — 36 I Direction pin for setting the direction of the motor rotation to clockwise or counterclockwise. DRVOFF 21 21 I When this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z. FB_BK 3 3 PWR I Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor. FGOUT 40 40 O Motor Speed indicator output. Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. It can be set to different division factor of Hall signals (see FGOUT Signal) GND_BK 4 4 GND Buck regulator ground. Refer Layout Guidelines for connections recommendation. HPA 27 27 I Phase A hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. HPB 29 29 I Phase B hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. HPC 31 31 I Phase C hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. HNA 28 28 I Phase A hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. HNB 30 30 I Phase B hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. HNC 32 32 I Phase C hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs. ILIM 37 37 I Set the threshold for phase current used in cycle by cycle current limit. MODE — 33 I PWM input mode setting. This pin is a 7-level input pin set by an external resistor. NC 1, 24 1 — No connection, open nFAULT 22 22 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on power up or the device will enter test mode nSCS 36 — I Serial chip select. A logic low on this pin enables serial interface communication. nSLEEP 23 23 I Driver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions without entering sleep mode. OUTA 13, 14 13, 14 PWR O Half bridge output A OUTB 16, 17 16, 17 PWR O Half bridge output B www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: MCT8316Z

TYPE(1) DESCRIPTION NAME MCT8316ZR MCT8316ZT OUTC 19, 20 19, 20 PWR O Half bridge output C PGND 12, 15, 18 12, 15, 18 GND Device power ground. Refer Layout Guidelines for connections recommendation. PWM 39 39 I PWM input for motor control. Set the duty cycle and switching frequency of the phase voltage of the motor. SCLK 35 — I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices). SDI 34 — I Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices). SDO 33 — O Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices). SLEW — 34 I Slew rate control setting. This pin is a 4-level input pin set by an external resistor (Hardware devices). SW_BK 5 5 PWR O Buck switch node. Connect this pin to an inductor or resistor. VM 9, 10, 11 9, 10, 11 PWR I Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. VSEL_BK — 24 I Buck output voltage setting. This pin is a 4-level input pin set by an external resistor. Thermal pad GND Must be connected to analog ground. (1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply pin voltage (VM) –0.3 40 V Power supply voltage ramp (VM) 4 V/µs Voltage difference between ground pins (GND_BK, PGND, AGND) –0.3 0.3 V Charge pump voltage (CPH, CP) –0.3 VM + 6 V Charge pump negative switching pin voltage (CPL) –0.3 VM + 0.3 V Switching regulator pin voltage (FB_BK) –0.3 5.75 V Switching node pin voltage (SW_BK) –0.3 VM + 0.3 V Analog regulators pin voltage (AVDD) –0.3 4 V Logic pin input voltage (DRVOFF, PWM, nSCS, nSLEEP, SCLK, SDI) –0.3 5.75 V Logic pin output voltage (nFAULT, SDO) –0.3 5.75 V Output pin voltage (OUTA, OUTB, OUTC) –1 VM + 1 V Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage tempertaure, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VVM 4.5 24 35 V fPWM Output PWM frequency OUTA, OUTB, OUTC 200 kHz IOUT (1) Peak output winding current OUTA, OUTB, OUTC 8 A VIN Logic input voltage DRVOFF, INHx, INLx, nSCS, nSLEEP, SCLK, SDI –0.1 5.5 V VOD Open drain pullup voltage nFAULT, SDO –0.1 5.5 V VSDO Push-pull voltage SDO 2.2 5.5 V IOD Open drain output current nFAULT, SDO 5 mA VVREF Voltage reference pin voltage VREF 2.8 AVDD V TA Operating ambient temperature –40 125 °C TJ Operating Junction temperature –40 150 °C (1) Power dissipation and thermal limits must be observed www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: MCT8316Z

7.4 Thermal Information

THERMAL METRIC(1) MCT8316ZT, MCT8316ZR UNITVQFN (RGF)

40 Pins

RθJA Junction-to-ambient thermal resistance 25.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.2 °C/W RθJB Junction-to-board thermal resistance 7.3 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 7.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVMQ VM sleep mode current VVM > 6 V, nSLEEP = 0, TA = 25 °C 1.5 2.5 µA nSLEEP = 0 2.5 5 µA IVMS VM standby mode current (Buck regulator disabled) nSLEEP = 1, PWM = 0, SPI = 'OFF', BUCK_DIS = 1; 4 10 mA VVM > 6 V, nSLEEP = 1, PWM = 0, SPI = 'OFF', TA = 25 °C, BUCK_DIS = 1; 4 5 mA IVMS VM standby mode current (Buck regulator enabled) VVM > 6 V, nSLEEP = 1, PWM = 0, SPI = 'OFF', IBK = 0, TA = 25 °C, BUCK_DIS = 5 6 mA nSLEEP = 1, PWM = 0, SPI = 'OFF', IBK = 0, BUCK_DIS = 0; 6 10 mA IVM VM operating mode current (Buck regulator disabled) VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C, BUCK_DIS = 1 10 13 mA VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C, BUCK_DIS = 1 18 21 mA nSLEEP =1, fPWM = 25 kHz, BUCK_DIS = 1 11 15 mA nSLEEP =1, fPWM = 200 kHz, BUCK_DIS = 1 17 24 mA IVM VM operating mode current (Buck regulator enabled) VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C, BUCK_DIS = 0; BUCK_PS_DIS = 0 11 13 mA VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C, BUCK_DIS = 0; BUCK_PS_DIS = 0 19 22 mA nSLEEP =1, fPWM = 25 kHz, BUCK_DIS = 0; BUCK_PS_DIS = 0 12 16 mA nSLEEP =1, fPWM = 200 kHz, BUCK_DIS = 0; BUCK_PS_DIS = 0 18 27 mA VAVDD Analog regulator voltage 0 mA ≤ IAVDD ≤ 30 mA; BUCK_PS_DIS = 0 3.1 3.3 3.465 V IAVDD External analog regulator load 30 mA VVCP Charge pump regulator voltage VCP with respect to VM 3.6 4.7 5.2 V fCP Charge pump switching frequency 400 kHz MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPWM_LOW PWM low time required for motor lock detection 200 ms tWAKE Wakeup time VVM > VUVLO, nSLEEP = 1 to outputs ready and nFAULT released 1 ms tSLEEP Sleep Pulse time nSLEEP = 0 period to enter sleep mode 120 µs tRST Reset Pulse time nSLEEP = 0 period to reset faults 20 40 µs BUCK REGULATOR VBK Buck regulator average voltage (LBK = 47 µH, CBK = 22 µF) (SPI Device) VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b), 0 mA ≤ IBK ≤ 200 mA VVM– IBK*(RLBK+ 2)(1) V VBK Buck regulator average voltage (LBK = 22 µH, CBK = 22 µF) (SPI Device) VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b), 0 mA ≤ IBK ≤ 50 mA VVM– IBK*(RLBK+ 2) (1) V VBK Buck regulator average voltage (RBK = 22 Ω, CBK = 22 µF) (SPI Device) VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b) or VVM < 6.0 V (BUCK_SEL = 11b), 0 mA ≤ IBK ≤ 40 mA VVM– IBK*(RBK+2 )(1) V VBK Buck regulator average voltage (LBK = 47 µH, CBK = 22 µF) (HW Device) VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin tied to AGND 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4 VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3 VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA, VSEL_BK pin to AGND 5.2 5.7 6.2 VVM < 6.0 V, 0 mA ≤ IBK ≤ 200 mA VVM– IBK*(RLBK+ 2)(1) V www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: MCT8316Z

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBK Buck regulator average voltage (LBK = 22 µH, CBK = 22 µF) (HW Device) VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin tied to AGND 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA, VSEL_BK pin to AGND 5.2 5.7 6.2 V VVM < 6.0 V, 0 mA ≤ IBK ≤ 50 mA VVM– IBK*(RLBK+ 2)(1) V VBK Buck regulator average voltage (RBK = 22 Ω, CBK = 22 µF) (HW Device) VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin tied to AGND 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to Hi-Z 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA, VSEL_BK pin to AGND 5.2 5.7 6.2 V VVM < 6.0 V, 0 mA ≤ IBK ≤ 40 mA VVM– IBK*(RBK+2 )(1) V VBK_RIP Buck regulator ripple voltage VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck regulator with inductor, LBK = 47 uH, CBK = 22 µF –100 100 mV VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with inductor, LBK = 22 uH, CBK = 22 µF –100 100 mV VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck regulator with resistor; RBK = 22 Ω, CBK = 22 µF –100 100 mV IBK External buck regulator load LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 200 mA LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 200 – IAVDD mA LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 50 mA LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 50 – IAVDD mA RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b 40 mA RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b 40 – IAVDD mA fSW_BK Buck regulator switching frequency Regulation Mode 20 535 kHz Linear Mode 20 535 kHz MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBK_UV Buck regulator undervoltage lockout (SPI Device) VBK rising, BUCK_SEL = 00b 2.7 2.8 2.9 V VBK falling, BUCK_SEL = 00b 2.5 2.6 2.7 V VBK rising, BUCK_SEL = 01b 4.2 4.4 4.55 V VBK falling, BUCK_SEL = 01b 4.0 4.2 4.35 V VBK rising, BUCK_SEL = 10b 2.7 2.8 2.9 V VBK falling, BUCK_SEL = 10b 2.5 2.6 2.7 V VBK rising, BUCK_SEL = 11b 4.2 4.4 4.55 V VBK falling, BUCK_SEL = 11b 4 4.2 4.35 V VBK_UV Buck regulator undervoltage lockout (HW Device) VBK rising, VSEL_BK pin tied to AGND 2.7 2.8 2.9 V VBK falling, VSEL_BK pin tied to AGND 2.5 2.6 2.7 V VBK rising, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 4.3 4.4 4.5 V VBK falling, VSEL_BK pin to 47 kΩ +/- 5% tied to AVDD 4.1 4.2 4.3 V VBK rising, VSEL_BK pin to Hi-Z 2.7 2.8 2.9 V VBK falling, VSEL_BK pin to Hi-Z 2.5 2.6 2.7 V VBK rising, VSEL_BK pin tied to AVDD 4.2 4.4 4.55 V VBK falling, VSEL_BK pin tied to AVDD 4.0 4.2 4.35 V VBK_UV_HYS Buck regulator undervoltage lockout hysteresis Rising to falling threshold 90 200 320 mV IBK_CL Buck regulator Current limit threshold (SPI Device) BUCK_CL = 0b 360 600 900 mA BUCK_CL = 1b 80 150 250 mA IBK_CL Buck regulator Current limit threshold (HW Device) 360 600 900 mA IBK_OCP Buck regulator Overcurrent protection trip point 2 3 4 A tBK_RETRY Overcurrent protection retry time 0.7 1 1.3 ms LOGIC-LEVEL INPUTS (BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK, SDI) VIL Input logic low voltage 0 0.6 V VIH Input logic high voltage Other Pins 1.5 5.5 V nSLEEP 1.6 5.5 V VHYS Input logic hysteresis Other PIns 180 300 420 mV nSLEEP 95 250 420 mV IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 5 V 10 30 µA Other pins, VPIN (Pin Voltage) = 5 V 30 75 µA RPD Input pulldown resistance nSLEEP 150 200 300 kΩ Other pins 70 100 130 kΩ CID Input capacitance 30 pF LOGIC-LEVEL INPUTS (nSCS) VIL Input logic low voltage 0 0.6 V VIH Input logic high voltage 1.5 5.5 V VHYS Input logic hysteresis 180 300 420 mV IIL Input logic low current VPIN (Pin Voltage) = 0 V 75 µA IIH Input logic high current VPIN (Pin Voltage) = 5 V –1 25 µA RPU Input pullup resistance 80 100 130 kΩ CID Input capacitance 30 pF www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: MCT8316Z

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FOUR-LEVEL INPUTS (SLEW, VSEL_BK) VL1 Input mode 1 voltage Tied to AGND 0 0.2*AVD D V VL2 Input mode 2 voltage Hi-Z 0.27*AV DD 0.5*AVDD 0.545*AV DD V VL3 Input mode 3 voltage 47 kΩ +/- 5% tied to AVDD 0.606*AV DD 0.757*AVD D 0.909*AV DD V VL4 Input mode 4 voltage Tied to AVDD 0.945*AV DD AVDD V RPU Input pullup resistance To AVDD 70 100 130 kΩ RPD Input pulldown resistance To AGND 70 100 130 kΩ FOUR-LEVEL INPUTS (OCP/SR) VL1 Input mode 1 voltage Tied to AGND 0 0.09*AV DD V VL2 Input mode 2 voltage 22 kΩ ± 5% to AGND 0.12*AV DD 0.15*AVDD 0.2*AVD D V VL3 Input mode 3 voltage 100 kΩ ± 5% to AGND 0.27*AV DD 0.33*AVDD 0.4*AVD D V VL4 Input mode 4 voltage Hi-Z 0.45*AV DD 0.5*AVDD 0.55*AV DD V VL5 Input mode 5 voltage 100 kΩ ± 5% to AVDD 0.6*AVD D 0.66*AVDD 0.73*AV DD V VL6 Input mode 6 voltage 22 kΩ ± 5% to AVDD 0.77*AV DD 0.85*AVDD 0.9*AVD D V VL7 Input mode 7 voltage Tied to AVDD 0.94*AV DD AVDD V RPU Input pullup resistance To AVDD 80 100 120 kΩ RPD Input pulldown resistance To AGND 80 100 120 kΩ OPEN-DRAIN OUTPUTS (FGOUT, nFAULT) VOL Output logic low voltage IOD = 5 mA 0.4 V IOH Output logic high current VOD = 5 V –1 1 µA COD Output capacitance 30 pF PUSH-PULL OUTPUTS (SDO) VOL Output logic low voltage IOP = 5 mA 0 0.4 V VOH Output logic high voltage IOP = 5 mA 2.2 5.5 V IOL Output logic low leakage current VOP = 0 V –1 1 µA IOH Output logic high leakage current VOP = 5 V –1 1 µA COD Output capacitance 30 pF DRIVER OUTPUTS RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6 V, IOUT = 1 A, TA = 25°C 95 120 mΩ VVM < 6 V, IOUT = 1 A, TA = 25°C 105 130 mΩ VVM > 6 V, IOUT = 1 A, TJ = 150 °C 140 185 mΩ VVM < 6 V, IOUT = 1 A, TJ = 150 °C 145 190 mΩ MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM = 24 V, SLEW = 00b or SLEW pin tied to AGND 14 25 45 V/us VVM = 24 V, SLEW = 01b or SLEW pin to Hi-Z 30 50 80 V/us VVM = 24 V, SLEW = 10b or SLEW pin to 47 kΩ +/- 5% to AVDD 80 125 185 V/us VVM = 24 V, SLEW = 11b or SLEW pin tied to AVDD 130 200 280 V/us SR Phase pin slew rate switching high to low (Falling from 80 % to 20 % VVM = 24 V, SLEW = 00b or SLEW pin tied to AGND 14 25 45 V/us VVM = 24 V, SLEW = 01b or SLEW pin to Hi-Z 30 50 80 V/us VVM = 24 V, SLEW = 10b or SLEW pin to 47 kΩ +/- 5% to AVDD 80 125 185 V/us VVM = 24 V, SLEW = 11b or SLEW pin tied to AVDD 110 200 280 V/us ILEAK Leakage current on OUTx VOUTx = VVM, nSLEEP = 1 5 mA Leakage current on OUTx VOUTx = 0 V, nSLEEP = 1 1 µA tDEAD Output dead time (high to low / low to high) VVM = 24 V, SR = 25 V/µs, HS driver ON to LS driver OFF 1800 3400 ns VVM = 24 V, SR = 50 V/µs, HS driver ON to LS driver OFF 1100 1550 ns VVM = 24 V, SR = 125 V/µs, HS driver ON to LS driver OFF 650 1000 ns VVM = 24 V, SR = 200 V/µs, HS driver ON to LS driver OFF 500 750 ns tPD Propagation delay (high-side / low-side ON/OFF) VVM = 24 V, PWM = 1 to OUTx transisition, SR = 25 V/µs 2000 4550 ns VVM = 24 V, PWM = 1 to OUTx transisition, SR = 50V/µs 1200 2150 ns VVM = 24 V, PWM = 1 to OUTx transisition, SR = 125 V/µs 800 1350 ns VVM = 24 V, PWM = 1 to OUTx transisition, SR = 200 V/µs 650 1050 ns tMIN_PULSE Minimum output pulse width SR = 200 V/µs 600 ns HALL COMPARATORS VICM Input Common Mode Voltage (Hall) 0.5 AVDD – 1.2 V VHYS Voltage hysteresis (SPI Device) HALL_HYS = 0 1.5 5 8 mV HALL_HYS = 1 35 50 75 mV Voltage hysteresis (HW Device) 1.5 5 8 mV ΔVHYS Hall comparator hysteresis difference Between Hall A, Hall B and Hall C comparator –8 8 mV VH(MIN) Minimum Hall Differential Voltage 40 mV II Input leakage current HPX = HNX = 0 V –1 1 μA tHDG Hall deglitch time 0.7 1.15 1.7 μs tHEDG Hall Enable deglitch time During Power up 1.4 μs PULSE-BY-PULSE CURRENT LIMIT VLIM Voltage on VLIM pin for cycle by cycle current limit AVDD/2 AVDD/2– 0.4 V ILIMIT Current limit corresponding to VLIM pin voltage range 0 8 A www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: MCT8316Z

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ILIM_AC Current limit accuracy –10 10 % tBLANK Cycle by cycle current limit blank time 5 µs ADVANCE ANGLE θADV Advance Angle Setting (SPI Device) ADVANCE_LVL = 000 b 0 ° ADVANCE_LVL = 001 b 4 ° ADVANCE_LVL = 010 b 7 ° ADVANCE_LVL = 011 b 11 ° ADVANCE_LVL = 100 b 15 ° ADVANCE_LVL = 101 b 20 ° ADVANCE_LVL = 110 b 25 ° ADVANCE_LVL = 111 b 30 ° θADV Advance Angle Setting (HW Device) Advance pin tied to AGND 0 ° Advance pin tied to 22 kΩ ± 5% to AGND 4 ° Advance pin tied to 100 kΩ ± 5% to AGND 11 ° Advance pin tied to Hi-Z 15 ° Advance pin tied to 100 kΩ ± 5% to AVDD 20 ° Advance pin tied to 22 kΩ ± 5% to AVDD 25 ° Advance pin tied to Tied to AVDD 30 ° PROTECTION CIRCUITS VUVLO Supply undervoltage lockout (UVLO) VM rising 4.3 4.4 4.5 V VM falling 4.1 4.2 4.3 V VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 140 200 350 mV tUVLO Supply undervoltage deglitch time 3 5 7 µs VOVP Supply overvoltage protection (OVP) (SPI Device) Supply rising, OVP_EN = 1, OVP_SEL = 0 32.5 34 35 V Supply falling, OVP_EN = 1, OVP_SEL = 0 31.8 33 34.3 V Supply rising, OVP_EN = 1, OVP_SEL = 1 20 22 23 V Supply falling, OVP_EN = 1, OVP_SEL = 1 19 21 22 V VOVP_HYS Supply overvoltage protection (OVP) (SPI Device) Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V Rising to falling threshold, OVP_SEL = 0 0.7 0.8 0.9 V tOVP Supply overvoltage deglitch time 2.5 5 7 µs VCPUV Charge pump undervoltage lockout (above VM) Supply rising 2.3 2.5 2.7 V Supply falling 2.2 2.4 2.6 V VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 75 100 140 mV VAVDD_UV Analog regulator undervoltage lockout Supply rising 2.7 2.85 3 V Supply falling 2.5 2.65 2.8 V VAVDD_ UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 180 200 240 mV IOCP Overcurrent protection trip point (SPI Device) OCP_LVL = 0b 10 16 20 A OCP_LVL = 1b 15 24 28 A Overcurrent protection trip point (HW Device) OCP pin tied to AGND 10 16 21.5 A OCP pin tied to AVDD 15 24 31 A MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOCP Overcurrent protection deglitch time (SPI Device) OCP_DEG = 00b 0.06 0.3 0.6 µs OCP_DEG = 01b 0.3 0.6 1.1 µs OCP_DEG = 10b 0.7 1.25 1.8 µs OCP_DEG = 11b 1.1 1.6 2.5 µs Overcurrent protection deglitch time (HW Device) 0.06 0.3 0.6 µs tRETRY Overcurrent protection retry time (SPI Device) OCP_RETRY = 0 4 5 6 ms OCP_RETRY = 1 450 500 560 ms tRETRY Overcurrent protection retry time (HW Device) 4 5 6 ms tMTR_ LOCK Motor lock detection time (SPI Device) MOTOR_LOCK_TDET = 00b 270 300 330 ms MOTOR_LOCK_TDET = 01b 450 500 550 ms MOTOR_LOCK_TDET = 10b 900 1000 1100 ms MOTOR_LOCK_TDET = 11b 4500 5000 5500 ms tMTR_ LOCK Motor lock detection time (HW Device) 900 1000 1100 ms tMTR_LOCK_R ETRY Motor lock retry time (SPI Device) MOTOR_LOCK_RETRY = 0b 450 500 550 ms MOTOR_LOCK_RETRY = 1b 4500 5000 5500 ms tMTR_LOCK_R ETRY Motor lock retry time (HW Device) 450 500 550 ms TOTW Thermal warning temperature (FET) Die temperature (TJ) 160 170 180 °C TOTW_HYS Thermal warning hysteresis (FET) Die temperature (TJ) 25 30 35 °C TTSD Thermal shutdown temperature Die temperature (TJ) 175 185 195 °C TTSD_HYS Thermal shutdown hysteresis Die temperature (TJ) 25 30 35 °C TTSD Thermal shutdown temperature (FET) Die temperature (TJ) 170 180 190 °C TTSD_HYS Thermal shutdown hysteresis (FET) Die temperature (TJ) 25 30 35 °C (1) RLBK is resistance of inductor LBK

7.6 SPI Timing Requirements

tREADY SPI ready after power up 1 ms tHI_nSCS nSCS minimum high time 300 ns tSU_nSCS nSCS input setup time 25 ns tHD_nSCS nSCS input hold time 25 ns tSCLK SCLK minimum period 100 ns tSCLKH SCLK minimum high time 50 ns tSCLKL SCLK minimum low time 50 ns tSU_SDI SDI input data setup time 25 ns tHD_SDI SDI input data hold time 25 ns tDLY_SDO SDO output data delay time 25 ns tEN_SDO SDO enable delay time 50 ns tDIS_SDO SDO disable delay time 50 ns www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: MCT8316Z

7.7 SPI Secondary Mode Timings

tHI_nSCS tSU_nSCS tSCLK tSCLKH tSCLKL MSB LSB tHD_SDItSU_SDI Z ZMSB LSB tHD_nSCS tDIS_SDO X X tEN_SDO tDLY_SDO Figure 7-1. SPI Secondary Mode Timing Diagram

7.8 Typical Characteristics

Supply Voltage (V) Active Current (mA) 6 9 12 15 18 21 24 27 30 33 36 F PWM = 25 kHz F PWM = 200 kHz T J = -40  C T J = 25  C T J = 150  C Figure 7-2. Supply current over supply voltage Junction Temperature (  V) R DS(ON) (m  ) -40 -20 0 20 40 60 80 100 120 140 100 110 120 130 140 150 160 Figure 7-3. RDS(ON) (high and low side combined) for MOSFETs over temperature Supply Voltage (V) Buck Efficiency (%) 4 8 12 16 20 24 28 32 36 77.5 82.5 87.5 92.5 97.5 100 T J = -40  C T J = 25  C T J = -150 C Figure 7-4. Buck regulator efficiency over supply voltage Buck Output Load Current (A) Buck Output Voltage (V) 3.25 3.5 3.75 4.25 4.5 4.75 5.25 5.5 5.75 BUCK_SEL = 00b BUCK_SEL = 01b BUCK_SEL = 10b BUCK_SEL = 11b Figure 7-5. Buck regulator output voltage over load current MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8 Detailed Description

8.1 Overview

The MCT8316Z device is an integrated 100-mΩ (combined high-side and low-side MOSFET's on-state resistance) driver for 3-phase motor-drive applications. The device reduces system component count, cost, and complexity by integrating three half-bridge MOSFETs, gate drivers, charge pump, linear regulator for the external load and buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external resistors. The architecture uses an internal state machine to protect against short-circuit events, and protect against dv/dt parasitic turnon of the internal power MOSFET. The MCT8316Z device integrates three-phase sensored trapezoidal commutation using analog or digital hall sensors for position detection. In addition to the high level of device integration, the MCT8316Z device provides a wide range of integrated protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump undervoltage lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck regulator ULVO for MCT8316ZR/T and overtemperature shutdown (OTW and OTSD). Fault events are indicated by the nFAULT pin with detailed information available in the SPI registers on the SPI device version. The MCT8316ZT and MCT8316ZR device are available in 0.5-mm pin pitch, VQFN surface-mount packages. The VQFN package size is 7 mm × 5 mm. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: MCT8316Z

8.2 Functional Block Diagram

ISEN_A ISEN_B ISEN_C Digital Control Overcurrent Protection Thermal Warning Thermal Shutdown Protection PGND PGNDPGNDTPAD Differential Comparators HNB HPB VVM VMCP +CVM1 CVM2 CPH CPL CCPCFLY HNA HPA HNC HPC To Digital Control Hall B Hall C Hall A (Optional) (Optional) (Optional) AVDD Linear Regulator Buck Regulator Regulators VVM VVMCharge Pump To AVDD and Buck Regulator nSLEEP SDO SPI SCLK SDI nSCS Input Control AVDD AVDD BRAKE Interface FGOUT AVDD RFGOUT PWM I/O Control nFAULT AVDD RnFAULT Output Current Sense and Current Limit AV Output Offset Bias AVDD ISEN_A AV ISEN_B AV ISEN_C ILIM SOA SOB SOC GND_BK SW_BK FB_BK AVDD AGND Ext. Load CBK CAVDD1 Ext. Load RBK LBK Replace Inductor (LBK) with Resistor (RBK) for larger external load or to reduce power dissipa on AVDD or Buck Output SDO can be configured to open drain or push pull configuraon Figure 8-1. MCT8316ZR Block Diagram MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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ISEN_A ISEN_B ISEN_C Digital Control Overcurrent Protection Thermal Warning Thermal Shutdown Protection PGND PGNDPGNDTPAD nSLEEP Input Control DIR BRAKE FGOUT AVDD RFGOUT PWM Differential Comparators HNB HPB VVM VMCP +CVM1 CVM2 CPH CPL I/O Control CCPCFLY HNA HPA HNC HPC To Digital Control nFAULT AVDD RnFAULT Output Hall B Hall C Hall A (Optional) (Optional) (Optional) MODE SLEW ADVANCE AVDD Linear Regulator Buck Regulator Regulators VVM VVMCharge Pump To AVDD and Buck Regulator VSEL_BK Current Sense and Current Limit AV Output Offset Bias AVDD ISEN_A AV ISEN_B AV ISEN_C ILIM SOA SOB SOC GND_BK SW_BK FB_BK AVDD AGND Ext. Load CBK CAVDD1 Ext. Load RBK LBK Replace Inductor (LBK) with Resistor (RBK) for larger external load or to reduce power dissipaon AVDD or Buck Output Figure 8-2. MCT8316ZT Block Diagram www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: MCT8316Z

8.3 Feature Description

Table 8-1 lists the recommended values of the external components for the driver. Note TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on power up or the device will enter internal test mode. Table 8-1. MCT8316Z External Components COMPONENTS PIN 1 PIN 2 RECOMMENDED CVM1 VM PGND X5R or X7R, 0.1-µF, TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device CVM2 VM PGND ≥ 10-µF, TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device CCP CP VM X5R or X7R, 16-V, 1-µF capacitor CFLY CPH CPL X5R or X7R, 47-nF, TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin CAVDD AVDD AGND X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to accurately regulate output voltage, capacitor should have effective capacitance between 0.7-µF to 1.3-µF at 3.3-V across operating temperature. CBK SW_BK GND_BK X5R or X7R, 22-µF, buck-output rated capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin LBK SW_BK FB_BK Output inductor RnFAULT VCC nFAULT 5.1-kΩ, Pullup resistor RMODE MODE AGND or AVDD MCT8316Z hardware interface RSLEW SLEW AGND or AVDD MCT8316Z hardware interface RADVANCE ADVANCE AGND or AVDD MCT8316Z hardware interface RVSEL_BK VSEL_BK AGND or AVDD MCT8316Z hardware interface CILIM ILIM AGND X5R or X7R, 0.1-µF, AVDD-rated capacitor (Optional)

8.3.1 Output Stage

The MCT8316Z device consists of an integrated 100-mΩ (combined high-side and low-side FET's on-state resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the motor-supply voltage.

8.3.2 PWM Control Mode (1x PWM Mode)

The MCT8316Z family of devices provides seven different control modes to support various commutation and control methods. The MCT8316Z device provides a 1x PWM control mode for driving the BLDC motor in trapezoidal current-control mode. The MCT8316Z device uses 6-step block commutation tables that are stored internally. This feature lets a three-phase BLDC motor be controlled using a single PWM sourced from a simple controller. The PWM is applied on the PWM pin and determines the output frequency and duty cycle of the half-bridges. The MCT8316Z family of devices supports both analog and digital hall inputs by changing mode input setting. Differential hall inputs should be connected to HPx and HNx pins (see Figure 8-3). Digital hall inputs should be connected to the HPx pins while keeping the HNx pins floating (see Figure 8-4). MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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The half-bridge output states are managed by the HPA, HNA, HPB, HNB, HPC and HNC pins in analog mode and HPA, HPB, HPC in digital mode which are used as state logic inputs. The state inputs are the position feedback of the BLDC motor. The 1x PWM mode usually operates with synchronous rectification (low-side MOSFET recirculation); however, the mode can be configured to use asynchronous rectification (MOSFET body diode freewheeling) as shown below Table 8-2. PWM_MODE Configuration MODE Type MODE Pin (Hardware Variant) Hall Configuration Modulation ASR and AAR Mode Mode 1 Connected to AGND Analog Hall Input Asynchronous ASR and AAR Disabled Mode 2 Connected to AGND with RMODE1 Digital Hall Input Asynchronous ASR and AAR Disabled Mode 3 Connected to AGND with RMODE2 Analog Hall Input Synchronous ASR and AAR Disabled Mode 4 Hi-Z Digital Hall Input Synchronous ASR and AAR Disabled Mode 5 Connected to AVDD with RMODE2 Analog Hall Input Synchronous ASR and AAR Enabled Mode 6 Connected to AVDD with RMODE1 Digital Hall Input Synchronous ASR and AAR Enabled Mode 7 Connected to AVDD Note Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during operation of the power MOSFETs. Set PWM to a low level before changing the MODE pin or PWM_MODE register.

8.3.2.1 Analog Hall Input Configuration

Figure 8-3 shows the connection of Analog Hall inputs to the driver. Analog hall elements are fed to the hall comparators, which zero crossing is used to generate the commutation logic. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: MCT8316Z

(Optional) (Optional) (Optional) DIR BRAKE PWM MCT8316Z MCU_PWM MCU_GPIO MCU_GPIO Analog Hall Comparator Input Figure 8-3. 1x PWM Mode with Analog Hall Input Note Texas Instruments recommends motor direction (DIR) change when the motor is stationary. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.2.2 Digital Hall Input Configuration

Figure 8-4 shows the connection of Digital Hall inputs to the driver. OUTA OUTB OUTC HNB HPB HNA HPA HNC HPC Hall B Hall C Hall A DIR BRAKE PWM MCT8316Z MCU_PWM MCU_GPIO MCU_GPIO Digital Inputs X X X Figure 8-4. 1x PWM Mode with Digital Hall Input

8.3.2.3 Asynchronous Modulation

The DIR pin controls the direction of BLDC motor in either clockwise or counter-clockwise direction. Tie the DIR pin low if this feature is not required. The BRAKE input halts the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when it is pulled high. This brake is independent of the states of the other input pins. Tie the BRAKE pin low if this feature is not required. Table 8-3 shows the configuration in 1x PWM mode with asynchronous modulation. Table 8-3. Asynchronous Modulation HALL INPUTS DRIVER OUTPUTS STATE DIR = 0 DIR = 1 PHASE A PHASE B PHASE C DESCRIPTIONHALL_A /HPA HALL_B /HPB HALL_C /HPC HALL_A /HPA HALL_B /HPB HALL_C /HPC High Side Low Side High Side Low Side High Side Low Side Stop 0 0 0 0 0 0 L L L L L L Stop Align 1 1 1 1 1 1 PWM L L H L H Align 1 1 1 0 0 0 1 L L PWM L L H B → C 2 1 0 0 0 1 1 PWM L L L L H A → C 3 1 0 1 0 1 0 PWM L L H L L A → B 4 0 0 1 1 1 0 L L L H PWM L C → B 5 0 1 1 1 0 0 L H L L PWM L C → A 6 0 1 0 1 0 1 L H PWM L L L B → A www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: MCT8316Z

8.3.2.4 Synchronous Modulation

Table 8-4 shows the configuration in 1x PWM mode with synchronous modulation. Table 8-4. Synchronous Modulation HALL INPUTS DRIVER OUTPUTS STATE DIR = 0 DIR = 1 PHASE A PHASE B PHASE C DESCRIPTIONHALL_A /HPA HALL_B /HPB HALL_C /HPC HALL_A /HPA HALL_B /HPB HALL_C /HPC High Side Low Side High Side Low Side High Side Low Side Stop 0 0 0 0 0 0 L L L L L L Stop Align 1 1 1 1 1 1 PWM !PWM L H L H Align 1 1 1 0 0 0 1 L L PWM !PWM L H B → C 2 1 0 0 0 1 1 PWM !PWM L L L H A → C 3 1 0 1 0 1 0 PWM !PWM L H L L A → B 4 0 0 1 1 1 0 L L L H PWM !PWM C → B 5 0 1 1 1 0 0 L H L L PWM !PWM C → A 6 0 1 0 1 0 1 L H PWM !PWM L L B → A

8.3.2.5 Motor Operation

Figure 8-5 and Figure 8-6 shows the BLDC motor commutation with direction setting (DIR) as 0 and 1 respectively. HA, LB HA, LC HB, LC HB, LA HC, LA HC, LB Van Vbn Vcn 2Œ/3 Idc 2Œ/3 2Œ/3 ia ib ic Hall A Hall B Hall C Figure 8-5. BLDC Motor Commutation with DIR = 0 HB, LA HC, LA HC, LB HA, LB HA, LC HB, LC Van Vbn Vcn 2Œ/3 Idc 2Œ/3 2Œ/3 ia ib ic Hall A Hall B Hall C Figure 8-6. BLDC Motor Commutation with DIR = 1 MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.3 Device Interface Modes

The MCT8316Z family of devices supports two different interface modes (SPI and hardware) to let the end application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one interface version and potentially switch to another with minimal modifications to their design.

8.3.3.1 Serial Peripheral Interface (SPI)

The SPI devices support a serial communication bus that lets an external controller send and receive data with the MCT8316Z. This support lets the external controller configure device settings and read detailed fault information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are described as follows:

• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on the SDI and SDO pins.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin can be configured to either open-drain or push-pull through SDO_MODE.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the MCT8316Z. For more information on the SPI, see the Section 8.5 section.

8.3.3.2 Hardware Interface

Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are ADVANCE, MODE, SLEW and VSEL_BK. This conversion lets the application designer configure the most common device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT pin.

• The MODE pin configures the PWM control mode.
• The SLEW pin configures the slew rate of the output voltage.
• The ADVANCE pin configures the lead angle of the output with respect to hall signals.
• The VSEL_BK pin is used to configure the buck regulator voltage. For more information on the hardware interface, see the Section 8.3.10 section. SDI SDO SCLK SPI Interface nSCS RPU VCC AVDD Figure 8-7. MCT8316ZR SPI Interface MODE ADVANCE SLEW GAIN RSLEW AVDD AVDD AVDD AVDD AVDD RGAIN Hardware Interface AVDD Figure 8-8. MCT8316ZT Hardware Interface www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: MCT8316Z

8.3.4 Step-Down Mixed-Mode Buck Regulator

The MCT8316ZR and MCT8316ZT has an integrated mixed-mode buck regulator in conjunction with AVDD to supply regulated 3.3 V or 5.0 V power for an external controller or system voltage rail. Additionally, the buck output can also be configured to 4.0 V or 5.7 V for supporting the extra headroom for external LDO for generating a 3.3 V or 5.0 V supplies. The output voltage of the buck is set by the VSEL_BK pin in the MCT8316ZT device (hardware variant) and BUCK_SEL bits in the MCT8316ZR device (SPI variant). TThe buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device improves performance during line and load transients by implementing a pulse-frequency current-mode control scheme which requires less output capacitance and simplifies frequency compensation design. To disable the buck regulator, set the BUCK_DIS bit in the MCT8316ZR (SPI variant). The buck regulator cannot be disabled in the MCT8316ZT (hardware variant). Note If the buck regulator is unused, the buck pins SW_BK, GND_BK, and FB_BK cannot be left floating or connected to ground. The buck regulator components L BK/RBK and C BK must be connected in hardware. Table 8-5. Recommended settings for Buck Regulator Buck Mode Buck output voltage Max output current from AVDD (IAVDD) Max output current from Buck (IBK) Buck current limit AVDD power sequencing Inductor - 47 μH 3.3 V or 4.0 V 30 mA 200 mA - IAVDD 600 mA (BUCK_CL = 0b) Not supported (BUCK_PS_DIS = 1) Inductor - 47 μH 5.0 V or 5.7 V 30 mA 200 mA - IAVDD 600 mA (BUCK_CL = 0b) Supported (BUCK_PS_DIS = 0) Inductor - 22 μH 5.0 V or 5.7 V 30 mA 50 mA - IAVDD 150 mA (BUCK_CL = 1b) Not supported (BUCK_PS_DIS = 1) Inductor - 22 μH 3.3 V or 4.0 V 30 mA 50 mA - IAVDD 150 mA (BUCK_CL = 1b) Supported (BUCK_PS_DIS = 0) Resistor - 22 μH 5.0 V or 5.7 V 30 mA 40 mA - IAVDD 150 mA (BUCK_CL = 1b) Not supported (BUCK_PS_DIS = 1) Resistor - 22 μH 3.3 V or 4.0 V 30 mA 40 mA - IAVDD 150 mA (BUCK_CL = 1b) Supported (BUCK_PS_DIS = 0) MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.4.1 Buck in Inductor Mode

The buck regulator in MCT8316Z device is primarily designed to support low inductance of 47µH and 22µH inductors. The 47µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas the 22µH inductor limits the load current to 50 mA. Figure 8-9 shows the connection of buck regulator in inductor mode. LBK SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK Figure 8-9. Buck (Inductor Mode)

8.3.4.2 Buck in Resistor mode

If the external load requirements is less than 40mA, the inductor can be replaced with a resistor. In resistor mode the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode. Figure 8-10 shows the connection of buck regulator in resistor mode. RBK SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK Figure 8-10. Buck (Resistor Mode) www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: MCT8316Z

8.3.4.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to fed to external LDO to generate standard 3.3 V or 5.0 V output rail with higher accuracies. The buck output voltage should be configured to 4 V or 5.5 V to provide for a extra headroom to support the external LDO for generating 3.3 V or 5 V rail as shown in Figure 8-11. This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out voltage. LBK SW_BK GND_BK VM Control CBK VBK (4V / 5.7V) VM FB_BK 3.3V / 5V LDO VIN GND VLDO CLDO GND Ext. Load VLDO (3.3V / 5V) External LDO Figure 8-11. Buck Regulator with External LDO

8.3.4.4 AVDD Power Sequencing on Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce power dissipation internally. The power sequencing mode allows on-the-fly changeover of LDO power supply from DC mains (VM) to buck output (VBK) as shown in Figure 8-12 . This sequencing can be configured through the BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5.0 V or 5.7 V. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK VBK BUCK_PS_DIS Figure 8-12. AVDD Power Sequencing on mixed mode Buck Regulator www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: MCT8316Z

8.3.4.5 Mixed mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control. The output voltage of the buck regulator is compared with the internal reference voltage (V BK_REF) which is internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer voltage control loop. Depending on the comparator output going high (V BK < V BK_REF) or low (V BK > V BK_REF), the high-side power FET of the buck turns on and turna off respectively. An independent current control loop monitors the current in high-side power FET (I BK) and turns off the high-side FET when the current becomes higher than the buck current limit (I BK_CL). This implements a current limit control for the buck regulator. Figure 8-13 shows the architecture of the buck and various control/protection loops. VM IBK_CL LBK SW_BK GND_BK CBK Ext. Load VBK VM FB_BK BUCK_SEL IBK IBK_OCP Buck Reference Voltage Generator VBK VBK_REF IBK IBK Current Limit OC Protection Voltage Control PWM Control and Driver _ VBK_UVLO + VBK UV Protection Buck Control Figure 8-13. Buck Operation and Control Loops MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.5 AVDD Linear Voltage Regulator

A 3.3-V, linear regulator is integrated into the MCT8316Z family of devices and is available for use by external circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the device and additionally, this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting low current (up to 30 mA). The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin. The AVDD nominal, no-load output voltage is 3.3V. AVDD AGND CAVDD External Load REF VM VBK BUCK_PS_DIS FB_BK Figure 8-14. AVDD Linear Regulator Block Diagram Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply (BUCK_PD_DIS = 1) (1) For example, at a V VM of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in Equation P 24 V 3.3 V 20 mA 414 mW u (2) Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as supply (BUCK_PD_DIS = 0) P = V F B _ BK − V A VD D × I A VD D (3) www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: MCT8316Z

8.3.6 Charge Pump

Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power supply to enhance the high-side FETs fully. The MCT8316Z integrates a charge-pump circuit that generates a voltage above the VM supply for this purpose. The charge pump requires two external capacitors for operation. See the block diagram, pin descriptions and see section (Section 8.3 ) for details on these capacitors (value, connection, and so forth). The charge pump shuts down when nSLEEP is low. VM CP CCP VM CPH Charge Pump Control VM CPL CFLY Figure 8-15. MCT8316Z Charge Pump MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.7 Slew Rate Control

An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew rate control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are predominantly determined by the rate of gate charge to internal MOSFETs as shown in Figure 8-16. VM OUTx VCP (Internal) Slew Rate Control Slew Rate Control VCP (Internal) GND Figure 8-16. Slew Rate Circuit Implementation The slew rate of each half-bridge can be adjusted by the SLEW pin in hardware device variant or by using the SLEW bits in SPI device variant. Each half-bridge can be selected to either of a slew rate setting of 25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise time and fall time of the voltage on OUTx pin as shown in Figure 8-17. 20% 80% 20% 80% tfall VM trise VM VOUTx Time Figure 8-17. Slew Rate Timings www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: MCT8316Z

8.3.8 Cross Conduction (Dead Time)

The device is fully protected for any cross conduction of MOSFETs. In half-bridge configuration, the operation of high-side and low-side MOSFETs are ensured to avoid any shoot-through currents by inserting a dead time (tdead). This is implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side MOSFET of same half-bridge as shown in Figure 8-18 and Figure 8-19. VM OUTx GND Gate Control Gate Control VGS VGS HS LS Figure 8-18. Cross Conduction Protection OUTx HS OUTx LS OUTx Gate (VGS_HS) OUTx Gate (VHS_LS) tDEAD Time 10% 10% Figure 8-19. Dead Time MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.9 Propagation Delay

The propagation delay time (t pd) is measured as the time between an input logic edge to change in gate driver voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator delay. The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate drivers. To support multiple control modes, a small digital delay is added as the input command propagates through the device. tPD OUTx Low OUTx High OUTx Time PWM Figure 8-20. Propagation Delay Timing

8.3.9.1 Driver Delay Compensation

MCT8316Z monitors the prorogation delay internally and adds a variable delay on top of it to provide fixed delay as shown in Figure 8-21 and Figure 8-22. Delay compensation feature reduces uncertainty caused in timing of current measurement and also reduces duty cycle distortion caused due to propagation delay. The fixed delay is summation of propagation delay (t PD) caused to internal driver delay and variable delay (t VAR) added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer Table 8-6 for recommendation on configuration for DLY_TARGET for different slew rate settings. Delay compensation is only available in SPI variant MCT8316ZR and can be enabled by configuring DLYCMP_EN and DLY_TARGET. It is disabled in hardware variant MCT8316ZT OUTx Time PWM tPD tVAR DLY_TARGET tPD tVAR DLY_TARGET Figure 8-21. Delay Compensation with current flowing out of phase OUTx Time PWM tPD tVAR DLY_TARGET tPD tVAR DLY_TARGET 1V1V Figure 8-22. Delay Compensation with current flowing into the phase www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: MCT8316Z

Table 8-6. Delay Target Recommendation SLEW RATE DLY_TARGET 200 V/μs DLY_TARGET = 0x5 (1.2 μs) 125 V/μs DLY_TARGET = 0x8 (1.8 μs) 50 V/μs DLY_TARGET = 0xB (2.4 μs) 25 V/μs DLY_TARGET = 0xF (3.2 μs)

8.3.10 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

8.3.10.1 Logic Level Input Pin (Internal Pulldown)

Figure 8-23 shows the input structure for the logic level pins, BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK and SDI. The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep mode to reduce leakage current through internal pull-down resistors. AVDD Logic High INPUT VIH STATE Tied to AVDD CONNECTION VIL Tied to GND Logic Low RPDESD Figure 8-23. Logic-Level Input Pin Structure

8.3.10.2 Logic Level Input Pin (Internal Pullup)

Figure 8-24 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or external resistor. AVDD Logic High INPUT VIH STATE Tied to AVDD CONNECTION VIL Tied to GND Logic Low AVDD ESD RPU Figure 8-24. Logic nSCC

8.3.10.3 Open Drain Pin

Figure 8-25 shows the structure of the open-drain output pins, nFAULT, FGOUT and SDO in open drain mode. The open-drain output requires an external pullup resistor to function properly. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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Figure 8-25. Open Drain

8.3.10.4 Push Pull Pin

Figure 8-26 shows the structure of SDO in push-pull mode. AVDD VOH STATE Pulled-Up STATUS VOL Pulled-Down Logic High OUTPUT Logic Low ESD Figure 8-26. Push Pull

8.3.10.5 Four Level Input Pin

Figure 8-27 shows the structure of the four level input pins, SLEW and VSEL_BK on hardware interface devices. The input can be set with an external resistor. Setting-1 CONTROL Setting-2 Setting-3 Setting-4 VL1 STATE Tied to AGND RESISTANCE VL2 Hi-Z (>2000 kŸWR AGND) VL3

47 NŸ“5%

Figure 8-27. Four Level Input Pin Structure www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: MCT8316Z

8.3.10.6 Seven Level Input Pin

Figure 8-28 shows the structure of the seven level input pins, ADVANCE and MODE , on hardware interface devices. The input can be set with an external resistor. Setting-1 CONTROL Setting-2 Setting-3 Setting-4 AVDDVL1 STATE Tied to AGND RESISTANCE VL2 22 k ± 5% to AGND VL3 100 k ± 5% to AGND VL4 Hi-Z (>2000 kŸ to AGND) AVDD VL5 100 k ± 5% to AVDD VL6

22 NŸ“5%

Figure 8-28. Seven Level Input Pin Structure MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.11 Active Demagnetization

MCT8316Z family of devices has smart rectification features (active demagnetization) which decreases power losses in the device by reducing diode conduction losses. When this feature is enabled, the device automatically turns ON the corresponding MOSFET whenever it detects diode conduction. This feature can be configured with the MODE pins in hardware variants. In SPI device variants this can be configured through EN_ASR and EN_AAR bits. The smart rectification is classified into two categories of automatic synchronous rectification (ASR) mode and automatic asynchronous rectification (AAR) mode which are described in sections below. Note In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active demagnetization. The MCT8316Z device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET output with the supply voltage (VM) threshold, whereas the AD_LS comparator compares with the ground (0-V) threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS comparator trips. This comparator provides a reference point for the operation of active demagnetization feature. VM PGND OUTX Sense FET GAIN SOX VREF I/V Converter Sense FET 0V (GND) VM AD_HS Comparator AD_LS Comparator (To Digital) (To Digital) Figure 8-29. Active Demagnetization Operation Table 8-7 shows the configuration of ASR and AAR mode in the MCT8316Z device. Table 8-7. PWM_MODE Configuration MODE Type MODE Pin (Hardware Variant) ASR and AAR configuration Hall Configuration Modulation ASR and AAR Mode Mode 1 Connected to AGND EN_ASR = 0, EN_AAR = 0 Analog Hall Input Asynchronous ASR and AAR Disabled Mode 2 Connected to AGND with RMODE1 EN_ASR = 0, EN_AAR = 0 Digital Hall Input Asynchronous ASR and AAR Disabled Mode 3 Connected to AGND with RMODE2 EN_ASR = 0, EN_AAR = 0 Analog Hall Input Synchronous ASR and AAR Disabled Mode 4 Hi-Z EN_ASR = 0, EN_AAR = 0 Digital Hall Input Synchronous ASR and AAR Disabled Mode 5 Connected to AVDD with RMODE2 EN_ASR = 1, EN_AAR = 1 Analog Hall Input Synchronous ASR and AAR Enabled www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: MCT8316Z

Table 8-7. PWM_MODE Configuration (continued) MODE Type MODE Pin (Hardware Variant) ASR and AAR configuration Hall Configuration Modulation ASR and AAR Mode Mode 6 Connected to AVDD with RMODE1 EN_ASR = 1, EN_AAR = 1 Digital Hall Input Synchronous ASR and AAR Enabled Mode 7 Connected to AVDD

8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)

The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation and ASR during PWM mode.

8.3.11.1.1 Automatic Synchronous Rectification in Commutation

Figure 8-30 shows the operation of active demagnetization during the BLDC motor commutation. As shown in Figure 8-30 (a), the current is flowing from HA to LC in one commutation state. During the commutation changeover as shown in Figure 8-30 (b), the HC switch is turned on, whereas the commutation current (due to motor inductance) in OUTA flows through the body diode of LA. This incorporates a higher diode loss depending on the commutation current. This commutation loss is reduced by turning on the LA for the commutation time as shown in Figure 8-30 (c). Similarly the operation of high-side FET is realized in Figure 8-30 (d), (e) and (f). MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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(a) Current flowing from HA to LC (b) Decay current with AD disabled (c) Decay current with AD enabled (d) Current flowing from HC to LA (e) Decay current with AD disabled (f) Decay current with AD enabled Figure 8-30. ASR in BLDC Motor Commutation www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: MCT8316Z

Figure 8-31 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode in BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a single commutation cycle. Figure 8-31 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with margin time (tmargin) and ASR mode early stop due to active demag. comparator threshold and delays. Current Limit HA, LB HA, LC HB, LC HB, LA LA HC, LA HC, LB HA HA, LC HB, LC HC, LA HC, LB HA Conducts tdead LA Body Diode Conducts LA Conducts tdead HA Body Diode Conducts 3KDVHµ$¶ Current 3KDVHµ$¶ Current tmargin (a) &RPPXWDWLRQFXUUHQWRI3KDVH³$´ (b) Zoomed waveform of Active Demagnetization Figure 8-31. Current Waveforms for ASR in BLDC Motor Commutation MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode

Figure 8-32 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on the high-side FET, whereas the low-side FET is always off. During the PWM off time, current decays from the low-side FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET during the low-side diode conduction. PWM_HS (Applied) PWM_LS (Applied) Ia PWM_HS (Actual) PWM_LS (Actual) ASR Mode Disabled ASR Mode Enabled Figure 8-32. ASR in PWM Mode www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: MCT8316Z

8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)

Figure 8-33 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a synchronous rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower inductance motors, the current can decay to zero and becomes negative since low side FET is in on-state. This creates a negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the decay is monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves the negative current building in the BLDC motor which results in better noise performance and better thermal management. PWM_HS (Applied) PWM_LS (Applied) Ia PWM_HS (Actual) PWM_LS (Actual) AAR Mode Disabled AAR Mode Enabled Figure 8-33. AAR in PWM Mode MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.12 Cycle-by-Cycle Current Limit

The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the I LIMIT current. This feature restricts motor current to less than the ILIMIT. The current-limit circuitry utilizes the current sense amplifier output of the three phases compared with the voltage at ILIM pin. Figure 8-34 shows the implementation of current limit circuitry. As shown in this figure, the output of current sense amplifiers is combined with star connected resistive network. This measured voltage VMEAS is compared with the external reference voltage e VILIM pin to realize the current limit implementation. The relation between current sensed on OUTX pin and VMEAS threshold is given as: (4) where

• AVDD is 3.3-V LDO output
• OUTX is current flowing into the low-side MOSFET
• GAIN is the CSA_GAIN setting The ILIMIT threshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.4) V. AVDD/2 is minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum threshold of 8A can be configured by applying (AVDD/2 - 0.4) V on ILIM pin. VM PGND OUTA I/V Converter Sense FETGAIN AVDD SOC ILIM To PWM Controller SOB SOA VMEAS VILIM Figure 8-34. Current Limit Implementation When then the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle as shown in Figure 8-35 . The low-side FETs can operate in brake mode or high-Z mode by configuring the ILIM_RECIR bit in the SPI device variant. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: MCT8316Z

Figure 8-35. Cycle-by-Cycle Current-Limit Operation MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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In the MCT8316Z device, when the current limit activates in synchronous rectification mode, the current recirculates through the low-side FETs while the high-side FETs are disabled as shown in Figure 8-36 Moreover, when the current limit activates in asynchronous rectification mode, the current recirculates through the body diodes of the low-side FETs while the high-side FETs are disabled as shown in Figure 8-37 OUTA OUTB OUTC VM HA LA HB LB HC LC XXX Figure 8-36. Brake State OUTA OUTB OUTC VM HA LA HB LB HC LC XXX X X X Figure 8-37. Coast State Note The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking time to prevent false trips of the current-limit circuit. Note During the brake operation, a high-current can flow through the low-side FETs which can eventually trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct and pump brake energy to the VM supply rail. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: MCT8316Z

8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input

In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To overcome this problem, MCT8316Z has built in internal PWM clock which is used to turn high-side FET back on once it is disabled after exceeding I LIMIT threshold. In SPI variant MCT8316ZR, this internal PWM clock can be configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant MCT8316ZT PWM internal clock is set to 20 kHz. Figure 8-38 shows operation with 100 % duty cycle. PWM ILIMIT OUTx Bridge Operating in Brake Mode Time Internal PWM Figure 8-38. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.13 Hall Comparators (Analog Hall Inputs)

Three comparators are provided to process the raw signals from the Hall-effect sensors to commutate the motor. The Hall comparators sense the zero crossings of the differential inputs and pass the information to digital logic. The Hall comparators have hysteresis, and their detect threshold is centered at 0. The hysteresis is defined as shown in Figure 8-39. In addition to the hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for a period of t HDEG after sensing a valid transition. Ignoring these transitions for the t HDEG time prevents PWM noise from being coupled into the Hall inputs, which can result in erroneous commutation. If excessive noise is still coupled into the Hall comparator inputs, adding capacitors between the positive and negative inputs of the Hall comparators may be required. The ESD protection circuitry on the Hall inputs implements a diode to the AVDD pin. Because of this diode, the voltage on the Hall inputs should not exceed the AVDD voltage. Because the AVDD pin is disabled in sleep mode (nSLEEP inactive), the Hall inputs should not be driven by external voltages in sleep mode. If the Hall sensors are powered externally, the supply to the Hall sensors should be disabled if the MCT8316Z device is put into sleep mode. In addition, the Hall sensors' power supply should be powered up after enabling the motor otherwise an invalid Hall state may cause a delay in motor operation. VHYS/2 Hall Differential Voltage (VID/2) Hall Comparator Output tHDEG (Hall Deglitch Time) Hall Comparator Common Mode Voltage (VCM) Time Figure 8-39. Hall Comparators Operation www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: MCT8316Z

8.3.14 Advance Angle

The MCT8316Z includes device an advance angle feature to advance the commutation by a specified electrical angle based on the voltage on the ADVANCE pin (in H/W device variant) or the ADVANCE bits (in SPI device variant). Figure 8-40 shows the operation of advance angle feature. HA, LB HA, LC HB, LC HB, LA HC, LA HC, LB Van Vbn Vcn 2Œ/3 2Œ/3 ia ib ic Hall A Hall B Hall C Before Advance After Advance Advance Angle Figure 8-40. Advance Angle MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.15 FGOUT Signal

The MCT8316Z device also has an open-drain FGOUT signal that can be used for closed-loop speed control of a BLDC motor. This signal includes the information of all three Hall-elements inputs as shown in Section 8.3.15. In the MCT8316ZR (SPI variant), FGOUT can be configured to be a different division factor of Hall signals as shown in Section 8.3.15. In the MCT8316ZT (Hardware variant), the default mode is FGOUT = 00b. Hall Input (HPA, HNA) Hall Input (HPB, HNB) Hall Input (HPC, HNC) Hall Comparator Output (HA) / Digital Hall Input FGOUT (FGOUT_SEL = 00b) Time Hall Comparator Output (HB) / Digital Hall Input Hall Comparator Output (HC) / Digital Hall Input FGOUT (FGOUT_SEL = 01b) FGOUT (FGOUT_SEL = 10b) FGOUT (FGOUT_SEL = 11b) Figure 8-41. FGOUT Signal www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: MCT8316Z

8.3.16 Protections

The MCT8316Z family of devices is protected against VM undervoltage, charge pump undervoltage, and overcurrent events. Table 8-8 summarizes various faults details. Table 8-8. Fault Action and Response (SPI Devices) FAULT CONDITION CONFIGURATION REPORT H-BRIDGE LOGIC RECOVERY VM undervoltage (NPOR) VVM < VUVLO — — Hi-Z Disabled Automatic: VVM > VUVLO_R CLR_FLT, nSLEEP Reset Pulse (NPOR bit) AVDD undervoltage (NPOR) VAVDD < VAVDD_UV — — Hi-Z Disabled Automatic: VAVDD > VAVDD_UV_R CLR_FLT, nSLEEP Reset Pulse (NPOR bit) Buck undervoltage (BUCK_UV) VFB_BK < VBK_UV — nFAULT Active Active Automatic: VFB_BK > VBUCK_UV_R CLR_FLT, nSLEEP Reset Pulse (BUCK_UV bit) Charge pump undervoltage (VCP_UV) VCP < VCPUV — nFAULT Hi-Z Active Automatic: VVCP > VCPUV CLR_FLT, nSLEEP Reset Pulse (VCP_UV bit) OverVoltage Protection (OVP) VVM > VOVP OVP_EN = 0b None Active Active No action (OVP Disabled) OVP_EN = 1b FAULT Hi-Z Active Automatic: VVM < VOVP CLR_FLT, nSLEEP Reset Pulse (OVP bit) Overcurrent Protection (OCP) IPHASE > IOCP OCP_MODE = 00b nFAULT Hi-Z Active Latched: CLR_FLT, nSLEEP Reset Pulse (OCP bits) OCP_MODE = 01b nFAULT Hi-Z Active Retry: tRETRY OCP_MODE = 10b nFAULT Active Active Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits) OCP_MODE = 11b None Active Active No action Buck Overcurrent Protection (BUCK_OCP) IBK > IBK_OC — nFAULT Active Active Retry: tRETRY SPI Error (SPI_FLT) SCLK fault and ADDR fault SPI_FLT_REP = 0b nFAULT Active Active Automatic: CLR_FLT, nSLEEP Reset Pulse (SPI_FLT bit) SPI_FLT_REP = 1b None Active Active No action OTP Error (OTP_ERR) OTP reading is erroneous — nFAULT Hi-Z Active Latched: Power Cycle, nSLEEP Reset Pulse Motor Lock (MTR_LOCK) No Hall Signals > tMTR_LOCK_TDET MTR_LOCK_MODE = 00b nFAULT Hi-Z Active Latched: CLR_FLT, nSLEEP Pulse (MTR_LOCK bit) MTR_LOCK_MODE = 01b nFAULT Hi-Z Active Retry: tMTR_LOCK_RETRY MTR_LOCK_MODE = 10b nFAULT Active Active Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits) MTR_LOCK_MODE = 11b None Active Active No action Thermal warning (OTW) TJ > TOTW OTW_REP = 0b None Active Active No action OTW_REP = 1b nFAULT Active Active Automatic: TJ < TOTW – THYS CLR_FLT, nSLEEP Pulse (OTW bit) Thermal shutdown (OTSD) TJ > TOTSD — nFAULT Hi-Z Active Automatic: TJ < TOTSD – THYS CLR_FLT, nSLEEP Pulse (OTS bit) MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.3.16.1 VM Supply Undervoltage Lockout (NPOR)

If at any time the input supply voltage on the VM pin falls lower than the V UVLO threshold (VM UVLO falling threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in Figure 8-42. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST). VUVLO (min) falling VUVLO (max) falling VUVLO (max) rising VUVLO (min) rising VVM DEVICE ON DEVICE OFF DEVICE ON Time Figure 8-42. VM Supply Undervoltage Lockout

8.3.16.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on AVDD pin falls lower than the V AVDD_UV threshold, all of the integrated FETs, driver charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).

8.3.16.3 BUCK Undervoltage Lockout (BUCK_UV)

If at any time the voltage on VFB_BK pin falls lower than the V BK_UV threshold, the integrated FETs of the buck regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally. The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices. Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).

8.3.16.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the V CPUV threshold voltage of the charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (t RST). The CPUV protection is always enabled in both hardware and SPI device varaints.

8.3.16.5 Overvoltage Protections (OV)

If at any time input supply voltage on the VM pins rises higher lower than the V OVP threshold voltage, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released) when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: MCT8316Z

reset pulse (tRST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. On hardware interface devices, the OVP protection is always enabled and set to a 34-V threshold. The OVP threshold is also programmable on the SPI device variant. The OVP threshold can be set to 20-V or 32-V based on the OVP_SEL bit. VOVP (min) falling VOVP (max) falling VOVP (max) rising VOVP (min) rising VVM nFAULT DEVICE ON DEVICE OFF DEVICE ON Time Figure 8-43. Over Voltage Protection

8.3.16.6 Overcurrent Protection (OCP)

A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a FET exceeds the I OCP threshold for longer than the t OCP deglitch time, an OCP event is recognized and action is done according to the OCP_MODE bit. On hardware interface devices, the I OCP threshold is fixed at 16-A threshold , the t OCP_DEG is fixed at 0.6-µs, and the OCP_MODE bit is configured for latched shutdown. On SPI devices, the I OCP threshold is set through the OCP_LVL SPI register, the t OCP_DEG is set through the OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP automatic retry, OCP report only, and OCP disabled.

8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)

After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP, and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST). MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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nFAULT Pulled High Fault Condition nFAULT Released Peak Current due to deglitch time Clear Fault Figure 8-44. Overcurrent Protection - Latched Shutdown Mode

8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)

After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP, and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again automatically (driver operation and the nFAULT pin is released) after the t RETRY time elapses. After the t RETRY time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST). IOCP tOCP nFAULT Time IOUTx nFAULT Pulled High Fault Condition nFAULT Released Peak Current due to deglitch time tRETRY Figure 8-45. Overcurrent Protection - Automatic Retry Mode

8.3.16.6.3 OCP Report Only (OCP_MODE = 10b)

No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the nFAULT pin low and latching the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. The MCT8316Z continues to operate as usual. The external controller manages the overcurrent condition by acting www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: MCT8316Z

appropriately. The reporting clears (nFAULT pin is released) when the OCP condition clears and a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

8.3.16.6.4 OCP Disabled (OCP_MODE = 11b)

No action occurs after a OCP event in this mode.

8.3.16.7 Buck Overcurrent Protection

A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the current across the buck regulator FET exceeds the I BK_OCP threshold for longer than the t BK_OCP deglitch time, an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after a buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low. The FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again automatically (driver operation and the nFAULT pin is released) after the t BK_RETRY time elapses. The FAULT, BK_FLT, and BUCK_OCP bits stay latched until the tRETRY period expires.

8.3.16.8 Motor Lock (MTR_LOCK)

During motor is in lock condition the hall signals will be not available, so a Motor Lock event is sensed by monitoring the hall signals. If the hall signals are not present for for longer than the tMTR_LOCK, a MTR_LCK event is recognized and action is done according to the MTR_LOCK_MODE bits. On hardware interface devices, the tMTR_LOCK threshold is set to 1000-ms, and the MTR_LOCK_MODE bit is configured for latched shutdown. On SPI devices, the tMTR_LOCK threshold is set through the MTR_LOCK_TDET register and the MTR_LOCK_MODE bit can operate in four different modes: MTR_LOCK latched shutdown, MTR_LOCK automatic retry, MTR_LOCK report only, and MTR_LOCK disabled.

8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)

After a motor lock event in this mode, all FETs are disabled and the nFAULT pin is driven low. The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again (driver operation and the nFAULT pin is released) when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)

After a motor lock event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again automatically (driver operation and the nFAULT pin is released) after the t MTR_LOCK_RETRY time elapses. The FAULT and MTR_LOCK bits stay latched until the tMTR_LOCK_RETRY period expires.

8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)

No protective action occurs after a MTR_LOCK event in this mode. The motor lock event is reported by driving the nFAULT pin low and latching the FAULT and MTR_LOCK bits high in the SPI registers. The MCT8316Z continues to operate as usual. The external controller manages the motor lock condition by acting appropriately. The reporting clears (nFAULT pin is released) when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).

8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)

No action occurs after a MTR_LOCK event in this mode. 8.3.16.8.5 Note The motor lock detection scheme requires the PWM off-time (t PWM_OFF) to be lower than the motor lock detection time (tMTR_LOCK)

8.3.16.9 Thermal Warning (OTW)

If the die temperature exceeds the trip point of the thermal warning (T OTW), the OT bit in the IC status (IC_STAT) register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device performs no additional action and continues to function. In this case, the nFAULT pin releases when the die temperature decreases below the hysteresis point of the thermal warning (T OTW_HYS). The OTW bit remains set until cleared through the CLR_FLT bit or an nSLEEP reset pulse (t RST) and the die temperature is lower than thermal warning trip (TOTW). Note Over temperature warning is not reported on nFAULT pin by default.

8.3.16.10 Thermal Shutdown (OTS)

If the die temperature exceeds the trip point of the thermal shutdown limit (T OTS), all the FETs are disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in the IC status (IC_STAT) register and OTS bit in the status register is set. Normal operation starts again (driver operation and the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays latched high indicating that a thermal event occurred until a clear fault command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST). This protection feature cannot be disabled. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: MCT8316Z

8.4 Device Functional Modes

8.4.1 Functional Modes

8.4.1.1 Sleep Mode

The nSLEEP pin manages the state of the MCT8316Z family of devices. When the nSLEEP pin is low, the device goes to a low-power sleep mode. In sleep mode, all FETs are disabled, sense amplifiers are disabled, buck regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled, and the SPI bus is disabled. The t SLEEP time must elapse after a falling edge on the nSLEEP pin before the device goes to sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The t WAKE time must elapse before the device is ready for inputs. In sleep mode and when VVM < VUVLO, all MOSFETs are disabled. Note During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the tSLEEP or tWAKE time. Note TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on power up or the device will enter internal test mode.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the V VM voltage is greater than the V UVLO voltage, the device goes to operating mode. The t WAKE time must elapse before the device is ready for inputs. In this mode the charge pump, AVDD regulator, buck regulator, and SPI bus are active.

8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)

In the case of device latched faults, the MCT8316Z family of devices goes to a partial shutdown state to help protect the power MOSFETs and system. When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should fall with the t RST time window or else the device will start the complete shutdown sequence. The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.

8.4.2 DRVOFF functionality

When DRVOFF pin is pulled high, all six MOSFETs are disabled. If nSLEEP is high when the DRVOFF pin is high, the charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults such as OCP will be inactive. DRVOFF pin independently disables MOSFETs which will stop motor commutation irrespective of status of PWM input pin. Note Since DRVOFF pin independently disables MOSFET, it can trigger fault condition resulting in nFAULT getting pulled low. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.5 SPI Communication

8.5.1 Programming

On MCT8316Z SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out diagnostic information. The SPI operates in secondary mode and connects to a controller. The SPI input data (SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit word, with a 8 bits of status information (STAT register) and 8-bit register data. A valid frame must meet the following conditions:

• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK pin.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following the 8-bit status data. The SPI registers are reset to the default settings on power up and when the device is enters sleep mode

8.5.1.1 SPI Format

The SDI input data word is 16 bits long and consists of the following format:

• 1 read or write bit, W (bit B15)
• 6 address bits, A (bits B14 through B9)
• Parity bit, P (bit B8). Parity bit is set such that the SDI input data word has even number of 1s and 0s
• 8 data bits, D (bits B7 through B0) The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the register being accessed. For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being written to. For a read command (W0 = 1), the response word is the data currently in the register being read. A1 D1 SDO SDI nSCS S1 R1 Figure 8-46. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: MCT8316Z

Figure 8-47. Table 8-9. SDI Input Data Word Format R/W ADDRESS Parity DATA B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W0 A5 A4 A3 A2 A1 A0 P D7 D6 D5 D4 D3 D2 D1 D0 Table 8-10. SDO Output Data Word Format STATUS DATA B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 nSCS SCLK SDI SDO MSB LSB Z ZMSB LSB X X Capture Point Propagate Point Figure 8-48. SPI Secondary Timing Diagram SPI Error Handling SPI Frame Error (SPI_SCLK_FLT: If the nSCS gets deasserted before the end of 16-bit frame, SPI frame error is detected and SPI_SCLK_FLT bit is set in STAT2. The SPI_SCLK_FLT status bit is latched and can be cleared when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse SPI Address Error (SPI_ADDR_FLT) : If an invalid address is provided in the ADDR field of the input SPI data on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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address that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC. The SPI_ADDR_FLT status bit is latched and can be cleared when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: MCT8316Z

8.6 Register Map

8.6.1 STATUS Registers

STATUS Registers lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in STATUS Registers should be considered as reserved locations and the register contents should not be modified. Table 8-11. STATUS Registers Offset Acronym Register Name Section 0h IC_Status_Register IC Status Register Section 8.6.1.1 1h Status_Register_1 Status Register 1 Section 8.6.1.2 2h Status_Register_2 Status Register 2 Section 8.6.1.3 Complex bit access types are encoded to fit into small table cells. STATUS Access Type Codes shows the codes that are used for access types in this section. Table 8-12. STATUS Access Type Codes Access Type Code Description Read Type R R Read R-0 R Read Returns 0s Reset or Default Value -n Value after reset or the default value MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.1.1 IC_Status_Register Register (Offset = 0h) [Reset = 00h]

IC_Status_Register is shown in IC_Status_Register Register and described in IC_Status_Register Register Field Descriptions. Return to the STATUS Registers. Figure 8-49. IC_Status_Register Register 7 6 5 4 3 2 1 0 MTR_LOCK BK_FLT SPI_FLT OCP NPOR OVP OT FAULT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 8-13. IC_Status_Register Register Field Descriptions Bit Field Type Reset Description

7 MTR_LOCK R 0h Motor Lock Staus Bit

0h = No motor lock is detected 1h = Motor lock is detected

6 BK_FLT R 0h Buck Fault Bit

0h = No buck regulator fault condition is detected 1h = Buck regulator fault condition is detected

5 SPI_FLT R 0h SPI Fault Bit

0h = No SPI fault condition is detected 1h = SPI Fault condition is detected

4 OCP R 0h Over Current Protection Status Bit

0h = No overcurrent condition is detected 1h = Overcurrent condition is detected

3 NPOR R 0h Supply Power On Reset Bit

0h = Power on reset condition is detected on VM 1h = No power-on-reset condition is detected on VM

2 OVP R 0h Supply Overvoltage Protection Status Bit

0h = No overvoltage condition is detected on VM 1h = Overvoltage condition is detected on VM

1 OT R 0h Overtemperature Fault Status Bit

0h = No overtemperature warning / shutdown is detected 1h = Overtemperature warning / shutdown is detected

0 FAULT R 0h Device Fault Bit

0h = No fault condition is detected 1h = Fault condition is detected www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: MCT8316Z

8.6.1.2 Status_Register_1 Register (Offset = 1h) [Reset = 00h]

Status_Register_1 is shown in Status_Register_1 Register and described in Status_Register_1 Register Field Descriptions. Return to the STATUS Registers. Figure 8-50. Status_Register_1 Register 7 6 5 4 3 2 1 0 OTW OTS OCP_HC OCL_LC OCP_HB OCP_LB OCP_HA OCP_LA R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 8-14. Status_Register_1 Register Field Descriptions Bit Field Type Reset Description

7 OTW R 0h Overtemperature Warning Status Bit

0h = No overtemperature warning is detected 1h = Overtemperature warning is detected

6 OTS R 0h Overtemperature Shutdown Status Bit

0h = No overtemperature shutdown is detected 1h = Overtemperature shutdown is detected

5 OCP_HC R 0h Overcurrent Status on High-side switch of OUTC

0h = No overcurrent detected on high-side switch of OUTC 1h = Overcurrent detected on high-side switch of OUTC

4 OCL_LC R 0h Overcurrent Status on Low-side switch of OUTC

0h = No overcurrent detected on low-side switch of OUTC 1h = Overcurrent detected on low-side switch of OUTC

3 OCP_HB R 0h Overcurrent Status on High-side switch of OUTB

0h = No overcurrent detected on high-side switch of OUTB 1h = Overcurrent detected on high-side switch of OUTB

2 OCP_LB R 0h Overcurrent Status on Low-side switch of OUTB

0h = No overcurrent detected on low-side switch of OUTB 1h = Overcurrent detected on low-side switch of OUTB

1 OCP_HA R 0h Overcurrent Status on High-side switch of OUTA

0h = No overcurrent detected on high-side switch of OUTA 1h = Overcurrent detected on high-side switch of OUTA

0 OCP_LA R 0h Overcurrent Status on Low-side switch of OUTA

0h = No overcurrent detected on low-side switch of OUTA 1h = Overcurrent detected on low-side switch of OUTA MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.1.3 Status_Register_2 Register (Offset = 2h) [Reset = 00h]

Status_Register_2 is shown in Status_Register_2 Register and described in Status_Register_2 Register Field Descriptions. Return to the STATUS Registers. Figure 8-51. Status_Register_2 Register 7 6 5 4 3 2 1 0 RESERVED OTP_ERR BUCK_OCP BUCK_UV VCP_UV SPI_PARITY SPI_SCLK_FLT SPI_ADDR_FL T R-0-0h R-0h R-0h R-0h R-0h R-0-0h R-0h R-0h Table 8-15. Status_Register_2 Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R-0 0h Reserved

6 OTP_ERR R 0h One Time Programmabilty Error

0h = No OTP error is detected 1h = OTP Error is detected

5 BUCK_OCP R 0h Buck Regulator Overcurrent Staus Bit

0h = No buck regulator overcurrent is detected 1h = Buck regulator overcurrent is detected

4 BUCK_UV R 0h Buck Regulator Undervoltage Staus Bit

0h = No buck regulator undervoltage is detected 1h = Buck regulator undervoltage is detected

3 VCP_UV R 0h Charge Pump Undervoltage Status Bit

0h = No charge pump undervoltage is detected 1h = Charge pump undervoltage is detected

2 SPI_PARITY R-0 0h SPI Parity Error Bit

0h = No SPI parity error is detected 1h = SPI parity error is detected

1 SPI_SCLK_FLT R 0h SPI Clock Framing Error Bit

0h = No SPI clock framing error is detected 1h = SPI clock framing error is detected

0 SPI_ADDR_FLT R 0h SPI Address Error Bit

0h = No SPI address fault is detected (due to accessing non-user register) 1h = SPI address fault is detected www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: MCT8316Z

8.6.2 CONTROL Registers

CONTROL Registers lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in CONTROL Registers should be considered as reserved locations and the register contents should not be modified. Table 8-16. CONTROL Registers Offset Acronym Register Name Section 3h Control_Register_1 Control Register 1 Section 8.6.2.1 4h Control_Register_2A Control Register 2A Section 8.6.2.2 5h Control_Register_3 Control Register 3 Section 8.6.2.3 6h Control_Register_4 Control Register 4 Section 8.6.2.4 7h Control_Register_5 Control Register 5 Section 8.6.2.5 8h Control_Register_6 Control Register 6 Section 8.6.2.6 9h Control_Register_7 Control Register 7 Section 8.6.2.7 Ah Control_Register_8 Control Register 8 Section 8.6.2.8 Bh Control_Register_9 Control Register 9 Section 8.6.2.9 Ch Control_Register_10 Control Register 10 Section 8.6.2.10 Complex bit access types are encoded to fit into small table cells. CONTROL Access Type Codes shows the codes that are used for access types in this section. Table 8-17. CONTROL Access Type Codes Access Type Code Description Read Type R R Read R-0 R Read Returns 0s Write Type W W Write W1C W Write 1 to clear WAPU W APU Write Atomic write with password unlock Reset or Default Value -n Value after reset or the default value MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.2.1 Control_Register_1 Register (Offset = 3h) [Reset = 00h]

Control_Register_1 is shown in Control_Register_1 Register and described in Control_Register_1 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-52. Control_Register_1 Register 7 6 5 4 3 2 1 0 RESERVED REG_LOCK R-0-0h R/WAPU-0h Table 8-18. Control_Register_1 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R-0 0h Reserved 2-0 REG_LOCK R/WAPU 0h Register Lock Bits 0h = No effect unless locked or unlocked 1h = No effect unless locked or unlocked 2h = No effect unless locked or unlocked 3h = Write 011b to this register to unlock all registers 4h = No effect unless locked or unlocked 5h = No effect unless locked or unlocked 6h = Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x03h bits 2-0. 7h = No effect unless locked or unlocked www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: MCT8316Z

8.6.2.2 Control_Register_2A Register (Offset = 4h) [Reset = 60h]

Control_Register_2A is shown in Control_Register_2A Register and described in Control_Register_2A Register Field Descriptions. Return to the CONTROL Registers. Figure 8-53. Control_Register_2A Register 7 6 5 4 3 2 1 0 RESERVED SDO_MODE SLEW PWM_MODE CLR_FLT R/W-1h R/W-1h R/W-0h R/W-0h W1C-0h Table 8-19. Control_Register_2A Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 1h Reserved

5 SDO_MODE R/W 1h SDO Mode Setting

0h = SDO IO in Open Drain Mode 1h = SDO IO in Push Pull Mode 4-3 SLEW R/W 0h Slew Rate Settings 0h = Slew rate is 25 V/µs 1h = Slew rate is 50 V/µs 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs 2-1 PWM_MODE R/W 0h Device Mode Selection 0h = Asynchronous rectification with analog Hall 1h = Asynchronous rectification with digital Hall 2h = Synchronous rectification with analog Hall 3h = Synchronous rectification with digital Hall

0 CLR_FLT W1C 0h Clear Fault

0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.2.3 Control_Register_3 Register (Offset = 5h) [Reset = 46h]

Control_Register_3 is shown in Control_Register_3 Register and described in Control_Register_3 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-54. Control_Register_3 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED PWM_100_DU TY_SEL OVP_SEL OVP_EN RESERVED OTW_REP R-0-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h Table 8-20. Control_Register_3 Register Field Descriptions Bit Field Type Reset Description

6 RESERVED R/W 1h Reserved

5 RESERVED R/W 0h Reserved

4 PWM_100_DUTY_SEL R/W 0h Freqency of PWM at 100% Duty Cycle

0h = 20KHz 1h = 40KHz

3 OVP_SEL R/W 0h Overvoltage Level Setting

0h = VM overvoltage level is 34-V 1h = VM overvoltage level is 22-V

2 OVP_EN R/W 1h Overvoltage Enable Bit

0h = Overvoltage protection is disabled 1h = Overvoltage protection is enabled

1 RESERVED R/W 1h Reserved

0 OTW_REP R/W 0h Overtemperature Warning Reporting Bit

0h = Over temperature reporting on nFAULT is disabled 1h = Over temperature reporting on nFAULT is enabled www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: MCT8316Z

8.6.2.4 Control_Register_4 Register (Offset = 6h) [Reset = 10h]

Control_Register_4 is shown in Control_Register_4 Register and described in Control_Register_4 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-55. Control_Register_4 Register 7 6 5 4 3 2 1 0 DRV_OFF OCP_CBC OCP_DEG OCP_RETRY OCP_LVL OCP_MODE R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h Table 8-21. Control_Register_4 Register Field Descriptions Bit Field Type Reset Description

7 DRV_OFF R/W 0h Driver OFF Bit

0h = No Action 1h = Enter Low Power Standby Mode

6 OCP_CBC R/W 0h OCP PWM Cycle Operation Bit

0h = OCP clearing in PWM input cycle change is disabled 1h = OCP clearing in PWM input cycle change is enabled 5-4 OCP_DEG R/W 1h OCP Deglitch Time Settings 0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.6 µs 2h = OCP deglitch time is 1.25 µs 3h = OCP deglitch time is 1.6 µs

3 OCP_RETRY R/W 0h OCP Retry Time Settings

0h = OCP retry time is 5 ms 1h = OCP retry time is 500 ms

2 OCP_LVL R/W 0h Overcurrent Level Setting

0h = OCP level is 16 A 1h = OCP level is 24 A 1-0 OCP_MODE R/W 0h OCP Fault Options 0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retrying fault 2h = Overcurrent is report only but no action is taken 3h = Overcurrent is not reported and no action is taken MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.2.5 Control_Register_5 Register (Offset = 7h) [Reset = 00h]

Control_Register_5 is shown in Control_Register_5 Register and described in Control_Register_5 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-56. Control_Register_5 Register 7 6 5 4 3 2 1 0 RESERVED ILIM_RECIR RESERVED RESERVED EN_AAR EN_ASR CSA_GAIN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 8-22. Control_Register_5 Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R/W 0h Reserved

6 ILIM_RECIR R/W 0h Current Limit Recirculation Settings

0h = Current recirculation through FETs (Brake Mode) 1h = Current recirculation through diodes (Coast Mode)

4 RESERVED R/W 0h Reserved

3 EN_AAR R/W 0h Active Asynshronous Rectification Enable Bit

0h = AAR mode is disabled 1h = AAR mode is enabled

2 EN_ASR R/W 0h Active Synchronous Rectification Enable Bit

0h = ASR mode is disabled 1h = ASR mode is enabled 1-0 CSA_GAIN R/W 0h Current Sense Amplifier's Gain Settings 0h = CSA gain is 0.15 V/A 1h = CSA gain is 0.3 V/A 2h = CSA gain is 0.6 V/A 3h = CSA gain is 1.2 V/A www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: MCT8316Z

8.6.2.6 Control_Register_6 Register (Offset = 8h) [Reset = 00h]

Control_Register_6 is shown in Control_Register_6 Register and described in Control_Register_6 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-57. Control_Register_6 Register 7 6 5 4 3 2 1 0 RESERVED RESERVED BUCK_PS_DIS BUCK_CL BUCK_SEL BUCK_DIS R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 8-23. Control_Register_6 Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R-0 0h Reserved

4 BUCK_PS_DIS R/W 0h Buck Power Sequencing Disable Bit

0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled

3 BUCK_CL R/W 0h Buck Current Limit Setting

0h = Buck regulator current limit is set to 600 mA 1h = Buck regulator current limit is set to 150 mA 2-1 BUCK_SEL R/W 0h Buck Voltage Selection 0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V

0 BUCK_DIS R/W 0h Buck Disable Bit

0h = Buck regulator is enabled 1h = Buck regulator is disabled MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.2.7 Control_Register_7 Register (Offset = 9h) [Reset = 01h]

Control_Register_7 is shown in Control_Register_7 Register and described in Control_Register_7 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-58. Control_Register_7 Register 7 6 5 4 3 2 1 0 RESERVED HALL_HYS BRAKE_MODE COAST BRAKE DIR R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h Table 8-24. Control_Register_7 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R-0 0h Reserved

4 HALL_HYS R/W 0h Hall Comparator Hysteresis Settings

0h = 5 mV 1h = 50 mV

3 BRAKE_MODE R/W 0h Brake Mode Setting

0h = Device operation is braking in brake mode 1h = Device operation is coasting in brake mode

2 COAST R/W 0h Coast Bit

0h = Device coast mode is disabled 1h = Device coast mode is enabled

1 BRAKE R/W 0h Brake Bit

0h = Device brake mode is disabled 1h = Device brake mode is enabled

0 DIR R/W 1h Direction Bit

0h = Motor direction is set to clockwise direction 1h = Motor direction is set to anti-clockwise direction www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: MCT8316Z

8.6.2.8 Control_Register_8 Register (Offset = Ah) [Reset = 41h]

Control_Register_8 is shown in Control_Register_8 Register and described in Control_Register_8 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-59. Control_Register_8 Register 7 6 5 4 3 2 1 0 FG_MODE RESERVED MTR_LOCK_R ETRY MTR_LOCK_TDET MTR_LOCK_MODE R/W-1h R-0-0h R/W-0h R/W-0h R/W-1h Table 8-25. Control_Register_8 Register Field Descriptions Bit Field Type Reset Description 7-6 FG_MODE R/W 1h Electrical Frequency Generation Output Mode Bits 0h = FGOUT frequency is commutation frequency 1h = FGOUT frequency is 1/2 of commutation frequency 2h = FGOUT frequency is 1/4 of commutation frequency 3h = FGOUT frequency is 1/8 of commutation frequency

5 RESERVED R-0 0h Reserved

4 MTR_LOCK_RETRY R/W 0h Motor Lock Retry Time Settings

0h = 500 ms 1h = 5000 ms 3-2 MTR_LOCK_TDET R/W 0h Motor Lock Detection Time Settings 0h = 300 ms 1h = 500 ms 2h = 1000 ms 3h = 5000 ms 1-0 MTR_LOCK_MODE R/W 1h Motor Lock Fault Options 0h = Motor lock causes a latched fault 1h = Motor lock causes an automatic retrying fault 2h = Motor lock is report only but no action is taken 3h = Motor lock is not reported and no action is taken MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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8.6.2.9 Control_Register_9 Register (Offset = Bh) [Reset = 00h]

Control_Register_9 is shown in Control_Register_9 Register and described in Control_Register_9 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-60. Control_Register_9 Register 7 6 5 4 3 2 1 0 RESERVED ADVANCE_LVL R-0-0h R/W-0h Table 8-26. Control_Register_9 Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R-0 0h Reserved 2-0 ADVANCE_LVL R/W 0h Phase Advance Setting 0h = 0° 1h = 4° 2h = 7° 3h = 11° 4h = 15° 5h = 20° 6h = 25° 7h = 30° www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: MCT8316Z

8.6.2.10 Control_Register_10 Register (Offset = Ch) [Reset = 00h]

Control_Register_10 is shown in Control_Register_10 Register and described in Control_Register_10 Register Field Descriptions. Return to the CONTROL Registers. Figure 8-61. Control_Register_10 Register 7 6 5 4 3 2 1 0 RESERVED DLYCMP_EN DLY_TARGET R-0-0h R/W-0h R/W-0h Table 8-27. Control_Register_10 Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R-0 0h Reserved

4 DLYCMP_EN R/W 0h Driver Delay Compensation enable

0h = Disable 1h = Enable 3-0 DLY_TARGET R/W 0h Delay Target for Driver Delay Compensation 0h = 0 us 1h = 0.4 us 2h = 0.6 us 3h = 0.8 us 4h = 1 us 5h = 1.2 us 6h = 1.4 us 7h = 1.6 us 8h = 1.8 us 9h = 2 us Ah = 2.2 us Bh = 2.4 us Ch = 2.6 us Dh = 2.8 us Eh = 3 us Fh = 3.2 us MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The MCT8316Z can be used to drive Brushless-DC motors. The following design procedure can be used to configure the MCT8316Z. nSLEEP ILIM PWM DIR AVDD AGND VVM VMCP CPH CPL OUTA OUTB OUTC DRVOFF 10 nF CAVDD BRAKE 1 µF 0.1 µF 10 µF ADVANCE MODE VSEL_BK SLEW Hardware interface PWM Control Input nFAULTGP-I RPU2 GP-O GP-O GP-O PWM Control Module PGND VCC 0.1 µF GP-O GP-ODriver Control MCT8316ZT Microcontroller HNAHPA Hall Sensors (Optional) HNBHPB HNCHPC Hall B Hall C Hall A FGOUT RCL1 RCL2 RPU1 GND_BK SW_BK FB_BK CBK External Load RBK LBK Replace Inductor (LBK) with Resistor (RBK) for larger external load or to reduce power dissipaon GP-I AVDD Figure 9-1. Primary Application Schematics for MCT8316ZT (hardware variant) www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: MCT8316Z

1 µF 0.1 µF 10 µF SDO SCLK SDI nSCS GP-I GP-O GP-O GP-O SPISPI PWM Control Input nFAULTGP-I RPU2 GP-O GP-O GP-O PWM Control Module PGND VCC 0.1 µF GP-O GP-ODriver Control MCT8316ZR Microcontroller HNAHPA Hall Sensors (Optional) HNBHPB HNCHPC Hall B Hall C Hall A FGOUT RCL1 RCL2 RPU1 GND_BK SW_BK FB_BK CBK External Load RBK LBK Replace Inductor (LBK) with Resistor (RBK) for larger external load or to reduce power dissipaon GP-I Figure 9-2. Primary Application Schematics for MCT8316ZR (SPIvariant)

9.2 Hall Sensor Configuration and Connection

The combinations of Hall sensor connections in this section are common connections.

9.2.1 Typical Configuration

The Hall sensor inputs on the MCT8316Z device can interface with a variety of Hall sensors. Typically, a Hall element is used, which outputs a differential signal. To use this type of sensor, the AVDD regulator can be used to power the Hall sensor. Figure 9-3 shows the connections. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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(Optional) Figure 9-3. Typical Hall Sensor Configuration Because the amplitude of the Hall-sensor output signal is very low, capacitors are often placed across the Hall inputs to help reject noise coupled from the motor. Capacitors with a value of 1 nF to 100 nF are typically used.

9.2.2 Open Drain Configuration

Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the MCT8316Z device, with the addition of a few resistors as shown in Figure 9-4. HPx AVDD HNx Hall Sensor VCC OUT To Other HNx Inputs 1 to 4.7 NŸ 1 to 4.7 NŸ GND Hall Comparator Figure 9-4. Open-Drain Hall Sensor Configuration The negative (HNx) inputs are biased to AVDD / 2 by a pair of resistors between the AVDD pin and ground. For open-collector Hall sensors, an additional pullup resistor to the VREG pin is required on the positive (HPx) input. Again, the AVDD output can usually be used to supply power to the Hall sensors. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: MCT8316Z

9.2.3 Series Configuration

Hall elements are also connected in series or parallel depending upon the Hall sensor current/voltage requirement. Figure 9-5 shows the series connection of Hall sensors powered via the MCT8316Z internal LDO (AVDD). This configuration is used if the current requirement per Hall sensor is high (>10 mA) HPA HNA Hall Sensor INP OUTP INN OUTN HPB HNB HPC HNC Hall Sensor INP OUTP INN OUTN Hall Sensor INP OUTP INN OUTN GND AVDD RSE Hall Comparator Hall Comparator Hall Comparator Figure 9-5. Hall Sensor Connected in Series Configuration MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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9.2.4 Parallel Configuration

Figure 9-6 shows the parallel connection of Hall sensors which is powered by the AVDD. This configuration can be used if the current requirement per Hall sensor is low (<10 mA). HPA HNA Hall Sensor INP OUTP INN OUTN HPB HNB HPC HNC GND Hall Sensor INP OUTP INN OUTN GND Hall Sensor INP OUTP INN OUTN GND AVDD RPL Hall Comparator Hall Comparator Hall Comparator Figure 9-6. Hall Sensors Connected in Parallel Configuration www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: MCT8316Z

9.3 Typical Applications

9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit

In this application, the MCT8316Z is used to drive a brushless-DC motor with current limit up to 100% duty cycle. The following design procedure can be used to configure the MCT8316Zin current limit mode.

9.3.1.1 Detailed Design Procedure

Table 9-1 lists the example input parameters for the system design. Table 9-1. Design Parameters DESIGN PARAMETERS REFERENCE EXAMPLE VALUE Supply voltage VVM 24 V Motor peak current IPEAK 2 A PWM Frequency fPWM 50 kHz Slew Rate Setting SR 200 V/µs Buck regulator output voltage VBK 3.3 V

9.3.1.1.1 Motor Voltage

Brushless-DC motors are typically rated for a certain voltage (for example 12 V or 24 V). Operating a motor at a higher voltage corresponds to a lower drive current to obtain the same motor power. Operating at lower voltages generally allows for more accurate control of phase currents. The MCT8316Z functions down to a supply of 4.5V. A higher operating voltage also corresponds to a higher obtainable rpm. The MCT8316Z allows for a range of possible operating voltages because of a maximum VM rating of 40 V.

9.3.1.1.2 Using Active Demagnetization

Active demagnetization reduces power losses in the device by turning on the MOSFETs automatically when the body diode starts conducting to reduce diode conduction losses. It is used in trapezoidal commutation when switching commutation states (turning a high-side MOSFET off and another high-side MOSFET on while keeping a low-side MOSFET on). Active demagnetization is enabled when EN_ASR and EN_AAR bits are set in the SPI variant or MODE pin is set to Mode 5, Mode 6, or Mode 7 in the H/W variant. When switching commutation states with active demagnetization disabled, dead time is inserted and the low-side MOSFET’s body diode conducts while turning another high-side MOSFET on to continue sourcing current through the motor. This conduction period causes higher power losses due to the forward-bias voltage of the diode and slower dissipation of current. Figure 9-7 shows the body diode conducting when switching commutation states. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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9.3.1.1.3 Using Delay Compensation

Differences in delays of dead time and propagation delay can cause mismatch in the output timings of PWMs, which can lead to duty cycle distortion. In order to accommodate differences in propagation delay between various input conditions, the MCT8316ZRintegrates a Delay Compensation feature. Delay Compensation is used to match delay times for currents going into and out of phase by adding a variable delay time (t var) to match a preset target delay time. This delay time is configurable in SPI devices, and it is recommended in the datasheets to choose a target delay time that is equal to the propagation delay time plus the driver dead time (tpd + tdead). For an example of Delay Compensation implementation, please visit the Delay and Dead Time in Integrated MOSFET Drivers application note.

9.3.1.1.4 Using the Buck Regulator

In the MCT8316Z, the buck regulator components must be populated whether the buck is used or unused. If unused, Resistor Mode should be configured by placing a small value resistor of 22-ohm for R BK and a 6.3-V rated, 22-uF capacitor for C BK to minimize board space and reduce component cost. To disable the buck regulator, set the BUCK_DIS in the SPI variant. The buck cannot be disabled in the Hardware variant. If the buck regulator is used, either the Inductor or Resistor Mode can be selected. Inductor Mode allows a 22-uH or 47-uH inductor be used for L BK. CBK is recommended to be 22-uF. Ensure an appropriate inductor is chosen to allow for maximum peak saturation current at a 20% inductance drop since the buck can supply up to 600-mA external current. Resistor Mode allows for power to be dissipated in an external resistor if the load requirement is less than 40-mA. Ensure the resistor is rated for the power dissipation required at worst case VM voltage dropout. See Equation 5, Equation 6, and Equation 7 to calculate the resistor power rating required for a 24-V rated system, 3.3V buck output voltage, and 20-mA load current. P R BK > V M − V BK × I BK (5) P R BK > 24 V − 3.3 V × 20 m A (6) P R _ BK > 0.434 W (7)

9.3.1.1.5 Power Dissipation and Junction Temperature Losses

To calculate the junction temperature of the MCT8316Z from power losses, use Equation 8 . Note that the thermal resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB layers, copper thickness on top and bottom layers, and the PCB area. T J ℃ = P l os s W × θ J A W + T A ℃ (8) MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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9.3.1.2 Application Curves

Figure 9-9. Device Powerup with VM Figure 9-10. Device Powerup with nSLEEP Figure 9-11. Driver PWM Operation Figure 9-12. Driver PWM Operation with FGOUT Figure 9-13. Power Management Figure 9-14. Driver PWM with Active Demagnetization (ASR and AAR) www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: MCT8316Z

Figure 9-15. Driver PWM Operation with Current Limit Figure 9-16. Driver 100% Operation with Current Chopping MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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10 Power Supply Recommendations

10.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including:

• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed dc, brushless DC, stepper)
• The motor braking method The inductance between the power supply and the motor drive system limits the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Local Bulk Capacitor Parasitic Wire Inductance Motor Driver Power Supply Motor Drive System VM GND IC Bypass Capacitor Figure 10-1. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: MCT8316Z

11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current. Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed closely to device pins. The high-current device outputs should use wide metal traces. To reduce noise coupling and EMI interference from large transient currents into small-current signal paths, grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to reduce voltage offsets and maintain gate driver performance. The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate the I2 × RDS(on) heat that is generated in the device. To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and improve thermal dissipation from the die surface. Separate the SW_BUCK and FB_BUCK traces with ground separation to reduce buck switching from coupling as noise into the buck outer feedback loop. Widen the FB_BUCK trace as much as possible to allow for faster load switching. Recommended Layout Example for VQFN Package shows a layout example for the MCT8316Z. MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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11.2 Layout Example

Recommended Layout Example for VQFN Package www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: MCT8316Z

11.3 Thermal Considerations

The MCT8316Z has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C (minimally) disables the device until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

11.3.1 Power Dissipation

The power dissipated in the output FET resistance, or RDS(on) dominates power dissipation in the MCT8316Z. At start-up and fault conditions, this current is much higher than normal running current; remember to take these peak currents and their duration into consideration. The total device dissipation is the power dissipated in each of the three half-H-bridges added together. The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking. Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when sizing the heatsink. A summary of equations for calculating each loss is shown below for trapezoidal control. Table 11-1. MCT8316Z Power Losses for Trapezoidal Control Loss type Trapezoidal Standby power Pstandby = VM x IVM_TA LDO (from VM) PLDO = (VM-VAVDD) x IAVDD FET conduction PCON = 2 x IRMS(trap) x Rds,on(TA) FET switching PSW = IPK(trap) x VPK(trap) x trise/fall x fPWM Diode Pdiode = IRMS(trap) x Vdiode X tdiode x fPWM Buck PBK = 0.97 x VBK x IBK MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 www.ti.com

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12 Device and Documentation Support

12.1 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.2 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.4 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com MCT8316Z SLVSF18A – MARCH 2021 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: MCT8316Z

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224999/A 06/2019 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RGF0040E A 0.08 C

0.1 C A B

0.05 C B SYMM SYMM PIN 1 INDEX AREA 5.1 4.9 7.1 6.9

1 MAX

0.05 0.00 C (0.1) TYP 3.7±0.1 5.7±0.1 40X 0.3 0.2 3.5 5.5 36X 0.5 40X 0.5 0.3 PIN 1 ID (OPTIONAL) 13 20 3340 SEATING PLANE

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224999/A 06/2019 www.ti.com VQFN - 1 mm max heightRGF0040E PLASTIC QUAD FLAT PACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK

0.07 MAX

0.07 MIN

(1.35) (1.25) (0.625) (0.975) (3.7) (5.7) (3.5) (5.5) 40X (0.25) 36X (0.5) 40X (0.6) (Ø0.2) VIA TYP (R0.05) TYP 13 20 3340

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224999/A 06/2019 www.ti.com VQFN - 1 mm max heightRGF0040E PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 69% PRINTED COVERAGE BY AREA SCALE: 12X SYMM SYMM (3.5) (5.5) 40X (0.25) 36X (0.5) 40X (0.6) (Ø0.2) VIA TYP (R0.05) TYP 13 20 3340 12X (1.15) 12X (1.05) (0.675) (1.35) (1.25)

www.ti.com 16-Oct-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples MCT8316Z0TRGFR ACTIVE VQFN RGF 40 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 MCT 8316ZT PMCT8316Z0TRGFR ACTIVE VQFN RGF 40 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 16-Oct-2021 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2021 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MCT8316Z0TRGFR VQFN RGF 40 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Oct-2021 Pack Materials-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224999/B 06/2021 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RGF0040E A 0.08 C 0.05 C B SYMM SYMM PIN 1 INDEX AREA 5.1 4.9 7.1 6.9 0.05 0.00 C (0.1) TYP 3.8 3.6 5.8 5.6 40X 0.3 0.2 3.5 5.5 36X 0.5 40X 0.5 0.3 PIN 1 ID (OPTIONAL) 13 20 3340 SEATING PLANE

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224999/B 06/2021 www.ti.com VQFN - 1 mm max heightRGF0040E PLASTIC QUAD FLAT PACK- NO LEAD SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X SOLDER MASK DETAILS NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK (5.5)(5.7) 40X (0.25) 40X (0.6) (3.5) (3.7) (1.25) (1.35) (4.8) (6.8) SYMM (Ø0.2) TYP VIA (R0.05) TYP

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224999/B 06/2021 www.ti.com VQFN - 1 mm max heightRGF0040E PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 69% PRINTED COVERAGE BY AREA SCALE: 12X SYMM 13 20 (5.5) 40X (0.25) 40X (0.6) (3.5) 36X (0.5) (1.35) (0.675) (4.8) (6.8) SYMM 12X (1.15) (1.25)12X (1.05) (R0.05) TYP

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