MCS1632R005FER

FAN54161 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• Integrated Back−to−Back Common Source N−channel MOSFETs with Combined RON = 11 m/C0087
• Maximum Input V oltage Tolerance of +22 V
• Reverse Input V oltage Tolerance of −2 V
• External N−channel MOSFET Drive Capability with Tolerance up to +32 V
• Regulation Modes ♦ Charge Current ♦ Input Current ♦ Output V oltage ♦ Battery Cell V oltage
• Hardware−based Safety Protections ♦ Input Over−V oltage ♦ Input Under−V oltage ♦ Output Over−V oltage ♦ Input Over−Current ♦ Die Over−Temperature ♦ Internal Switch Short
• 10−bit High−accuracy ADC Typical Applications
• Mobile Devices
• Tablets www.onsemi.com See detailed ordering and shipping information on page 2 of this data sheet.

ORDERING INFORMATION

12 = Specific Device Code KK = Lot Run Code X = Year Code Y = 2−Weeks Date Code Z = Assembly Plant Code MARKING DIAGRAM

www.onsemi.com Block Diagram and Application Schematic Figure 1. FAN54161, External FET, Switching Charger, Battery Pack with Exposed Cell, and External Fuel Gauge

9 Channel

Part Number Temperature Range Package Packing Method FAN54161UCX −40°C to +85°C 2.78 x 3.06 mm, 42−Bump WLCSP Tape and Reel

Figure 2. WLCSP−42 Pin Assignments Table 1. PIN DESCRIPTIONS pin to the appropriate logic level before power is applied (VBUS or VOUT). Connect to the ground node in the PCB. set this pin will assert low. disabled, and I2C communication is not available. If not used, it is recommended to pull−up to VOUT. Pull−up with a resistor to logic supply voltage. Pull−up with a resistor to logic supply voltage. for protection, connect VBUS to the source of this MOSFET. VBUS has an internal 100 /C0087 pulldown resistor that is active when VBUSPD_EN = 1.

Connect to the battery pack. SNSN physically as close as possible to the negative terminal of the pack. VBATREG(TH), the voltage across SNSP and SNSN is regulated to the threshold. VBATREG(TH), the voltage across SNSP and SNSN is regulated to the threshold. Connect to the negative side of the sense resistor in series with the cell. SRN and SRP is regulated to the threshold. Connect to the positive side of the sense resistor in series with the cell. SRN and SRP is regulated to the threshold. TS_BUS to an external 2.4 V supply. TS_BAT to an external 2.4 V supply. VUSB pin must be left floating. Do not connect this pin to GND. the OVP_C pin should be tied to VBUS or float. Do not connect this pin to GND.

Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) should not be assumed, damage may occur and reliability may be affected.

1. All voltages are referenced to ground, GND, unless otherwise noted.
2. Pins should be protected with external TVS devices when tested for IEC compliance.

Table 3. THERMAL CHARACTERISTICS given ambient temperature TA. Table 4. RECOMMENDED OPERATING RANGES (Note 3) 1.8 V to 4.5 V, TA = −40°C to 85°C, unless otherwise noted. the Recommended Operating Ranges limits may affect device reliability.

1. All voltages are measured relative to GND.

Table 5. ELECTRICAL CHARACTERISTICS (Notes 4, 5, 6, 7) Unless otherwise specified: according to the circuit in Figure 1;

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

1. V IH(max) = VPU + 0.5 V or VBAT whichever is lower
2. It is assumed that the SCL and SDA pins are open drain with external pull −ups resistors tied to an external supply VPU.

200 mV on noise margin to the required VOL(max) of the transmitter.

1. I 2C standard specifies VOL(max) for VPU /C0118 2.0 V to be 0.2 x VPU.
2. Guaranteed by design. Not tested in production.
3. Regulation Mode control will reduce t OFF_IBUSOCP.

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

www.onsemi.com Functional Specifications Charging Bypass Switch with Regulation Mode Overview The FAN54161 is designed to be placed in a system that requires high current charging for a large battery. It is essentially a high current bypass switch with protection that provides a path from a charging source (adapter) to the battery directly through a low resistance path. In order to ensure safety of the battery as well as the system, the FAN54161 features multiple hardware protection mechanisms. Most of these result in the path from the charging source to the battery being opened. Examples of these are input over −voltage, over −current through the switch and reverse current. Some of the parameters are monitored and regulated such that they are at or below a programmed threshold. This is achieved by controlling the gate of the power switch. However, this mode of operation is only meant to be used temporarily while the system controller/host reacts to this and corrects the system configuration to allow the switch to return to a bypass mode (fully−on state). Many of the hardware protection mechanisms have I programmable thresholds, enable/disable controls, interrupts with masks and status bits. The product block diagram (Figure 1) provides an illustrative overview of the functionality within the FAN54161. The FAN54161 also utilizes a fully independent charge pump based gate drive circuit to control an optional external N−channel MOSFET for an additional level of input protection from over voltage faults up to 32 V applied at the USB port. Bypass Switch Modes of Operation Broadly speaking, the FAN54161 has four modes of bypass switch operation. 1. OFF: This represents a lack of power to the FAN54161. 2. SHUTDOWN: Valid power is applied to one of VBUS or VOUT but the RESET_N input is asserted low. In this state, no communication with the FAN54161 is possible and the switch is forced open. 3. STANDBY: Valid power is applied to one of VBUS or VOUT and the RESET_N input is de−asserted high. I2C communication is enabled, but, the switch is not programmed to close. 4. SWITCH ENABLED: As evidenced by the name, the FAN54161 bypass switch is closed in this state. From the STANDBY state, when the SW_EN bit is written with a 1, the FAN54161 enters the SWITCH ENABLED state. In this state, the switch’s gate is controlled by the control circuit of the FAN54161 to be either fully on (bypass mode) or partially on (regulation mode) based on the parameters being monitored. Power−up and Reset (VBUS and VOUT) When power is first applied to either VBUS or VOUT, an internal power−on reset (POR) circuit ensures the default state of all registers and circuits and keeps the switch in the OPEN state. Power for all internal logic circuits comes from the higher of VBUS and VOUT. This allows the FAN54161 to be I2C programmable even with just one of the supplies present (VBUS or VOUT). The RESET_N pin is an active−low reset input. When the RESET_N pin is asserted low externally, the FAN54161 remains in a reset state and does not support I communication. The switch is forced OPEN. This corresponds to the SHUTDOWN state. The RESET_N pin being low also forces the ADC in the FAN54161 to its SHUTDOWN state. In order to properly control and operate the FAN54161, a valid supply must be present at VBUS or VOUT and the RESET_N pin must be de−asserted (logic high state). VUSB Power The VUSB pin does not affect POR behavior of the FAN54161 and should be considered a completely independent power domain with respect to VBUS and VOUT. Hardware Fault Protection The FAN54161 features hardware safety protection monitors, some of which can cause the switch to OPEN if enabled. Other than VBUS UVLO and IC Thermal Shutdown, each hardware safety protection monitor has an independently programmable enable bit. The high current switch is closed by setting SW_EN = 1. Before the switch closes, though, the IC is checked against the following safety protection thresholds:

• VBUS UVLO
• VBUS OVP
• VOUT OVP
• VDROP OVP
• Thermal Shutdown If any of these safety protection monitors are enabled and the associated fault is triggered, the switch is not allowed to close and the appropriate interrupt bit is set to report the fault to the system controller/host. If no faults are triggered when SW_EN bit is set, the switch is closed. When the switch is closed, all enabled safety protection monitors are armed. With the exception of VOREG, VBA TREG, IBA TREG, and IBUSREG, if any enabled fault is triggered, the switch is opened and its appropriate interrupt bit is set to 1. Refer to Figure 10 for details. When the switch is closed, if a VOREG, VBATREG, IBATREG, or IBATREG fault is triggered, the internal logic drives the gate of the bypass switch such that the current or voltage does not exceed its regulation threshold. Additionally, its appropriate interrupt bit is set to 1. It is

on again. Refer to Figure 11 for details. enabled and programmed to convert this channel. Figure 10. Hardware Protection Logic Diagram

Table 6. HARDWARE FAULT PROTECTION ENTRY SUMMARY

Table 7. HARDWARE FAULT PROTECTION EXIT (RECOVERY) SUMMARY

1. Isolate VBUS from VOUT by opening the bypass
2. Set the VBUSOVP_INT bit to 1 and pull the

VBUS has fallen below V BUSOVP(TH) − V BUSOVP(HYS). condition will result in a SW_EN self clear. according to the ADC_EN setting. VBUS < VBUSUVLO(TH) will keep the bypass switch open.

www.onsemi.com VDROP Alarm Reporting While the bypass switch is closed, if the voltage measured across the switch (V BUS − V OUT) exceeds the VDROPALM(TH) threshold for more than tVDROPALMGLTCH, the FAN54161 sets the VDROPALM_INT bit to 1 and pulls the INT_N pin low. This alerts the host processor that the FAN54161 is operating in a condition that may soon trigger a VDROP OVP fault which would force the switch to open. This alert feature warns the host processor to reprogram the Travel Adapter or the FAN54161’s charge parameter settings to prevent a VDROP OVP fault from triggering. VDROP Over−Voltage Protection While the bypass switch is closed, if the voltage measured across the switch (V BUS − V OUT) exceeds the VDROPOVP(TH) threshold for more than t VDROPGLTCH, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the VBUSOVP_INT bit to 1 and pull the INT_N pin low If a VDROP OVP fault occurs, the host processor should reprogram the FAN54161’s charging parameter settings to prevent a VDROP OVP fault from reoccurring the next time the bypass switch is closed. Once the VDROP OVP fault is removed, the host processor must set SW_EN to 1 in order to close the bypass switch again. The VDROP OVP protection is disabled by default to allow the switch to close even if the difference between VBUS and VOUT is greater than the VDROP OVP threshold. If VDROP OVP protection is enabled before the switch is closed, care should be taken to ensure that VBUS −VOUT is less than the VDROP OVP threshold, otherwise the VDROP OVP protection will prevent the switch from closing when writing SW_EN to 1. The ADC is not affected by this fault and operates according to the ADC_EN setting. Input Connector Over−Temperature Fault The FAN54161 can monitor the temperature of the input connector with an external NTC thermistor tied from the TS_BUS pin to ground. This protection prevents bypass charging from continuing if the input connector temperature rises to a dangerous level. A TS_BUS pullup resistor tied to an externally supplied reference voltage (recommended V EXTREF = 2.4 V) along with the NTC thermistor generate a temperature dependent voltage on the TS_BUS pin. The FAN54161’s ADC must be enabled to measure and digitally compare the voltage at TS_BUS to a programmed TBUS_TH threshold. The ADC’s measurement of the TS_BUS voltage is monitored by the TBUSADC register. A digital comparison is made between the TBUSADC register contents and the TBUS_TH threshold. If the TBUSADC value falls below the TBUS_TH threshold for more than t TBUS_TBAT_GLTCH, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the TBUSOTP_INT bit to 1 and pull the INT_N pin low There is no automatic recovery from this fault, and the host must program SW_EN to 1 to close the switch again. The ADC is not affected by this fault and operates according to the ADC_EN setting. This digital comparison scheme does not restrict the use of NTC thermistor type or pullup resistor value. The desired TBUS_TH threshold can be programmed based on the external components selected by the system designer. Battery Over−Temperature Fault The F AN54161 can monitor the temperature of the battery by measuring the battery pack’s thermistor output pin. This protection prevents bypass charging from continuing if the battery temperature rises to a dangerous level. A TS_BAT pull−up resistor tied to an externally supplied reference voltage (recommended V EXTREF = 2.4 V) along with the battery pack’s NTC thermistor generate a temperature dependent voltage on the TS_BAT pin. The FAN54161’s ADC must be enabled to measure and digitally compare the voltage at TS_BAT to a programmed TBAT_TH threshold. The ADC’s measurement of the TS_BAT voltage can be monitored by the TBATADC register. A digital comparison is made between the TBATADC register contents and the TBAT_TH threshold. If the TBATADC value falls below the TBAT_TH threshold for more than t TBUS_TBAT_GLTCH, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the TBATOTP_INT bit to 1 and pull the INT_N pin low There is no automatic recovery from this fault, and the host must program SW_EN to 1 to close the switch. The ADC is not affected by this fault and operates according to the ADC_EN setting. This digital comparison scheme does not restrict the use of NTC thermistor type or pullup resistor value. The desired TBAT_TH threshold can be programmed based on the external components selected by the system designer. Thermal Shutdown Protection When the FAN54161’s junction temperature exceeds the thermal shutdown threshold (TSDN(TH)), the IC will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the TSDN_INT bit to 1 and pull the INT_N pin low

www.onsemi.com 4. Disable ADC conversion and ADC reference. ADC enters standby state, maintains ADC_EN=1 There is no automatic recovery from this fault, and the host must program SW_EN to 1 to close the switch again. IBUS Over Current Protection If the input current through the bypass switch exceeds the programmed IBUSOCP(TH) threshold, the bypass switch will be forced open to protect the IC, battery, and system from an over−current fault condition. The IBUSOCP_MODE control bit determines the manner in which the bypass switch will react to an IBUS over−current fault event. The IC internally monitors the IBUS current through the bypass switch. When IBUSOCP_MODE=0 and IBUS > IBUSOCP(TH) for more than tIBUSOCPGLTCH, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the IBUSOCP_INT bit to 1 and pulls the INT_N pin low 4. Rely on the host processor to send a SW_EN=1 command to close the switch again When IBUSOCP_MODE=1 and I BUS > IBUSOCP(TH) for more than tIBUSOCPGLTCH, the FAN54161 will: 1. Enter the Hiccup Mode cycle and isolate VBUS and VOUT by opening the bypass switch 2. Maintain SW_EN =1 during hiccup mode retry 3. Wait 100 ms, close the bypass switch to check if the IBUS over−current condition is removed ♦ If the IBUS over−current condition is removed, the bypass switch will remain closed, keep SW_EN=1, and exit the Hiccup Mode cycle ♦ If the IBUS over−current condition remains, the Hiccup Mode cycle (starting from step 1) is repeated up to 6 more times ♦ If the IBUS over−current condition remains after 6 attempts, the IBUSOCP_INT interrupt bit is set to 1 and the INT_N pin is pulled low. The bypass switch is forced open and SW_EN is reset to 0 and the host processor must set SW_EN=1 to close the switch again The ADC is not affected by this fault and operates according to the ADC_EN setting. Watchdog Timer To prevent unattended charging that may potentially damage the battery and/or system while the bypass switch is closed, the FAN54161 uses a watchdog timer as an additional layer of protection. The WDT control bits set the watchdog timer period and whether the watchdog timer protection will be enabled. If enabled, the watchdog timer starts when SW_EN is programmed to 1. To clear the watchdog timer, the host processor must execute an I read or write command to any of the FAN54161’s I 2C registers. When changing the setting of the watchdog timer in REG 0x06h[3:2], the new watchdog setting will not take effect until the next I2C read/write transaction. If the host processor fails to clear the watchdog timer and allows the watchdog timer to expire, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset all registers to their default values 3. Set the TIMER_INT bit to 1 and pull the INT_N pin low VOUT Over−Voltage Protection If the voltage applied to the VOUT pin exceeds the programmed V OUTOVP(TH) threshold for more than tVOUTOVPGLTCH, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the VOUTOVP_INT bit to 1 and pull the INT_N pin low If a VOUT OVP fault occurs, the host processor should reprogram the FAN54161’s charge parameter settings to prevent a VOUT OVP fault from reoccurring the next time the bypass switch is closed. Once the VOUT OVP fault is removed, the host processor must set SW_EN to 1 in order to close the bypass switch again. The switch will not close again until after VOUT has fallen below V OUTOVP(TH) − VOUTOVP(HYS). The VOUT over−voltage protection feature serves as an additional layer of protection in case the VOREG CV regulation loop is not fast enough to respond to a VOUT over−voltage fault, or if VOREG regulation is disabled. The ADC is not affected by this fault and operates according to the ADC_EN setting. IBUS Reverse Current Protection If the reverse current through the bypass switch (from VOUT to VBUS) rises above the programmed IRCB(TH) threshold, the bypass switch will be forced open to prevent excessive reverse current flow from the battery back to the input source. The IRCB control bit sets the I RCB(TH) reverse current threshold (0 = 100 mA, 1 = 3 A). The direction of I RCB(TH) is defined as current flow from VOUT to VBUS. The IC internally monitors the IBUS current through the bypass switch. When the current from VOUT to VBUS rises above IRCB(TH) for more than the tRCBGLTCH deglitch time, the FAN54161 will: 1. Isolate VBUS from VOUT by opening the bypass switch 2. Reset SW_EN to 0 3. Set the IBUSRCB_INT bit to 1 and pull the INT_N pin low 4. Rely on the host processor to send a SW_EN=1 command to close the switch again The ADC is not affected by this fault and operates according to the ADC_EN setting.

www.onsemi.com VFAIL Detection In bypass charging applications, a failure of the bypass charging switch (however, this is rare) could result in the travel adapter output being directly connected to the battery pack which can cause a potentially dangerous system fault. A V FAIL comparator monitors the voltage at PMID while the bypass switch is open to detect the presence of a leakage path from VBUS to PMID (when TA is attached) or VOUT to PMID (when battery is connected) which would indicate a failure in the bypass charging FET. During VFAIL detection, a R FAIL pulldown resistor is connected to PMID and a comparator checks if the PMID voltage exceeds the VFAIL threshold. R FAIL will be disconnected from PMID anytime the bypass switch is enabled to avoid power consumption during bypass charging. If the detection determines that VPMID > VFAIL for more than tVFAIL_GLTCH, the FAN54161 will: 1. Set the VFAIL_INT bit to 1 and pull the INT_N pin low A VFAIL interrupt alerts the host that damage to the bypass charging FET has occurred. The host can then alert the system bypass charging controller to clamp the travel adapter’s output voltage to the battery pack’s float voltage to prevent an overcharge of the battery. Additionally, the host can alert the end user that the portable device is damaged and should be returned for repair. If VFAIL_EN=1, VFAIL detection is momentarily activated when: 1. SW_EN is set from 0 to 1, while ADC_EN=0 and RESET_N=1. VFAIL detection occurs before the charge pump gate drive turns on the bypass charging FET but after the main bandgap reference is enabled 2. ADC_EN is set from 0 to 1, while SW_EN=0 and RESET_N=1 Regulation Loops Figure 11 illustrates the logic that causes the FAN54161 to enter regulation mode. Either of the following four fault protections being triggered can cause the switch to operate in regulation mode as follows: 1. If the voltage at VOUT exceeds VOREG(TH), and VOREG_EN=1, the bypass switch will be regulated such that V OUT is limited to VOREG(TH). 2. If the voltage across SNSP and SNSN exceeds VBATREG(TH), and VBATREG_EN=1, the bypass switch will be regulated such VBAT is limited to VBATREG(TH). 3. If IBAT (sensed as a voltage across SRP and SRN) exceeds IBATREG(TH), and IBATREG_EN=1, the bypass switch will be regulated such that IBAT is limited to IBATREG(TH). 4. If IBUS (from VBUS to VOUT) exceeds IBUSREG(TH), and IBUSREG_EN=1, the bypass switch will be regulated such that IBUS is limited to IBUSREG(TH). It must be noted that the switch essentially becomes more resistive during regulation mode. This will cause more power dissipation in the switch and a greater likelihood of the junction temperature reaching or exceeding the shutdown threshold T SDN(TH). Therefore it is imperative for the system host controller to update the system configuration such that none of the above four monitors are triggered. This can be done by increasing the thresholds in the FAN54161 or changing other external system parameters (ex: adapter voltage or current limit).

Figure 11. Switch Regulation Mode Entry Diagram affect bypass switch operation. architecture that drives the INT_N pin. be enabled or the switch closed.

1. Fully Differential Input high−accuracy SAR ADC
2. Up to 9 channels that can be independently
3. Single−shot or Continuous conversion
4. Post−processed Output Format
5. Fully configurable through digital I

VBUS and IBUS which would typically be zero. ADC in the FAN54161 can be configured to convert.

1. Every signal is processed through an analog

range in volts, amps or °C to the ADC input range.

1. IBAT has special considerations since it measures
2. T_BUS and T_BAT are meant for measuring
3. The accuracy referred to the input is based on error

Table 8. ADC CHANNEL SUMMARY

www.onsemi.com ADC Configuration There are two registers, ADC_CHANNEL and ADC_CONTROL, which are used to configure and control the ADC. All 9 channels have independent enable bits which reside in these registers. The ADC_CONTROL register and ADC_CHANNEL register values should not be reprogrammed when the ADC is performing a conversion. ADC Control The ADC can be configured to perform a one −shot conversion or perform continuous conversion by setting the ADC_RA TE bit to 1. An ADC conversion is initiated by setting the ADC_EN bit to 1. Once initiated, the ADC will convert the channels enabled for conversion according to the average mode selected (programmed by A VG_EN and SAMPLES). The enabled ADC channels are converted in order (LSB to MSB of ADC_CHANNEL register), followed by the ICTEMP bit in the ADC_CONTROL register.

• If the ADC_RATE bit is 0 (one−shot conversion), the ADC stores the results in the appropriate registers and sets the ADC_DONE interrupt bit. The ADC_EN bit is cleared to 0 after the conversion of all channels is complete.
• If the ADC_RATE bit is 1 (continuous conversion), the ADC stores the results in the appropriate registers and immediately begins a new conversion. In order to stop conversions, it is recommended to set the ADC_RATE bit to 0. This will ensure a complete conversion where the ADC_DONE interrupt bit is set and the ADC_EN bit is cleared to 0 similar to a normal one−shot conversion. ♦ Writing a 0 to the ADC_EN bit during continuous conversion is not recommended. This will immediately stop conversion without completing even the currently scheduled channel’s conversion. The ADC_DONE interrupt bit will not be set. ADC Output Format Each channel of the ADC has a dedicated pair of registers (an MSB register and an LSB register) where the input referred results are stored after a conversion is completed. Each pair is used to report the ADC’s converted result and polarity in binary format. Example 1: if the IBAT current is 5 A, the ADC’s output in 10−bit format is converted back to represent 5 A = 5000 mA = 0b0000100111000100. This value is stored in the registers IBAT_MSB and IBAT_LSB. If IBAT is −5 A instead, the final result stored in 0b1000100111000100. ADC Result Access The required sequence for reading the results of any ADC channel is to first read its MSB register followed by its LSB register. If the ADC is in one−shot conversion mode (ADC_RATE = 0), the host should issue I2C read commands to any of the results registers (REG 0x13 to 0x23) after the ADC_DONE interrupt is issued. If the ADC is in continuous conversion mode (ADC_RA TE = 1), the host can issue I2C read commands to any of the results registers (REG 0x13 to 0x23) even while the ADC is performing conversions and storing results in these registers. ADC Based Over−temperature Protection The two pins TS_BUS and TS_BAT are used to measure temperature of the VBUS connector and the battery respectively, by measuring voltage of an external NTC thermistor. This thermistor has an external pull−up to a 2.4 V supply. The ADC also converts the signal on these two pins to 10 −bit results and stores them in the registers TBUS_MSB, TBUS_LSB, TBAT_MSB and TBAT_LSB respectively. These results are used in the following manner described to provide hardware protection for over−temperature of the VBUS connector or battery. The logic to explain this is illustrated in Figure 12.
• There are two registers to configure a digital over−temperature threshold called TBUSOTP and TBATOTP respectively.
• When the voltage measured by the ADC on TS_BUS or TS_BAT drops below the value in the registers TBUSOTP or TBATOTP respectively, the over−temperature hardware protection is triggered.
• If TBUSOTP_EN or TBATOTP_EN bits in the PROTECT_EN register are set to 1, and in addition, the corresponding TBUSADC_EN or TBATADC_EN bits are enabled, then the TBUSOTP or TBATOTP fault being triggered will result in the switch of the FAN54161 to be opened.
• This also causes the interrupt bit TBUSOTP_INT or TBATOTP_INT to be set accordingly, and if unmasked, will assert the INT_N pin low. Example 1: TBUSOTP_EN = 1 and TBUSADC_EN = 1 If the output of the ADC for the TBUS channel (TBUS_MSB, TBUS_LSB) drops below the value programmed in TBUSOTP, the switch will open and TBUSOTP_INT will be set. Example 2: TBATOTP_EN = 1 and TBATADC_EN = 0 If the output of the ADC for the TBAT channel (TBAT_MSB, TBAT_LSB) drops below the value programmed in TBA TOTP, the switch will not open and the TBATOTP_INT will not be set. Although the value in the ADC result registers exceeds that in the threshold register, since the ADC is not enabled to convert that channel, the result cannot be trusted and hence is not allowed to control the switch.

charging current when the FAN54161 switch is closed.

• Increase copper weight to greater than 1 oz, if possible.
• Use large as possible copper area for both VBUS and VOUT planes and ensure that copper floods the landing pads of all the VBUS and VOUT balls.
• Place via−in−pad on all VBUS and VOUT landing pads and mirror the top layer copper to the bottom layer for an additional thermal relief path. ♦ Follow the recommended placement for CBUS and COUT shown in Figure 19.
• Place a floating copper plane on PMID (A5 through G5) to provide an additional thermal relief path. ♦ Place via−in−pad on all PMID landing pads and mirror the top layer copper to the bottom layer for an additional thermal relief path.

Figure 19. VBUS and VOUT Copper Top Layer Routing

www.onsemi.com I2C Registers and Bit Descriptions Register Map Name Adr 7 6 5 4 3 2 1 0 IC INFO 00h Reserved Reserved INT1 MASK 01h VBUSOVP_M IBUSREG_M VBATREG_M IBATREG_M VOREG_M TBUSOTP_M TBATOTP_M IBUSRCB_M INT2 MASK 02h Reserved ADCDONE_M VDROPALM_M VDROPOVP_M VBUSINSERT_M VBATINSERT_M TSDN_M IBUSOCP_M INT1 03h VBUSOVP_INT IBUSREG_INT VBATREG_INT IBATREG_INT VOREG_INT TBUSOTP_INT TBATOTP_INT IBUSRCB_INT INT2 04h Reserved ADCDONE_INT VDROPALM_INT VDROPOVP_INT VBUSINSERT_INT VBATINSERT_INT TSDN_INT IBUSOCP_INT PROTECT_EN 05h VBUSOVP_EN IBUSREG_EN VBATREG_EN IBATREG_EN VOREG_EN TBUSOTP_EN TBATOTP_EN VBUSPD_EN SW_CONTROL 06h VDROPOVP_EN VDROPALM_EN RSENSE SW_EN IRCB REG_RST ADC_CONTROL 07h ICTEMPADC_EN Reserved Reserved Reserved ADC_EN ADC_RATE AVG_EN SAMPLES ADC_CHANNEL 08h VBUSADC_EN IBUSADC_EN VOUTADC_EN VDROPADC_EN VBATADC_EN IBATADC_EN TBUSADC_EN TBATADC_EN PROT_DELAY 09h Reserved Reserved IBUSOCP_MODE OVP_DLY VBUSOVP 0Ah Reserved VOREG 0Bh Reserved VDROPOVP 0Ch VDROP_ALM 0Dh VBATREG 0Eh Reserved IBATREG 0Fh Reserved IBUSREG 10h TBUSOTP 11h Reserved TBATOTP 12h Reserved VBUS_MSB 13h Reserved Reserved Reserved VBUS_LSB 14h IBUS_MSB 15h Reserved Reserved Reserved IBUS_LSB 17h VOUT_MSB 17h Reserved Reserved Reserved VOUT_LSB 18h VDROP_MSB 19h Reserved Reserved Reserved Reserved Reserved Reserved VDROP_LSB 1Ah VBAT_MSB 1Bh Reserved Reserved Reserved VBAT_LSB 1Ch IBAT_MSB 1Dh IBATADC_POL Reserved Reserved IBAT_LSB 1Eh TBUS_MSB 1Fh Reserved Reserved Reserved Reserved TBUS_LSB 20h TBAT_MSB 21h Reserved Reserved Reserved Reserved TBAT_LSB 22h ICTEMP_ADC 23h CONTROL1 50h Reserved VOUTOVP_DLY VOUTOVP_EN VFAIL_EN IBUSRCB_EN IBUSOCP_EN CONTROL2 51h Reserved INT3 MASK 52h Reserved Reserved Reserved Reserved VOUTOVP_M VFAIL_M VUSBOVP_M VUSBINSERT_M INT3 53h Reserved Reserved Reserved TIMER_INT VOUTOVP_INT VFAIL_INT VUSBOVP_INT VUSBINSERT_INT STATUS1 54h VOREG_ST VBATREG_ST IBATREG_ST IBUSREG_ST VBUSINSERT_ST VBATINSERT_ST Reserved VUSBINSERT_ST IBATREG Register Bit Name REV PN WDT IBUSOCP_TH VBUSOVP_TH VOREG VDROPOVP_TH VDROP_ALM VBATREG VBATADC_MSB IBUSREG TBUS_TH TBAT_TH VBUSADC_MSB VBUSADC_LSB IBUSADC_MSB IBUSADC_LSB VOUTADC_MSB VOUTADC_LSB VDROPADC_MSB VDROPADC_LSB TBATADC_LSB ICTEMPADC TJSHDN VOUTOVP_TH VBATADC_LSB IBATADC_MSB IBATADC_LSB TBUSADC_MSB TBUSADC_LSB TBATADC_MSB

www.onsemi.com Bit Descriptions Default values are in bold text. Default values are with VBAT = 3.8 V and VBUS = open. IC INFO Register Address = 00h Default = 0000 1010 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5:3 REV 001 Read This indicates the revision number of the IC. 2:0 PN 010 Read This indicates the part number of the IC. INT1 MASK Register Address = 01h Default = 0000 0000 Bit Name Default Type Description 7 VBUSOVP_M 0 R/W This is the interrupt mask for a VBUS over voltage fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6 IBUSREG_M 0 R/W This is the interrupt mask for an IBUS over current regulation event where the switch

operates in regulation mode to limit the input current to the IBUSREG setting. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VBATREG_M 0 R/W This is the interrupt mask for the VBAT CV regulation loop. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 IBATREG_M 0 R/W This is the interrupt mask for the IBAT CC regulation loop. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VOREG_M 0 R/W This is the interrupt mask for the VOUT CV regulation loop. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 TBUSOTP_M 0 R/W This is the interrupt mask for a T_BUS over temperature fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TBATOTP_M 0 R/W This is the interrupt mask for a T_BAT over temperature fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 IBUSRCB_M 0 R/W This is the interrupt mask for an IBUS reverse current fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry INT2 MASK Register Address = 02h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 ADCDONE_M 0 R/W This is the interrupt mask for a completed ADC conversion. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VDROPALM_M 0 R/W This is the interrupt mask for when VDROP rises above its alarm threshold. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 VDROPOVP_M 0 R/W This is the interrupt mask for when VDROP rises above its OVP threshold. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

3 VBUSINSERT_M 0 R/W This is the interrupt mask for when VBUS rises above VBUSUVLO(TH) or falls below

VBUSUVLO(TH) − VBUSUVLO(HYS). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 VBATINSERT_M 0 R/W This is the interrupt mask for when VSNSP rises above VBATINSERT(TH) or falls below VBATINSERT(TH) − VBATINSERT(HYS). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TSDN_M 0 R/W This is the interrupt mask for an IC thermal shutdown fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

0 IBUSOCP_M 0 R/W This is the interrupt mask for an IBUS over current event where the IBUSOCP thresh-

old is exceeded. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com INT1 Register Address = 03h Default = 0000 0000 Bit Name Default Type Description 7 VBUSOVP_INT 0 R/CLR This interrupt bit is set when the VBUS voltage exceeds VBUSOVP(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 6 IBUSREG_INT 0 R/CLR This interrupt bit is set when IBUS CC loop operates the switch in regulation mode to limit IBUS to IBUSREG(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VBATREG_INT 0 R/CLR This interrupt bit is set when the VBAT CV loop is operating the switch in regulation mode to limit (VSNSP−VSNSN) to VBATREG(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 IBATREG_INT 0 R/CLR This interrupt bit is set when the IBAT CC loop is operating the switch in regulation mode to limit IBAT to IBATREG(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VOREG_INT 0 R/CLR This interrupt bit is set when the VOUT CV loop is operating the switch in regulation mode to limit VOUT to VOREG(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 TBUSOTP_INT 0 R/CLR This interrupt bit is set when the temperature of the T_BUS NTC thermistor has ex- ceeded the T_BUS over temperature threshold. The ADC must have the TBUSOTP channel active to trigger this interrupt. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TBATOTP_INT 0 R/CLR This interrupt bit is set when the temperature of the T_BAT NTC thermistor has ex- ceeded the T_BAT over temperature threshold. The ADC must have the TBATOTP channel active to trigger this interrupt. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 IBUSRCB_INT 0 R/CLR This interrupt bit is set when the current from VOUT to VBUS exceeds IRCB(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry INT2 Register Address = 04h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0.

6 ADCDONE_INT 0 R/CLR This interrupt bit is set when ADC conversion is complete in one−shot mode only

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VDROPALM_INT 0 R/CLR This interrupt bit is set when the VDROP voltages exceeds VDROPALM(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 VDROPOVP_INT 0 R/CLR This interrupt bit is set when the VDROP voltages exceeds VDROPOVP(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

3 VBUSINSERT_INT 0 R/CLR This interrupt bit is set when the ADC is enabled and VBUS voltage rises above

VBUSUVLO(TH) or falls below VBUSUVLO(TH) − VBUSUVLO(HYS). This interrupt is edge triggered. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 VBATINSERT_INT 0 R/CLR This interrupt bit is set when the ADC is enabled and VSNSP rises above VBATIN- SERT(TH) or falls below VBATINSERT(TH) − VBATINSERT(HYS). This interrupt is edge trig- gered. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TSDN_INT 0 R/CLR This interrupt bit is set when the die temperature exceeds TSDN(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 IBUSOCP_INT 0 R/CLR This interrupt bit is set when the IBUS current exceeds IBUSOCP(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com PROTECT_EN Register Address = 05h Default = 1111 1110 Bit Name Default Type Description 7 VBUSOVP_EN 1 R/W A 1 enables VBUS OVP protection. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 6 IBUSREG_EN 1 R/W A 1 enables IBUS constant current regulation capability. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VBATREG_EN 1 R/W A 1 enables VBAT constant voltage regulation capability. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 IBATREG_EN 1 R/W A 1 enables IBAT constant current regulation capability. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VOREG_EN 1 R/W A 1 enables VOUT constant voltage regulation capability. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 TBUSOTP_EN 1 R/W A 1 enables T_BUS over temperature protection. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TBATOTP_EN 1 R/W A 1 enables T_BAT over temperature protection. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 VBUSPD_EN 0 R/W A 1 enables an internal 100 Ohm pulldown resistor on VBUS. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com SW_CONTROL Register Address = 06h Default = 0010 1000 Bit Name Default Type Description 7 VDROPOVP_EN 0 R/W A 1 enables the VDROP protection circuit. If this protection is enabled, the switch will open whenever VBUS−VOUT > VDROPOVP(TH) for more than tVDROPGLTCH. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 6 VDROPALM_EN 0 R/W A 1 enables the VDROP alarm circuit. If this alarm is enabled, the IC will flag the host that VBUS−VOUT has exceeded the VDROPALM(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5 RSENSE 1 R/W Program this bit according to the value of the external sense resistor across RSP and

RSN. Code RSENSE Value 0 5 m/C0087 1 10 m/C0087 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 SW_EN 0 R/W A 1 enables the switch and hardware protection. This bit will automatically reset to 0 when the switch is opened due to a fault condition other than VBUS UVLO. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3:2 WDT 10 R/W This enables and sets the duration of the watch dog timer. When enabled, the watchdog timer is reset by an I2C read or write command to any register of the FAN54161. A watchdog timer expiry opens the switch and generates an interrupt. Code WDT Setting

00 Disabled

01 0.5 sec 10 1.0 sec 11 2.0 sec Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 IRCB 0 R/W This bit sets the reverse current blocking protection threshold. The direction of re- verse current flow through the switch is from VOUT to VBUS. Code IRCB Threshold (mA) 0 100 1 3000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 REG_RST 0 W1CLR Setting this bit will reset all I2C control and interrupt register bits (except status) to their default value. This bit is self−clear. Code Action

0 No Effect

1 Reset I2C control and interrupt bits to default values

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com ADC_CONTROL Register Address = 07h Default = 1000 0111 Bit Name Default Type Description 7 ICTEMPADC_EN 1 R/W A 1 enables the ADC measurement of the IC temperature. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 Reserved 0 Read Reserved. Always reads 0. 3 ADC_EN 0 R/W A 1 enables the ADC. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 ADC_RATE 1 R/W This bit controls the conversion mode of the ADC. Code ADC Mode

0 Single Conversion

1 Continuous Conversion

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 AVG_EN 1 R/W A 1 enables ADC measurement averaging. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

0 SAMPLES 1 R/W This bit sets the number of samples used for an ADC conversion if averaging is en-

abled. Code # of ADC Averaging Samples 0 8 1 16 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry ADC_CHANNEL Register Address = 08h Default = 1111 1111 Bit Name Default Type Description 7 VBUSADC_EN 1 R/W A 1 enables ADC measurement of VBUS. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 6 IBUSADC_EN 1 R/W A 1 enables ADC measurement of IBUS. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 VOUTADC_EN 1 R/W A 1 enables ADC measurement of VOUT. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 VDROPADC_EN 1 R/W A 1 enables ADC measurement of VDROP. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VBATADC_EN 1 R/W A 1 enables ADC measurement of VBAT via VSNSP and VSNSN. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2 IBATADC_EN 1 R/W A 1 enables ADC measurement of IBAT through the sense resistor across SRP and

SRN. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 TBUSADC_EN 1 R/W A 1 enables ADC measurement of T_BUS. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 TBATADC_EN 1 R/W A 1 enables ADC measurement of T_BAT. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com PROT_DELAY Register Address = 09h Default = 1010 0000 Bit Name Default Type Description 7:4 IBUSOCP_TH 1010 R/W This sets the IBUS over current protection threshold. When IBUS rises above the IBUS over protection threshold, the switch will open and an interrupt will be generated. Code IBUS OCP Threshold (A) 0000 0.5 0001 0.5 0010 1.0 0011 1.5 0100 2.0 0101 2.5 0110 3.0 0111 3.5 1000 4.0 1001 4.5 1010 5.0 1011 5.5 1100 6.0 1101 6.5 1110 7.0 1111 7.5 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 Reserved 0 Read Reserved. Always reads 0. 2 Reserved 0 Read Reserved. Always reads 0. 1 IBUSOCP_MODE 0 R/W This bit controls the IBUS over current protection mode of operation. Code IBUS OCP Response After Over Current Fault IBUS OCP Deglitch Time

0 Open switch and reset SW_EN = 0 50 /C0109s

1 Hiccup Mode (open switch and then at-

tempt to close switch every 100 ms up to 7 times before latching switch open if over current fault still exists) 8 /C0109s Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 OVP_DLY 0 R/W This bit sets the deglitch time of the VBUS and VDROP over voltage protection circuits. Code VBUS OVP Deglitch Time (/C0109s) VDROP OVP Deglitch Time (/C0109s) VDROP Alarm Deglitch Time (/C0109s) 0 4 4 4 1 20 20 20 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com VBUSOVP Register Address = 0Ah Default = 0011 0100 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 VBUSOVP_TH 0110100 R/W This sets the VBUS over voltage protection threshold. When VBUS rises above the VBUS over protection threshold, the switch will open and an interrupt will be generated. Code VBUSOVP Threshold (V) 0000000 4.200 0000001 4.225 0000010 4.250 − − 0110100 5.500 − − 1011100 to 1111111 6.500 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VOREG Register Address = 0Bh Default = 0001 0100 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 VOREG 0010100 R/W This sets the VOREG regulation threshold of the VOUT CV loop. When VOUT rises to the VOREG threshold, the switch will operate in regulation mode and limit VOUT to the VOREG threshold. Code VOREG (V) 0000000 4.20 0000001 4.21 0000010 4.22 − − 0010100 4.40 − − 1001111 4.99 1010000 to 1111111 5.00 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VDROPOVP Register Address = 0Ch Default = 0011 1100 Bit Name Default Type Description 7:0 VDROPOVP_TH 00111100 R/W This sets the VDROP over voltage protection threshold. When VDROP voltage rises above the VDROP over voltage protection threshold, the switch will open and an inter- rupt will be generated. Code VDROP OVP Threshold (V) 0000 0000 0 0000 0001 5 0000 0010 10 0000 0011 15 − − 0011 1100 300 − − 11000111 995 1100 1000 to 1111 1111 1000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com VDROP_ALM Register Address = 0Dh Default = 0001 0100 Bit Name Default Type Description 7:0 VDROP_ALM 00010100 R/W This sets the VDROP alarm threshold. When VDROP voltage rises above the VDROP alarm threshold, an interrupt will be generated. Code VDROP Alarm Threshold (V) 0000 0000 0 0000 0001 5 0000 0010 10 − − 0001 0100 100 − − 1100 0111 995 1100 0000 to 1111 1111 1000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VBATREG Register Address = 0Eh Default = 0000 1011 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 VBATREG 0001010 R/W This sets the VBATREG regulation threshold of the VBAT CV loop. When VSNSP− VSNSN rises to the VBATREG threshold, the switch will operate in regulation mode and limit VSNSP−VSNSN to the VBATREG threshold. Code VBATREG Threshold (V) 0000000 4.20 0000001 4.21 0000010 4.22 − − 0001010 4.3 − − 1001111 4.99 1010000 to 1111111 5.00 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry IBATREG Register Address = 0Fh Default = 0010 1000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 IBATREG 0101000 R/W This sets the IBATREG regulation threshold of the IBAT CC loop. When the measured IBAT current rises above the IBATREG threshold, the switch will operate in regula- tion mode to limit the IBAT current to IBATREG. The IBAT current is sensed using the SRP and SRN pins with an external R SENSE resistor. Code IBATREG Threshold (V) 0000000 0.10 0000001 0.10 0000010 0.10 0000011 0.15 − − 0101000 2.00 − − 1111101 6.25 1111110 6.30 1111111 6.35 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com IBUSREG Register Address = 10h Default = 0100 0110 Bit Name Default Type Description 7:0 IBUSREG 01000110 R/W This sets the IBUSREG regulation threshold of the IBUS CC loop. When the measured IBUS current rises above the IBUSREG threshold, the switch will operate in regula- tion mode to limit the IBUS current to IBUSREG. The IBUS current is sensed internally through the switch. Code IBUSREG Threshold (A) 0000 0000 0.10 0000 0001 0.10 0000 0010 0.10 0000 0011 0.15 − − 0100 0110 3.50 − − 1000 0000 6.40 1000 0001 6.45 1000 0010 to 1111 1111 6.50 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry TBUSOTP Register Address = 11h Default = 0001 1110 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 TBUS_TH 0011110 R/W This sets the T_BUS over temperature threshold. When the ADC measurement of the T_BUS voltage falls below the T_BUS over temperature voltage threshold, the switch will open and a VBUS connector over−temperature interrupt will be generated. An ex- ternal NTC thermistor is used to measure the temperature of the VBUS connector. Code T_BUS Over Temperature Threshold (V) 0000 0000 0.0 0000 0001 0.02 0000 0010 0.04 − − 0011110 0.60 − − 1110111 2.38 1111000 to 1111 1111 2.40 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry TBATOTP Register Address = 12h Default = 0010 0011 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 TBAT_TH 0100011 R/W This sets the T_BAT over temperature threshold. When the ADC measurement of the T_BAT voltage falls below the T_BAT over temperature voltage threshold, the switch will open and a battery over−temperature interrupt will be generated. An external NTC thermistor can be used to measure the temperature of the battery. Code T_BAT Over Temperature Threshold (V) 0000 0000 0.0 0000 0001 0.02 0000 0010 0.04 − − 0100011 0.70 − − 1110111 2.38 1111000 to 1111 1111 2.40 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com VBUS_MSB Register Address = 13h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4:0 VBUSADC_MSB 00000 Read VBUSADC_MSB along with VBUSADC_LSB form the 13 bit result of the VBUS volt- age. When VBUS < 300mV, VBUSADC will report 0V. VBUSADC (b) VBUSADC (h) VBUS (mV) 0000000000000 0000 0 to 299 0000100101100 012C 300 0000100101101 012D 301 − − − 1011111010011 17D3 6099 1011111010100 17D4 6100 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VBUS_LSB Register Address = 14h Default = 0000 0000 Bit Name Default Type Description 7:0 VBUSADC_LSB 00000000 Read VBUSADC_LSB along with VBUSADC_MSB (REG 13h[4:0]) form the 13 bit result of the VBUS voltage. When V BUS < 300mV, VBUSADC will report 0V. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry IBUS_MSB Register Address = 15h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4:0 IBUSADC_MSB 00000 Read IBUSADC_MSB along with IBUSADC_LSB form the 13 bit result of the IBUS current. IBUSADC (b) IBUSADC (h) IBUS (mA) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 1101101010111 1B57 6999 1101101011000 1B58 7000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry IBUS_LSB Register Address = 16h Default = 0000 0000 Bit Name Default Type Description 7:0 IBUSADC_LSB 00000000 Read IBUSADC_MSB along with IBUSADC_LSB (REG15h[4:0]) form the 13 bit result of the IBUS current. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com VOUT_MSB Register Address = 17h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4:0 VOUTADC_MSB 00000 Read VOUTADC_MSB along with VOUTADC_LSB form the 13 bit result of the VOUT volt- age. VOUTADC (b) VOUTADC (h) VOUT (mV) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 1001110000111 1387 4999 1001110001000 1388 5000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VOUT_LSB Register Address = 18h Default = 0000 0000 Bit Name Default Type Description 7:0 VOUTADC_LSB 00000000 Read VOUTADC_LSB along with VOUTADC_MSB (REG17h[4:0]) form the 13 bit result of the VOUT voltage. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VDROP_MSB Register Address = 19h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 Reserved 0 Read Reserved. Always reads 0. 3 Reserved 0 Read Reserved. Always reads 0. 2 Reserved 0 Read Reserved. Always reads 0. 1:0 VDROPADC_MSB 00 Read VDROPADC_LSB along with VDROPADC_MSB form the 10 bit result of the VDROP voltage = VBUS − VOUT. VDROPADC (b) VDROPADC (h) VDROP (mV) 0000000000 0000 0 0000000001 0001 1 0000000010 0002 2 − − − 1111100111 3E7 999 1111101000 3E8 1000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VDROP_LSB Register Address = 1Ah Default = 0000 0000 Bit Name Default Type Description 7:0 VDROPADC_LSB 00000000 Read VDROPADC_LSB along with VDROPADC_MSB (REG19h[1:0]) form the 10 bit result of the VDROP voltage = VBUS − VOUT. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com VBAT_MSB Register Address = 1Bh Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4:0 VBATADC_MSB 00000 Read VBATADC_LSB along with VBATADC_MSB form the 13 bit result of the VBAT = VSNSP − VSNSN. VBATADC (b) VBATADC (h) VBAT (mV) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 1001110000111 1387 4999 1001110001000 1388 5000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry VBAT_LSB Register Address = 1Ch Default = 0000 0000 Bit Name Default Type Description 7:0 VBATADC_LSB 00000000 Read VBATADC_LSB along with VBATADC_MSB (REG1B[4:0]) form the 13 bit result of the VBAT = VSNSP − VSNSN. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry IBAT_MSB Register Address = 1Dh Default = 0000 0000 Bit Name Default Type Description 7 IBATADC_POL 0 Read Polarity of IBAT_ADC result. 0 − positive (+) 1 − negative (−) 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4:0 IBATADC_MSB 00000 Read IBATADC_MSB along with IBATADC_LSB form the 13 bit ADC measurement of the IBAT current measured through RSENSE across SRP and SRN pins. IBUSADC (b) IBUSADC (h) IBUS (mA) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 1101101010111 1387 6999 1101101011000 1388 7000 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry IBAT_LSB Register Address = 1Eh Default = 0000 0000 Bit Name Default Type Description 7:0 IBATADC_LSB 00000000 Read IBATADC_LSB along with IBATADC_MSB (REG1Dh[4:0]) form the 13 bit ADC mea- surement of the IBAT current measured through R SENSE across SRP and SRN pins. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com TBUS_MSB Register Address = 1Fh Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 Reserved 0 Read Reserved. Always reads 0. 3:0 TBUSADC_MSB 0000 Read TBUSADC_MSB along with TBUSADC_LSB form the raw bit ADC measurement of the TS_BUS voltage formed by the external NTC thermistor network used to sense the temperature of the input connector. A 2.4V external reference is recommended. TBUSADC (b) TBUSADC (h) TBUS (mV) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 100101011111 95F 2399 100101100000 960 2400 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry TBUS_LSB Register Address = 20h Default = 0000 0000 Bit Name Default Type Description 7:0 TBUSADC_LSB 00000000 Read TBUSADC_LSB along with TBUSADC_MSB (REG1Fh[3:0]) form the 12 bit result of the TS_BUS voltage formed by the external NTC thermistor network used to sense the temperature of the input connector. A 2.4V external reference is recommended. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry TBAT_MSB Register Address = 21h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 Reserved 0 Read Reserved. Always reads 0. 3:0 TBATADC_MSB 0000 Read TBATADC_MSB along with TBATADC_LSB form the 12 bit result of the TS_BAT volt- age formed by the external NTC thermistor network used to sense the temperature of the battery. A 2.4V external reference is recommended. TBATADC (b) TBATADC (h) TBAT (mV) 0000000000000 0000 0 0000000000001 0001 1 0000000000010 0002 2 − − − 100101011111 95F 2399 100101100000 960 2400 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry TBAT_LSB Register Address = 22h Default = 0000 0000 Bit Name Default Type Description 7:0 TBATADC_LSB 00000000 Read TBATADC_LSB along with TBATADC_MSB (reg21h[3:0]) form the 12 bit result of the TS_BAT voltage formed by the external NTC thermistor network used to sense the temperature of the battery. A 2.4V external reference is recommended. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com ICTEMP_LSB Register Address = 23h Default = 0000 0000 Bit Name Default Type Description 7:0 ICTEMPADC 00000000 Read ICTEMPADC forms the 8 bit result of the IC’s internal die temperature sensor. ICTEMPADC (b) ICTEMPADC (h) ICTEMP (/C0053C) 00000000 0 0 − − − 00011001 19 25 00011010 1A 26 00011011 1B 27 − − − 10010101 95 149 10010110 96 150 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry CONTROL1 Register Address = 50h Default = 0100 0011 Bit Name Default Type Description 7:6 TJSHDN 01 R/W TJSHDN programs the thermal shutdown threshold. Code Junction Temperature Threshold (/C0053C) 00 115 01 125 10 135 11 145 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

5 Reserved 0 Read Reserved

4 VOUTOVP_DLY 0 R/W This bit sets the deglitch time of the VOUT over voltage protection circuit. Code VOUT OVP Deglitch Time (/C0109S) 00 4 01 20 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VOUTOVP_EN 0 R/W A 1 enables the VOUT OVP protection circuit. If enabled and VOUT > VOUTOVP, the switch is forced open. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2 VFAIL_EN 0 R/W A 1 enables a detection mechanism that senses if the bypass switch is permanently

shorted. RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 IBUSRCB_EN 1 R/W A 1 (default setting) enables IBUS reverse current blocking protection. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 IBUSOCP_EN 1 R/W A 1 (default setting) enables the IBUS over current protection circuit that is set by a programmable IBUSOCP threshold. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com CONTROL2 Register Address = 51h Default = 0001 0100 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6:0 VOUTOVP_TH 0010100 R/W This sets the VOUT OVP threshold. When VOUT rises above its OVP threshold, the switch will open. Code VOUT OVP Threshold (V) 0000000 4.50 0000001 4.51 0000010 4.52 − − 0010100 4.70 − − 1001111 5.29 1010000 to 1111111 5.30 Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry INT3 MASK Register Address = 52h Default = 0000 0001 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 Reserved 0 Read Reserved. Always reads 0. 3 VOUTOVP_M 0 R/W A 1 sets the interrupt mask for a VOUT OVP fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 VFAIL_M 0 R/W A 1 sets the interrupt mask for a VFAIL fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 VUSBOVP_M 0 R/W A 1 sets the interrupt mask for a VUSBOVP fault. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 0 VUSBINSERT_M 1 R/W A 1 (default setting) sets the interrupt mask for a VUSB insertion or removal event. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

www.onsemi.com INT3 Register Address = 53h Default = 0000 0000 Bit Name Default Type Description 7 Reserved 0 Read Reserved. Always reads 0. 6 Reserved 0 Read Reserved. Always reads 0. 5 Reserved 0 Read Reserved. Always reads 0. 4 TIMER_INT 0 R/CLR This interrupt is set when the watchdog timer has expired. Reset condition: RESET_N falling; REG_RST=1 3 VOUTOVP_INT 0 R/CLR This interrupt is set when VOUT exceeds VOUTOVP(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

2 VFAIL_INT 0 R/CLR This interrupt is set when the common source voltage of the bypass switch is above

the VFAILthreshold when the switch is open (SW_EN=0). A “1” would indicate that the bypass switch has failed and the host processor should flag the user to service the device. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 VUSBOVP_INT 0 R/CLR This interrupt is set when VUSB exceeds the VUSBOVP threshold. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

0 VUSBINSERT_INT 0 R/CLR This interrupt is set when VUSB rises above VUSBUVLO(TH) or falls below VUSBU-

VLO(TH) − VUSBUVLO(HYS). When an external OVP blocking FET is not used, the floating VUSB pin can still exceed the VUSBUVLO(TH) threshold during a VBUS OVP event causing a false VUSBINSERT interrupt. It is recommended to mask this bit when no external FET is used to prevent the INT pin from pulling low due to a VBUS OVP event. Masking this bit does not prevent it from being set, so this bit should be ignored when an external OVP blocking FET is not used. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry STATUS1 Register Address = 54h Default = 0000 0100 Bit Name Default Type Description 7 VOREG_ST 0 Read A 1 indicates that the VOREG CV regulation loop is active. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

6 VBATREG_ST 0 Read A 1 indicates that the VBATREG CV regulation loop is active

Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 5 IBATREG_ST 0 Read A 1 indicates that the IBATREG CC regulation loop is active. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 4 IBUSREG_ST 0 Read A 1 indicates that the IBUSREG CC regulation loop is active. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 3 VBUSINSERT_ST 0 Read A 1 indicates that VBUS is above VBUSUVLO(TH). When the switch is open (SW_EN=0) and the ADC is disabled (ADC_EN=0), this bit is latched to 0 regardless if there is a valid source on VBUS. Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 2 VBATINSERT_ST 1 Read A 1 indicates that VSNSP is above VBATINSERT(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry 1 Reserved 0 Read Reserved. Always reads 0. 0 VUSBINSERT_ST 0 Read A 1 indicates that VUSB is above VUSBUVLO(TH). Reset condition: RESET_N falling; REG_RST=1; Watchdog Timer Expiry

WLCSP42 2.78x3.06x0.65 CASE 567TY ISSUE O DATE 31 MAR 2017 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON13337GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1WLCSP42 2.78x3.06x0.65 © Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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