MCR20A

MCR20AVHM NXP | Alldatasheet

Document overview

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Technical content

Low power, high-performance 2.4 GHz IEEE 802.15.4 compliant transceiver with connectivity The MCR20AVHM transceiver (or MCR20A) is a low power, high-performance 2.4 GHz, IEEE 802.15.4 compliant transceiver with connectivity to a broad range of microcontrollers, including the Kinetis family of products. The MCR20AVHM transceiver enables development of proprietary and standard 802.15.4 based communication protocols such as SMAC, IEEE802.15.4 PHY-MAC, Thread, ZigBeePRO, RF4CE, and others. Typical applications include Home Area Networks consisting of meters, gateways, in-home displays, and connected appliances, and also networked building control, home automation applications with lighting control, HVAC, and security and remote controls for home entertainment products. Transceiver Performance

• 2.4 GHz (2360 to 2480 MHz) covers ISM band
• Fractional-N PLL supports 1 MHz and 5 MHz channels
• 250 kbps data rate
• OQPSK modulation
• Programmable output power
• -102 dBm RX sensitivity Standards
• 802.15.4 Compliant Transceiver
• Thread, IPv6-6LoWPAN Transceiver Features
• Hardware acceleration for IEEE 802.15.4 2006 packet processing
• Support for Dual PAN mode
• Onboard trim of reference crystal
• 128-byte RAM data buffer
• Low-power operating modes with single SPI command device wake-up
• On-chip voltage regulators
• Clear Channel Assessment, Energy Detect, Link Quality Indicator Radio peripherals
• 24-bit event timer with interrupts
• Eight (8) software programmable GPIOs
• Control port for antenna diversity mode or external PA and LNA Microcontroller Interface
• Programmable frequency clock output (CLK_OUT)
• SPI command channel and interface
• Interrupt request output Operating Characteristics
• 1.8 V to 3.6 V operating voltage
• 17mA TX, 19mA RX, < 1mA idle/doze, < 1uA hybernate typical current
• operational temperature range : –40°C to +105°C Physical Characteristics
• RoHS compliant, 5 mm x 5 mm, 32-pin MLGA package
• Small RF footprint, low component count MCR20AVHM

32 LGA

NXP Semiconductors MCR20AVHM Data Sheet: Technical Data Rev. 3.2, 07/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Ordering Information

Device Operating Temp Range (TA) Package Description MCR20AVHM -40 deg C to +105 deg C MLGA-32 IEEE 802.15.4 - 2.4 GHz ISM Band 2 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

1.3.5 Clear channel assessment (CCA), energy

detection (ED), and link quality indicator MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 3 NXP Semiconductors

1 Transceiver Description

1.1 Transceiver Architecture

GPIOs, and digital manager block and MCU interface. Figure 1. MCR20A Transceiver Simplified Block Diagram

Each of the blocks is described in more detail in the following sections.

1.2 RF interface and usage

an internal hardware state machine.

1.2.1 Radio to MCU interface

describing the functionality and connections between the radio and MCU. Figure 2. MCU to MCR20A block diagram

1.2.1.1 SPI interface

1.2.1.2 IRQ management

• The IRQ_B pin can be configured as actively-driven high or open-drain.
• Each interrupt source has its own interrupt status bit in the MCR20A transceiver's direct register space.
• Each interrupt can be individually controlled by an interrupt mask—The IRQ is issued when the mask is cleared to 0.
• There is also a global interrupt mask, TRCV_MSK, which can enable or disable all IRQ_B assertions by programming a single masking bit.
• All status bits use a write-1-to-clear protocol—interrupt status bits are not affected by reads.
• IRQ_B will remain asserted until all active interrupt sources are cleared or masked.

Table 1. IRQ sources

Any or all of the interrupt sources, can be enabled to cause an assertion on IRQ_B.

1.2.1.3 Memory map and registers

Numerous register bits are provided to control interrupt behavior within the MCR20A transceiver. Detailed information for memory map and registers is located in the MCR20A Reference Manual.

1.2.2 Clock output feature

The CLK_OUT digital output can be enabled to drive the system clock to the MCU. This provides a highly accurate clock source based on the transceiver reference oscillator. The clock is programmable over a wide range of frequencies divided down from the reference 32 MHz (see Table 4). The frequency of CLK_OUT will be determined by the state of the GPIO5/BOPT (boot option) pin. If this pin is low upon POR, then the frequency will be 4 MHz (32 MHz/8). If this pin is high upon POR (GPIO5 has a pullup resistor) then the frequency will be 32.78689 kHz (32 MHz/976). Transceiver Functions

1.3.1 Receive

The receiver has the functionality to operate in either normal run state or low power run state that can be considered as a partial power down mode. Low power run state can save a considerable amount of current by duty-cycling some sections of the receiver lineup during preamble search and is referred to as low power preamble search mode (LPPS). The radio receiver path is based upon a near zero IF (NZIF) architecture incorporating front end amplification, one mixed-signal down conversion to IF that is programmably filtered, demodulated, and digitally processed. The RF front end (FE) input port is differential and shares the same off-chip matching network with the transmit path. 1.3 Transceiver Functions MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 7 NXP Semiconductors

1.3.2 Transmit

The MCR20A transceiver transmits OQPSK modulation adjusting power and channel selection determined by the user's application. After the channel of operation is determined, coarse and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is then routed to a multi-stage amplifier for transmission. The differential signals at the output of the PA (RFOUTP, RFOUTN) are converted as single ended (SE) signals with off-chip components as required.

1.3.3 PLL Synthesizer

The MCR20A Phase Locked Loop synthesizer provides a signal to either the transmit PA or the receive mixer. The reference is derived from the (typically 32 MHz) crystal oscillator. The PLL divider is a Fractional-N type with a step size of Fref/65536 or 488Hz with a 32 MHz reference. After the channel of operation is determined, coarse and fine tuning is executed within the Fractional-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is then routed to a multi-stage amplifier for transmission. Unlock detect circuitry drives an abort of the transceiver sequence in the event of abnormal behavior and asserts an interrupt. Modulation is performed inside the PLL during transmit and the modulated signal is routed to the PA. This signal is not modulated in receive and the carrier routed to the receive mixer.

1.3.4 Low power preamble search (LPPS)

The MCR20A transceiver provides a unique low power preamble search (LPPS) in the receive mode operation. A summary of this mode of operation when selected is described as follows:

• Whenever a receive cycle is initiated, the receiver is not turned fully on to save current until receive energy of a preset level is detected.
• The receiver will turn fully on only when triggered by energy at a pre-determined preset level thus enabling reception of the expected frame. Afterwards, the receiver will begin operating in the full-on state that is considered to be the same as the standard receive state.
• The preset level can be programmed for various receiver input power levels. Transceiver Functions 8 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

Use of the LPPS mode provides two distinct advantages:

• Reduced “listen” mode current—The receive current is significantly reduced while waiting for a frame. If a node is a coordinator, router, or gateway and it spends a significant percentage of its RF-active time waiting for incoming frames from clients or other devices, the net power savings can be significant.
• Reduced sensitivity as a desired effect—The LPPS mode provides different levels of reduced sensitivity. If a node operates in a densely populated area, it may be desirable to de-sensitize the receiver such that the device does not respond to incoming frames with an energy level below the desired threshold. This could be useful for security, net efficiency, reduced noise triggering, and many other purposes.

1.3.5 Clear channel assessment (CCA), energy detection (ED), and

link quality indicator (LQI) The MCR20A transceiver supports three clear channel assessment (CCA) modes of operation including energy detection (ED) and link quality indicator (LQI). Functionality for each of these modes is as follows.

1.3.5.1 CCA mode 1

CCA mode 1 has two functions:

• To estimate the energy in the received baseband signal. This energy is estimated based on the receiver signal strength indicator (RSSI).
• To determine whether the energy is greater than a set threshold. The estimate of the energy can also be used as the link quality metric. In CCA mode 1, the MCR20A transceiver must warm-up from idle to receive mode where RSSI averaging takes place.

1.3.5.2 CCA mode 2

CCA mode 2 detects whether there is any 802.15.4 signal transmitting in the frequency band that an 802.15.4 transmitter intends to transmit. From the definition of CCA mode 2 in the 802.15.4 standard, the requirement is to detect an 802.15.4 complied signal. Whether the detected energy is strong or not is not important for CCA mode 2. Transceiver Functions MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 9 NXP Semiconductors

1.3.5.3 CCA mode 3

CCA mode 3 as defined by the 802.15.4 standard is implemented using a logical combination of CCA mode 1 and CCA mode 2. Specifically, CCA mode 3 operates in one of two operating modes:

• CCA mode 3 is asserted if both CCA mode 1 and CCA mode 2 are asserted.
• CCA mode 3 is asserted if either CCA mode 1 or CCA mode 2 is asserted. This mode setting is available through a programmable register.

1.3.5.4 Energy detection (ED)

Energy detection (ED) is based on receiver signal strength indicator (RSSI) and correlator output for the 802.15.4 standard. ED is an average value of signal strength. The magnitude from this measurement is calculated from the digital RSSI value that is averaged over a 128 μs duration.

1.3.5.5 Link quality indicator (LQI)

The link quality indicator (LQI) is based on the receiver signal strength indicator (RSSI) or correlator output for the 802.15.4 standard. In this mode, the RSSI measurement is calculated during normal packet reception. LQI computations for the MKW20 transceiver are based on either digital RSSI or correlator peak values. This setting is executed through a register bit where the final LQI value is available 64 μs after preamble is detected. If a continuous update of LQI based on RSSI throughout the packet is desired, it can be read in a separate 8-bit register by enabling continuous update in a register bit.

1.3.5.6 LQI ED RSSI

The following figure shows the MCR20A transceiver's reported energy detect (ED) as a function of input power. The figure also shows the link quality indication (LQI)/ RSSI_CONT (continuous) and the RSSI as a function of a unitless numeric register reading. LQI is available 64 μs after the preamble is detected. RSSI_CONT can be used to read LQI when a continuous value averaged over the entire received packet is desired. This value may be read as LQI if continuous update of LQI is desired during packet reception (both scaled the same but averaged differently). The curves are measured using the default offset compensation value and can be changed to center the curve if desired. Transceiver Functions 10 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

The following sequences are performed in test software to create the curves that are shown in the figure. Similar sequences are incorporated into NXP software stacks.

• For ED, the device is configured to perform an ED via write to the register 0x7 with 0x00.
• ED/CCA sequence is started via write to register 0x3 with 0x3
• Register 0 is polled for bit 3 to be set
• RSSI_CONT_EN bit is disabled in indirect 0x25 (CCA_CTRL) all other bits are reset/overwrite values
• Direct register 0x0B is read (CCA final)
• Direct register 0x25 is read (LQI)
• Indirect register 0x5B is read (RSSI)
• Direct register 0x26 is read (RSSI_CONT), however, not enabled in ED case so ignored
• For LQI, the device is configured to perform an LQI via write to the register 0x7 with 0x00.
• The device is configured to perform an LQI via write to the register 0x7 with 0x00
• Receive sequence is started via write to register 0x3 with 0x1
• Register 0 is polled for bit 2 to be set
• RSSI_CONT_EN bit is enabled in indirect 0x25
• RSSI_CONT_EN bit is disabled in indirect 0x25 (CCA_CTRL) all other bits are reset or overwrite values
• Direct register 0x0B is read (CCA final)
• Direct register 0x25 is read (LQI)
• Indirect register 0x5B is read (RSSI)
• Direct register 0x26 is read (RSSI_CONT), valid for LQI For both LQI and ED the input power is swept with a modulated input signal from -100 dBm to -20 dBm in steps of 1 dBm and the ED and LQI sequences are called during each step and the results recorded. Transceiver Functions MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 11 NXP Semiconductors

Figure 3. ED/LQI relation to RSSI/RSSI_CONT Table 2. Minimum and Maximum Values

The 802.15.4 transceiver integrates (as listed below) hardware features that reduce the software stack size, off-loads functions from the CPU, supports security and improves performance:

• Complete IEEE®802.15 modem
• 2006 packet processor/sequencer
• Internal event timer block with four comparators to assist sequencer and provide timer capability.

1.3.7 Packet processor

The MCR20A transceiver's packet processor performs sophisticated hardware filtering of the incoming received packet to determine whether the packet is both PHY- and MAC-compliant, is addressed to this device, if the device is a PAN coordinator, and whether a message is pending for the sending device. The packet processor greatly reduces the packet filtering burden on software enabling it to tend to higher-layer tasks with a lower latency and smaller software footprint.

1.3.7.1 Features

The MCR20A transceiver's packet processor has the following features:

• Aggressive packet filtering to enable long, uninterrupted MCU sleep periods
• Fully compliant with both 2003 and 2006 versions of the 802.15.4 wireless standard
• Supports all frame types, including reserved types
• Supports all valid 802.15.4 frame lengths
• Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame control field and sequence number
• Supports all source and destination address modes, and also PAN ID compression
• Supports broadcast address for PAN ID and short address mode
• Supports “promiscuous” mode, to receive all packets regardless of address- and rules-checking
• Enables frame type-specific filtering—that is, it rejects all but beacon frames
• Supports SLOTTED and non-SLOTTED modes Transceiver Functions MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 13 NXP Semiconductors

• Includes special filtering rules for PAN coordinator devices
• Enables minimum-turnaround transmit-acknowledge frames for data-polling requests by automatically determining message-pending status
• Assists the MCU to locate pending messages in its indirect queue for data-polling end devices
• Makes available to MCU detailed status of frames that fail address-checking or rules-checking
• Supports dual PAN mode, to enable the device to exist on two PANs simultaneously
• Supports two IEEE addresses for the device
• Supports active promiscuous mode

1.3.8 Packet buffering

The packet buffer is a 128-byte random access memory (RAM) dedicated to the storage of 802.15.4 packet contents for both transmit and receive sequences. For transmit sequences, software stores the contents of the packet buffer starting with the frame length byte at packet buffer address 0 followed by the packet contents at the subsequent packet buffer addresses. For receive sequences, the incoming packet's frame length is stored in a register external to the packet buffer. Software will read this register to determine the number of bytes of packet buffer to read. This facilitates DMA transfer through the SPI. For receive packets, an LQI byte is stored at the byte immediately following the last byte of the packet (frame length +1). Usage of the packet buffer for receive and transmit sequences is on a time-shared basis—that is, the receive packet data will overwrite the contents of the packet buffer. Software can inhibit receive- packet overwriting of the packet buffer contents by setting the PB_PROTECT bit. This will block receive packet overwriting, but will not inhibit transmit content loading of the packet buffer via the SPI.

1.3.8.1 Features

The features of the packet buffer are as follow:

• 128 byte buffer stores maximum length 802.15.4 packets
• Same buffer serves both transmit and receive sequences Transceiver Functions 14 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

• The entire packet buffer can be uploaded or downloaded in a single SPI burst
• Automatic address auto-incrementing for burst accesses
• Single-byte access mode supported
• Entire packet buffer can be accessed in hibernate mode
• Under-run error interrupt supported

1.4 Dual PAN ID

PAN mode. These parameters are described in Table 3. Table 3. PAN0 and PAN1 descriptions parameter sets to configure the hardware for operation on two networks.

1.4.1 Event Timer

The MCR20A transceiver features a 24-bit event timer that can be used in conjunction with the sequencer to provide protocol control as well as timing interrupts. The event timer consists of a continuously running counter and four separate 24-bit comparators. The event timer functionality:

• The event timer counter runs at the 802.15.4 bit rate of 250 kHz (programmable).
• Each comparator has an individual interrupt request capability—the compare status is set when there is a match between the comparator and the timer counter. Each status can be enabled to generate an IRQ.
• A separate 16-bit T2PRIMECMP comparator is provided, which uses only the lower 16 bits of the event timer rather than requiring a full 24-bit compare. For each timer compare enable, when the bit is set, a match on the respective 24-bit compare value to the event timer will cause the corresponding interrupt status bit to become set. If the compare enable is low, then the event timer matches prevent the corresponding interrupt status bit to become set.

2 System and power management

The MCR20A transceiver is a low power device that also supports extensive system control and power management modes to maximize battery life and provide system protection.

2.1 Modes of operation

The transceiver modes of operation include:

• Idle mode
• Doze mode
• Low power (LP) / hibernate mode
• Reset / powerdown mode
• Run mode System and power management 16 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

2.2 Power management

• Preamble search
• Preamble search sniff
• Low power preamble search (LPPS)
• Fast antenna diversity (FAD) preamble search
• Packet decoding

3 Radio Peripherals

MCU, to control the external RF modules and circuitry, and to control the GPIO.

3.1 Clock output (CLK_OUT)

• XTAL domain can be completely gated off (hibernate mode)
• SPI communication allowed during hibernation

Table 4. CLK_OUT table Table continues on the next page...

Table 4. CLK_OUT table (continued)

1. May require high drive strength for proper signal integrity.
2. DEFAULT if GPIO5/BOPT = 0
3. DEFAULT if GPIO5/BOPT = 1

available to adjust the CLK_OUT I/O pad drive strength.

3.2 General-purpose input output (GPIO)

general-purpose inputs with internal pull-up devices enabled.

• Programmable output drive strength
• Programmable output slew rate
• Hi-Z mode
• Programmable as outputs or inputs (default) Radio Peripherals 18 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

Table 5. Pin configuration summary

1. For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.
2. Leakage current applies for the full range of possible input voltage conditions.
3. Rise and fall time values in reference to 20% and 80%
4. Propagation Delay measured from/to 50% voltage point.
5. Full drive values provided are in reference to a 75 pF load.
6. Partial drive values provided are in reference to a 15 pF load.

3.2.1 Serial peripheral interface (SPI)

single-byte or a burst mode of unlimited length. especially during the register-initialization phase of the radio.

The SPI design features a compact, single-byte control word, reducing SPI access latency to a minimum. Most SPI access types require only a single-byte control word, with the address embedded in the control word. During control word transfer (the first byte of any SPI access), the contents of the IRQSTS1 register (the radio's highest- priority status register) are always shifted out so that the MCU obtains access to IRQSTS1, with the minimum possible latency, on every SPI access.

3.2.1.1 Features

The SPI interface features:

• 4-wire industry standard interface, supported by all MCUs
• SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses)
• SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses)
• Write and read access to all radio registers (direct and indirect)
• Write and read access to packet buffer
• SPI accesses can be single-byte or burst
• Automatic address auto-incrementing for burst accesses
• Asynchronous mode
• Entire packet buffer can be uploaded or downloaded in a single SPI burst
• Entire packet buffer and most registers can be accessed during hibernation mode
• All GPIO-related registers are accessible in hibernation mode
• Built-in synchronization inside the SPI module to or from the rest of the radio
• R_MISO can be tristated when the SPI is inactive, enabling multi-slave configurations

3.2.2 Antenna diversity

To improve the reliability of RF connectivity to long range applications, the antenna diversity feature is supported without using the MCU through use of four dedicated control pins (package pins 23, 24, 25, and 26). Radio Peripherals 20 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

Fast antenna diversity (FAD) mode supports this radio feature and, when enabled, allows the selection between two antennas during the preamble phase. By continually monitoring the received signal, the FAD block will select the first antenna of which the received signal has a correlation factor above a predefined progammable threshold. The FAD accomplishes the antenna selection by sequentially switching between the two antennas testing for the presence of suitably strong s0 symbol where the first antenna to reach this condition is then selected for the reception of the packet. Note that the antenna with the strongest signal is not necessarily picked but the antenna that first meets the signal requirements. Each of the antennas are monitored for a period of 28 μs. The antenna switching is continued until 1.5 valid s0 symbols are detected. The demodulator then continues with normal preamble search before declaring Preamble Detect.

3.2.3 RF Output Power Distribution

The following figure shows the linear region of the output and the typical power distribution of the radio as a function of PA_PWR [4:0] range. The PA_PWR [4:0] is the lower 5 bits of the PA_PWR 0x23 direct register and has a usable range of 3 to 31 decimal. Radio Peripherals MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 21 NXP Semiconductors

Figure 4. MCR20A transmit power vs. PA_PWR step

4 Serial peripheral interface (SPI)

• Slave select (R_SSEL_B)—A transaction on the SPI port is framed by the active low R_SSEL_B input signal.
• SPI clock (R_SCLK)—The host drives the SPICLK input to the MCR20A transceiver. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. Serial peripheral interface (SPI) 22 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

• Master out/slave in (MOSI)—Incoming data from the host is presented on the MOSI input.
• Master in/slave out (MISO)—The MCR20A transceiver presents data to the master on the MISO output. The SPI interface is capable of operating with either the crystal oscillator ON (synchronous mode), or OFF (asynchronous mode; i.e., hibernate).

Figure 5. SPI read transaction diagram

4.1 SPI transfer protocol

Figure 6. SPI Transfer Protocol

4.2 SPI control word

depicts an overview of the control word. Table 6. Control word overview

5 MCR20A Operating Modes

• Reset or power down
• Low power (LP) or hibernate
• Doze (low power with reference oscillator active)
• Idle
• Receive
• Transmit Table 7 lists and describes the transceiver's power modes and consumption.

Table 7. Transceiver power modes

1. Conditions: VBAT and VBAT_2 = 2.7 V, nominal process @ 25°C.
2. While in Doze mode, 4 MHz maximum frequency can be selected for CLK_OUT.
3. Signal sensitivity = -102 dBm.

5.1 Transceiver Transmit Current Distribution

radio and its current consumption. Figure 7. MCR20A transmit power vs transmit current

6.1 Maximum ratings

Table 8. Maximum ratings Table continues on the next page...

Table 8. Maximum ratings (continued) restricted to the limits in the electrical characteristics or recommended operating conditions tables.

1. Digital interface supply voltage (VDDINT). In this device it is required VBAT, VBAT2 are common and VBAT2 is equal

to VDDINT and are supplied from a single un-regulated source.

1. Electrostatic discharge on all device pads meet this requirement

recommended operating conditions tables.

6.2 Radio recommended operating conditions

Table 9. Recommended operating conditions

6.3.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

6.3.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

6.3.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 6.3 Ratings 28 MCR20AVHM Data Sheet, Rev. 3.2, 07/2016 NXP Semiconductors

7 AC electrical characteristics

Figure 8. Input signal measurement reference

8 Nonswitching electrical specifications

8.1 EMC radiated emissions operating behaviors

Table 10. EMC radiated emissions operating behaviors 1

1. This data was collected on a MK20DN128VLH5 64pin LQFP device.
2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

whole number, from among the measured orientations in each frequency range.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

8.2 Designing with radiated emissions in mind

• Go to www.nxp.com.
• Perform a keyword search for “EMC design.”

8.3 Capacitance attributes

Table 11. Capacitance attributes

9 Thermal specifications

9.1 Thermal operating requirements

Table 12. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

10.1 DC electrical characteristics

Table 13. DC electrical characteristics (V BAT, VBAT2 = 2.7 V, TA=25 °C, unless otherwise

1. To attain specified low power current, all GPIO and other digital IO must be handled properly.

10.2 AC electrical characteristics

Table 14. Receiver AC electrical characteristics (V BAT, VDDINT = 2.7 V, TA=25 °C, fref = 32 MHz Table continues on the next page...

1. Measurement is referenced to the package pin.

Table 15. Transmitter AC electrical characteristics (V BAT, VDDINT = 2.7 V, TA=25 °C, fref = 32

1. Measurement is referenced to the package pin.
2. Measurement is referenced to the package pin on the output of the Tx/Rx switch. It does not degrade more than ±2 dB

to +8 dBm in 21 steps @ 2 dBm / step.

1. Measured with output power set to nominal (0 dBm) and temperature @ 25°C. Trap filter is needed.

Table 16. RF port impedance

2.360 GHz

2.420 GHz

2.480 GHz

10.3 SPI timing: R_SSEL_B to R_SCLK

Figure 9. SPI timing: R_SSEL_B to R_SCLK

10.4 SPI timing: R_SCLK to R_MOSI and R_MISO

guaranteed by the radio SPI (R_MISO).

Figure 10. SPI timing: R_SCLK to R_MOSI and R_MISO

11 Crystal oscillator reference frequency

reference design and recommended crystal usage.

11.1 Crystal oscillator design considerations

crystal load capacitance is external.

11.2 Crystal requirements

The suggested crystal specification for the MCR20A transceiver is shown in Table 17. temperature range and the use of crystal capacitive load trimming. Table 17. MCR20A transceiver's crystal specifications Table continues on the next page...

Table 17. MCR20A transceiver's crystal specifications (continued)

1. A wider aging tolerance may be acceptable when the application uses trimming at production final test.

12.1 Pin assignments

This figure shows the MCR20A transceiver's package pin assignment.

Figure 11. Pin assignment

12.2 Pin function table

Table 18. Pin function

2 VBAT Power Input Battery Voltage Connect to system VDD supply

3 XTAL_32M Analog Output RF 32 MHz reference oscillator output

4 EXTAL_32M Analog Input RF 32 MHz references oscillator input

5 GPIO1 Digital Input/Output General-Purpose IO GPIO

6 GPIO2 Digital Input/Output General-Purpose IO GPIO

Table continues on the next page...

Table 18. Pin function (continued)

7 GPIO3 Digital Input/Output General-Purpose IO GPIO

8 GPIO4 Digital Input/Output General-Purpose IO GPIO

9 GPIO5 Digital Input/Output General-Purpose IO GPIO or CLK_OUT default state

10 RST_B Digital Input/Output Digital Device asynchronous hardware

11 R_MISO Digital Input/Output Digital SPI MISO

12 R_MOSI Digital Input/Output Digital SPI MOSI

13 R_SCLK Digital Input/Output Digital SPI clock

14 R_SSEL_B Digital Input/Output Digital SPI slave select

15 IRQ_B Digital Input/Output Digital Interrupt command signal

16 CLK_OUT Digital Output RF Programmable clock source

18 VBAT2 Power Input Battery Voltage Connect to system VDD supply.

19 GPIO6 Digital Input/Output General-Purpose IO GPIO

20 GPIO7 Digital Input/Output General-Purpose IO GPIO

21 GPIO8 Digital Input/Output General-Purpose IO GPIO

22 DTM0 — Factory Test Do not connect.

23 ANT_A Digital Input/Output Antenna Diversity Programmable sink and source

24 ANT_B Digital Input/Output Antenna Diversity Programmable sink and source

25 RX_SWITCH Digital Input/Output Control Switch Programmable sink and source

26 TX_SWITCH Digital Input/Output Control Switch Programmable sink and source

27 VSSA_PA — Gnd RF ground

28 RF_OUTP RFInput/Output RF Bidirectional RF input/output

29 RF_OUTN RFInput/Output RF Bidirectional RF input/output

30 VSSA_PA2 — Gnd RFground

33 GND_RF — — Connect to RF ground

34 GND_PA — — Connect to RF ground

Table continues on the next page...

35 GND_RF — — Connect to RF ground

13 Dimensions

13.1 Obtaining package dimensions

Package dimensions are provided in package drawings. The following table provides a revision history for this document. Table 19. Revision History 3.2 07/2016 Added section 5.1 "Transceiver Transmit Current Distribution".

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