MCP8021

MCP8021 MICROCHIP | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 66

Technical content

Features

• AEC-Q100 Automotive Qualified, See Product Identification System
• Three Half-Bridge Drivers Configured to Drive External High-Side NMOS and Low-Side NMOS MOSFETs: - Independent input control for high-side and low-side NMOS MOSFET gate drives - Typical peak output current: 0.5A @ 12V - Shoot-through protection - Overcurrent and short-circuit protection
• Three Operational Amplifiers (MCP8022)
• Fixed Output Linear Regulator: - 3.3V or 5.0V @ 70 mA - True current foldback
• Supply Current: - Sleep mode: 5 µA typical - Standby mode: < 330 µA (MCP8021) - Standby mode, op amps off: < 330 µA (MCP8022) - Standby mode, op amps on: < 1300 µA (MCP8022)
• Dedicated WAKE Pin for Sleep Mode Recovery
• Dedicated FAULT Pin
• Single Wire UART Communications
• Supply Voltage Range: 4V-40V
• Operational Voltage Range: 6.25V-29V
• Gate Drive Undervoltage Lockout: 4.5V
• Supply Voltage Undervoltage Shutdown: 4.5V
• Supply Voltage Undervoltage Lockout (UVLO): 6.25V
• Overvoltage Lockout (OVLO): 29V
• Temperature Range (T J): -40°C to +165°C
• Thermal Shutdown

Applications

• Automotive Applications like Fuel, Water, Oil Pumps, Ventilation Motors, Window Lift, Trunk Openers, Sun Roof
• Home Appliances
• Permanent Magnet Synchronous Motor (PMSM) Control
• Hobby Aircraft, Boats, Vehicles

Description

The MCP8021/2 devices are 3-phase Brushless DC (BLDC) power modules containing three integrated half-bridge drivers, capable of driving three external NMOS/NMOS transistor pairs. The three half-bridge drivers are capable of delivering a peak output current of 0.5A at 12V for driving high-side and low-side NMOS MOSFET transistors. The drivers have shoot- through, overcurrent and sh ort-circuit protection. A Sleep mode has been added to achieve a typical “key off” quiescent current of 5 µA. The MCP8021/2 devices in tegrate a 3.3V or 5.0V LDO regulator for host and peripheral power, an overtemperature sensor and user-configurable functions. The user-configurable functions are: dead time, blank- ing time, op amp enable/disable during standby, enable/ disable Sleep mode, enable/disable overcurrent detection and enable/disable gate drive undervoltage protection. The on-board 3.3V or 5.0V dropout voltage regulators are capable of delivering 70 mA of current. The voltage option is selected by part number. The MCP8022 device adds three independent operational amplifiers for general use. The MCP8021/2 functional operation is specified over a junction temperature range of -40°C to +165°C. 5x5 mm VQFN and 28-Lead TSSOP-EP . Package options for the MCP8022 include 40-Lead 5x5 mm VQFN and 38-Lead TSSOP-EP. 3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module, Sleep Mode, Op Amps

DS20006265D-page 2  2020-2024 Microchip Technology Inc. and its subsidiaries CAP1 PWMCL PWMCH PWMBL PWMBH VBA HSA VBB HSB PHB FAULT OE DE2 WAKE GND CAP2 VDD VREG VBOOT LSA Exposed Pad (EP) 8 28 V BOOT VREG VDD CAP2 CAP1 PWMCL PWMCH PWMBL PWMBH PWMAL VBC PHB HSB VBB PHA HSA VBA LSC LSB LSA Exposed Pad (EP) LSB LSC PWMAL PWMAH PHA VBC HSC PHC HSC18 PHC17 GND16 WAKE15 PWMAH FAULT OE DE2 5m mx5m mQFN-28* 4.4 mm TSSOP-28* *Includes Exposed Thermal Pad (EP), see Table 3-1. 5 mm x 5 mm VQFN-28*

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 3 MCP8021/2 VREG VDD CAP2 CAP1 DE2 PWMCL PWMCH PWMBL PWMBH PWMAL HSB VBB PHA HSA VBA GND LSC LSB LSA VBOOT1 Exposed Pad (EP) PHB28 VBC27 HSC26 PHC25 PWMAH FAULT OE OUT3 GND24 WAKE23 IN1+22 IN1- IN3- IN3+ OUT2 IN2- IN2+ 19 OUT120 PWMCL PWMCH PWMBL PWMBH PWMAL VBA HSA VBB HSB PHB OUT3 IN3- IN3+ OUT2 IN2- CAP1 CAP2 VDD VREG GND Exposed Pad (EP)15 11 40 VBOOT LSA PWMAH DE2 PHA VBC OUT1 IN2+

23 HSC

22 PHC

5m mx5m mQFN-40* 4.4 mm TSSOP-38* *Includes Exposed Thermal Pad (EP), see Table 3-2. 5 mm x 5 mm VQFN-40*

DS20006265D-page 4  2020-2024 Microchip Technology Inc. and its subsidiaries Functional Block Diagram PWM1H PWM2H PWM3H PWM1L PWM2L PWM3L Control Logic HSA HSB HSC LSA LSB LSC PHA PHB PHC +12V GND FAULT OE 70 mA VREG LDO 12V @ 30 mA Regulated Charge Pump CAP1 CAP2VDD VREG DE2 UART I I I I I I I O O O O O O O I I I VBOOT +12V+VINT VBA VBB VBC EP MCP8022 IN1+ IN2+ IN3+ IN1- IN2- IN3- OUT3 OUT2 OUT1 WAKE PO VREG VREG VREG VREG

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 5 MCP8021/2 Typical Application Circuit Host Controller O O O O O O Tx O I HSA HSB HSC LSA LSB LSC PHB PHC GND V BOOT EP 47 K: A B C 22 K: A/D A/D A/D VDD GND PWMAH PWMBH PWMCH PWMAL PWMBL PWMCL Control Logic PHA +12V /FAULT OE 70 mA VREG LDO 12V @ 30 mA Regulated Charge Pump CAP1 CAP2 VDD VREG DE2 UART I I I I I I I O O O O O O O I I I +12V VBA VBB VBC MCP8022 IN1+ IN2+ IN3+ IN1- IN2- IN3- OUT3 OUT2 OUT1 Rx 2 K: WAKE PO VREG VREG VREG VREG CVREG CVDD CCP CVBOOT Note: A Schottky diode between the CAP1 pin and HVSS is recommended to ensure that the CAP1 pin absolute minimum voltage specification is maintained.

DS20006265D-page 6  2020-2024 Microchip Technology Inc. and its subsidiaries

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† ESD and Latch-Up Protection: Note 1: Transient junction temperatures should not exceed one second in duration. Sustained junction temperatures above +170°C may impact the device reliability. 2: The maximum allowable power dissipation is a functi on of ambient temperature, the maximum allowable junction temperature and the thermal resi stance from junction to air (i.e., T A, T J, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum +165°C rating. Sustained junction temperatures above +165°C can impact the device reliability. † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maxi- mum rating conditions for extended periods may affect device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions POWER SUPPLY INPUT Input Operating Voltage V DD 4.5 — 40 V V REG active 6.0 — 29.0 Driver output active Input Supply Current (MCP8021) ISUP — 5 15 µA Sleep mode, T J = +25°C — 180 330 Standby, OE = 0V — 500 — Active, V DD > 13, 5V, OE > VDIG_HI_TH — 1200 — Active, V DD = 6V, TJ = +25°C Input Supply Current (MCP8022) I SUP — 5 15 µA Sleep mode, T J =+ 2 5 ° C — 200 350 Standby, OPAMP = 1, OE = 0V — 800 1300 Standby, OPAMP = 0, OE = 0V — 1000 — Active, V DD > 13, 5V, OE > VDIG_HI_TH — 1500 — Active, OE > V DIG_HI_TH, VDD =7 V , TJ = +25°C Note 1: Limits based on design, simulation or characterization. Not production tested.

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 7 MCP8021/2 BIAS GENERATOR +12V Regulated Charge Pump (VBOOT) Charge Pump Current I CP 20 — — mA V DD =9 . 0 V Charge Pump Start CP START 12.50 12.75 — V Falling Charge Pump Stop CP STOP — 13.25 14 V Rising Charge Pump Frequency CP FSW — 76.80 — kHz V DD =9 . 0 V —0 — V DD = 14V Charge Pump Switch Resistance CPRDSON —1 4 —  RDSON sum of high-side and low-side (Note 1) Output Voltage V BOOT —1 2 —V V DD  14V, IOUT =3 0m A 91 2 — 7 V VDD 14V, CCP = 150 nF, IOUT =2 0m A CCP = 270 nF, IOUT =1 5m A Output Voltage Tolerance |TOLV OUT12|— — 4 . 0 % I OUT =3 0m A Output Capability I BOOT 30 — — mA Average current Output Current Limit I BOOTLIMIT 50 60 80 mA Average current Output Voltage Temperature Coefficient TCVOUT12 — 160 — ppm/°C Note 1 Line Regulation | VOUT/ (VOUT x )| IOUT =3 0m A Load Regulation | VOUT/VOUT|— 0 . 2 1 . 0 % I OUT = 0.1 mA to 30 mA, VDD = 14V Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz, I OUT =1 0m A (Note 1) Output Capacitor Capacitance Range CVBOOT 4.7 — 10 µF Ceramic, Tantalum, Electrolytic (Note 1) Output Capacitor ESR Range CESR VBOOT 0.010 — 1.0  Note 1 Flying Capacitor Capacitance Range CCP 100 220 1000 nF Note 1 VBOOT Ready Threshold V 12SM_PG —5 0 — % V BOOT State machine VBOOT Power Good threshold to move to next state (Note 1) AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Limits based on design, simulation or characterization. Not production tested.

DS20006265D-page 8  2020-2024 Microchip Technology Inc. and its subsidiaries +3.3V/+5V Linear Regulator (VREG) Output Voltage V REG —— —V V DD =6 V , IOUT =7 0m A 4.8 5 5.2 V REG =5 V 3.168 3.3 3.432 V REG =3 . 3 V Output Voltage Tolerance |TOLV REG|— — 4 . 0 % Output Current I OUT 70 — — mA Average current Output Foldback Current Corner I FOLD 80 95 120 mA Average current Output Foldback Current Limit I FOLD_LIM —1 0 — m A R LOAD =1 0m  Line Regulation | VOUT/ (VOUT x VDD)| —0 . 1 0 . 5 % / V V REG = 3.3V: 6V < VDD < 19V, IOUT = 70 mA; VREG =5 V : 7 . 5 V < VDD < 19V, IOUT = 70 mA Load Regulation | VOUT/VOUT|— 0 . 2 1 . 0 % I OUT = 0.1 mA to 70 mA Power Supply Rejection Ratio PSRR — 60 — dB f = 1 kHz, I OUT =1 0m A (Note 1) Output Capacitor Capacitance Range CVREG 4.7 — 30 µF Ceramic, Tantalum, Electrolytic (Note 1) Output Capacitor ESR Range CESR VREG 0.010 — 1.0  Note 1 Voltage Supervisor VREG Undervoltage Fault Inactive VREGUVFINACT —9 2 — % V REG VREG rising VREG Undervoltage Fault Active VREGUVF ACT —8 8 — % V REG VREG falling VREG Undervoltage Fault Hysteresis VREGUVFHYS —4 — % V REG VDD Undervoltage Lockout Inactive UVLOINACT — 6.0 6.25 V Rising VDD Undervoltage Lockout Active UVLO ACT 5.1 5.5 — V Falling VDD Undervoltage Lockout Hysteresis UVLOHYS —0 . 5 — V VDD Undervoltage Shutdown Active UVSHDNACT 4.0 4.25 4.5 V V DD < UVSHDNACT VDD Undervoltage Shutdown Inactive UVSHDNINACT UVLOINACT VV DD >U V L OINACT VDD Overvoltage Lockout Active OVLO ACT — 32.0 33.0 V V DD rising VDD Overvoltage Lockout Inactive OVLOINACT 29.0 30.0 — V V DD falling VDD Overvoltage Lockout Hysteresis OVLOHYS —2 . 0 — V Temperature Supervisor Thermal Warning Temperature T WARN — 140 — °C Rising temperature Thermal Warning Hysteresis TWARN — 15 — °C Falling temperature Thermal Shutdown Temperature TSD 170 210 — °C Rising temperature (Note 1) Thermal Shutdown Hysteresis TSD — 25 — °C Falling temperature AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Limits based on design, simulation or characterization. Not production tested.

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 9 MCP8021/2 MOTOR CONTROL UNIT Gate Output Drivers Output Driver Source Current I SOURCE 0.25 0.37 — A HS[A:C], LS[A:C] (Note 1) Output Driver Sink Current I SINK 0.3 0.49 — A HS[A:C], LS[A:C] (Note 1) Output Driver Source Resistance RDSONSOURCE —1 4 2 6  IOUT = -10 mA, HS[A:C], LS[A:C] Output Driver Sink Resistance LS RDSONSINKLS — 14 26  IOUT = 10 mA, LS[A:C] Output Driver Sink Resistance HS Dynamic RDSONSINKHS- DYN —1 4 2 6  IOUT = 10 mA, HS[A:C], t < 1 ms Output Driver Sink Resistance HS RDSONSINKHS — 19 31  IOUT = 10 mA, HS[A:C] Output Driver Fault Blanking Time (UVLO and OCP); Set in the DRVBL[1:0] bits (CFG2[1:0]) tBLANK 3900 4400 4900 ns 00 – Default (Note 1) 2000 2200 2400 01 (Note 1) 900 1100 1300 10 (Note 1) 400 550 700 11 (Note 1) Output Driver UVLO Threshold V DUVLO 4 — 4.5 V Configuration Register 0 (bit 3 = 0) Output Driver PWM Dead Time; Set in the DRVDT[2:0] bits (CFG2[4:2]) tPWM_DEAD 1800 2000 2200 ns 000 – Default (Note 1) 1550 1750 1950 001 (Note 1) 1350 1500 1650 010 (Note 1) 1100 1250 1400 011 (Note 1) 900 1000 1150 100 (Note 1) 650 750 900 101 (Note 1) 450 500 650 110 (Note 1) 200 250 350 111 (Note 1) Output Driver Propagation Delay Time On tGATE_PROP_ON — 40 80 ns From PWMxy active to HSx/LSx > 10% (Note 1) Output Driver Propagation Delay Time Off tGATE_PROP_OFF — 40 80 ns From PWMxy inactive to HSx/LSx < 90% (Note 1) Output Driver HS Drive Voltage V HS 4.5 12 12.5 V With respect to Phase pin (Note 1) Output Driver LS Drive Voltage V LS 4.5 12 12.5 V With respect to ground (Note 1) Output Driver Short-Circuit Protection Threshold (High-Side: VDD – VPHX), (Low-Side: VPHX – PGND); Set in the EXTOC[1:0] bits (CFG0[1:0]) DSC_THR 0.230 0.250 0.270 V 00 – Default (Note 1) 0.470 0.500 0.530 01 (Note 1) 0.720 0.750 0.780 10 (Note 1) 0.960 1.000 1.040 11 (Note 1) Output Driver Short-Circuit Filter Time TSC_DLY 230 — 600 ns C LOAD = 1000 pF, VDD = 12V, detection after filtering (Note 1) Filter Time for All Other Faults T FLT_DLY 1400 — 3600 ns Note 1 Power-Up or Sleep to Standby t POWER —5 — m s I VREG =7 0m A AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Limits based on design, simulation or characterization. Not production tested.

DS20006265D-page 10  2020-2024 Microchip Technology Inc. and its subsidiaries Standby to Motor Operational t MOTOR — 35 — µs OE high-low-high transition < 1 ms Fault clearing pulse (Note 1) — 5 10 ms OE low-high transition, Standby state to operational (Note 1) — — 16 ms OE low-high transition, Standby state to operational if VBOOT fails to reach V12SM_PG (Note 1) Fault to Driver Output Turn-Off T FAULT_OFF —— — µ s C LOAD = 1000 pF, VDD = 12V, time after Fault occurs (Note 1) — 0.420 1.0 XOCP (Note 1) —2 . 4 4 . 0 O V L O (Note 1) — 4.2 6.0 All other Faults (Note 1) OE Low to Driver Output Turn-Off TDEL_OFF —3 . 2 4 . 0 µ s C LOAD = 1000 pF, VDD = 12V, time after OE = Low (Note 1) OE Low to Standby State t STANDBY 0.9 — 1.35 ms Time after OE = Low, SLEEP bit = 0 OE Low to Sleep State t SLEEP 0.9 — 1.35 ms Time after OE = Low, SLEEP bit = 1 OE Fault Clearing Pulse t FAULT_CLR 1 — 900 µs OE high-low-high transition time Operational Amplifiers (MCP8022) Input Offset Voltage V OS -10 — +10 mV V CM =0 V Input Offset Temperature Drift VOS/TA — ±2.0 — µV/°C V CM =0 V (Note 1) Input Bias Current I B -1 — +1 µA Common-Mode Input Range V CMR -0.3 — V REG V Common-Mode Rejection Ratio CMRR — 80 — dB Freq = 1 kHz, I OUT =1 0µ A (Note 1) Maximum Output Voltage Range V OL, VOH 0.15 — V REG – 0.300 VI OUT = ±200 µA Slew Rate SR — ±7 — V/µs Symmetrical, C LOAD =2 0p F (Note 1) Gain Bandwidth Product GBWP 4 10.0 — MHz Note 1 I/O PORTS Digital Interface Digital Input/Output DIGITAL I/O 0—5 . 5 V V REG = 5.0V version (Note 1) 0—3 . 3 V REG = 3.3V version (Note 1) Digital Open-Drain Low Voltage DIGITALV I/O —— 5 0 m V I LOAD = 1 mA Digital Input Rising Threshold V DIG_HI_TH — — 1.26 V Digital Input Falling Threshold V DIG_LO_TH 0.54 — — V Digital Input Current I DIG — 30 100 µA V DIG =3 . 0 V —0 . 2 — V DIG =0 V Input Pull-Down Resistance R PULLDN —5 1 — k  PWM[A:C]H/L, OE pins AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Limits based on design, simulation or characterization. Not production tested.

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 11 MCP8021/2 Analog Interface Analog Low-Voltage Input ANALOG VIN 0 — 5.5 V Excludes high-voltage pins (Note 1) Analog Low-Voltage Output ANALOG VOUT 0— V REG V Excludes high-voltage pins (Note 1) WAKE Input Input Voltage WAKE I/O 0— V DD V Input Rising Threshold V WAKE_HI_TH — — 1.26 V (Note 1) Input Falling Threshold V WAKE_LO_TH 0.54 — — V Input Current I WAKE —0 . 2 —µ A V WAKE =0 . 0 V (Note 1) —7 0 — V WAKE =3 . 3 V (Note 1) —1 0 6 — V WAKE =5 . 0 V (Note 1) —5 9 6 — V WAKE =2 8 V (Note 1) Input Pull-Down Resistance R WAKE_PULLDN —5 1 — k  Wake-Up Signal Setup Time t WAIT_SETUP 150 — — µs Minimum time WAKE pin must be logic low before rising edge of wake-up pulse DE2 Communications Baud Rate BAUD 9030 9600 10170 bps Half-duplex Power-Up Delay PU_DELAY — 6 10 ms Time from rising V DD  6V to DE2 starts sending POR message, CVREG = 1 µF (Note 1) DE2 Sink Current I DE2_SINK 1— — m A V DE2  50 mV (Note 1) DE2 Message Response Time t DE2_RSP 0 — 1 ms Time from last received Stop bit to response Start bit DE2 Host Wait Time t DE2_WAIT 2.8 — — ms Minimum time for host to wait for response; three packets based on 9600 Baud DE2 Message Receive Time-out DE2RCVTOUT — — 1.45 ms Time after Start bit received to NACK for no Stop bit Auto-Baud Detection Window (Break) ABAUDDET 1.29 — 2.00 ms Window for valid detection of continuous logic low on DE2 link Auto-Baud Response Delay ABAUD DLY —1 . 0 0 — m s D e l a y f r o m A B U A D DET to start of sending 0x55 byte Auto-Baud Complete Delay ABAUD COMP — 2.00 — ms Delay after sending 0x55 byte before exiting auto-baud function Delay Between Bytes of Multibyte Message from Host tDE2_HOST_ MULTI_DLY — — 1.3 ms Delay between message bytes arriving from host AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted: TJ = -40°C to +150°C; typical values are for +25°C, VDD = 13.5V, CVBOOT = 4.7 µF, CVREG =4 . 7µ F , CCP = 220 nF. Parameter Sym. Min. Typ. Max. Units Conditions Note 1: Limits based on design, simulation or characterization. Not production tested.

DS20006265D-page 12  2020-2024 Microchip Technology Inc. and its subsidiaries TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Units Conditions Temperature Ranges (Note 1) Specified Temperature Range T A -40 — +150 °C Operating Temperature Range T J -40 — +165 °C Storage Temperature Range T A -55 — +165 °C Package Thermal Resistances 5 mm x 5 mm 28-Lead VQFN JA — 35 — °C/W 4-Layer JC51-7 standard board, natural convectionJC —1 0— 5 mm x 5 mm 40-Lead VQFN JA — 35 — °C/W 4-Layer JC51-7 standard board, natural convectionJC —1 0— 4.4 mm 28-Lead TSSOP-EP, 0.65 mm Pitch JA — 34 — °C/W 4-Layer JC51-7 standard board, natural convectionJC —5— 4.4 mm 38-Lead TSSOP-EP, 0.50 mm Pitch JA — 34 — °C/W 4-Layer JC51-7 standard board, natural convectionJC —5— Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +165°C rating. Sustained junction temperatures above +165°C can impact the device reliability. ESD, SUSCEPTIBILITY, SURGE AND LATCH-UP TESTING Parameter Standard and Test Condition Value Input Voltage Surges ISO 16750-2 40V for 500 ms ESD HBM with 1.5 k/100 pF CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref E JEDEC JS-001-2017 ±2 kV ESD CDM – Corner Pins ANSI/ESD-STM5.3.1-2009 CDM13073 AEC-Q100-011-Ref_B ±750V ESD CDM – All Other Pins ANSI/ESD-STM5.3.1-2009 CDM13073 AEC-Q100-011-Ref_B ±500V Latch-Up Susceptibility AEC Q100-004, 150°C JEDEC JESD78 > 100 mA

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 13 MCP8021/2

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated: TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in junction temperature over the ambient temperature is not significant. FIGURE 2-1: Fault Low to DE2 Message Delay. FIGURE 2-2: Bootstrap Voltage @ 92% Duty Cycle. FIGURE 2-3: Sleep Current vs. Temperature (MCP8022). FIGURE 2-4: Driver RDSON vs. Temperature. FIGURE 2-5: Auto-Baud vs. Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tabl es, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 5µ s / d i v 1V/div

10 V/div10 V/div

10 V/div

10 µs/div 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ‐40 ‐10 20 50 80 110 140 IVDD Sleep Mode Current (µA) Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) RDSON [Ω] Switch ON Switch OFF 9000 9100 9200 9300 9400 9500 9600 9700 9800 9900 ‐40 ‐20 0 20 40 60 80 100 120 140 DE2 Baud Rate Temperature (°C)

DS20006265D-page 14  2020-2024 Microchip Technology Inc. and its subsidiaries NOTES:

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 15 MCP8021/2

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1 and Table 3-2. TABLE 3-1: MCP8021 – PIN FUNCTION TABLE 28- Lead TSSOP 28- Lead VQFN Symbol I/O Description 12 5 V BOOT Power Bootstrap and internal low-side gate drive circuit supply output 22 6 V REG Power Linear regulator output 32 7 V DD Power Input supply 4 28 CAP2 I/O Charge pump flying capacitor input 5 1 CAP1 I/O Charge pump flying capacitor input (1) 6 2 PWMCL I Digital input, Phase C lo w-side control, pull-down resistor 7 3 PWMCH I Digital input, Phase C high-side control, pull-down resistor 8 4 PWMBL I Digital input, Phase B low- side control, pull-down resistor 9 5 PWMBH I Digital input, Phase B hi gh-side control, pull-down resistor 10 6 PWMAL I Digital input, Phase A low-side control, pull-down resistor 11 7 PWMAH I Digital input, Phase A hi gh-side control, pull-down resistor 12 8 FAULT O Digital output, driver Fault, open-drain 13 9 OE I Digital input, device out put enable, pull-down resistor 14 10 DE2 I/O Digital input/output, hal f-duplex communications, open-drain 15 11 WAKE I HV digital edge-triggered input, device wake-up from Sleep, pull-down resistor 16 12 P GND Power Power 0V reference 17 13 PHC I/O Phase C high-side MOSFET driver bias reference 18 14 HSC O Phase C high-side N-channel MOSFET gate drive 19 15 VBC Power Phase C high-side MOSFET driver bias 20 16 PHB I/O Phase B high-side MOSFET driver bias reference 21 17 HSB O Phase B high-side N-channel MOSFET gate drive 22 18 VBB Power Phase B high-side MOSFET driver bias 23 19 PHA I/O Phase A high-side MOSFET driver bias reference 24 20 HSA O Phase A high-side N-channel MOSFET gate drive 25 21 VBA Power Phase A high-side MOSFET driver bias 26 22 LSC O Phase C low-side N-channel MOSFET gate drive 27 23 LSB O Phase B low-side N-channel MOSFET gate drive 28 24 LSA O Phase A low-side N-channel MOSFET gate drive EP EP P GND Power Exposed Pad; connect to power 0V reference (P GND) Note 1: A Schottky diode between the CAP1 pin and HVSS is recommended to ensure that the CAP1 pin absolute minimum voltage specification is maintained.

DS20006265D-page 16  2020-2024 Microchip Technology Inc. and its subsidiaries TABLE 3-2: MCP8022 – PIN FUNCTION TABLE 40-Lead VQFN 38-Lead TSSOP Symbol I/O Description 1 5 DE2 I/O Digital input/output, half-duplex communications, open-drain 2 6 PWMCL I Digital input, Phase C low-side control, pull-down resistor 3 7 PWMCH I Digital input, Phase C high-side control, pull-down resistor 4 8 PWMBL I Digital input, Phase B low-side control, pull-down resistor 5 9 PWMBH I Digital input, Phase B high -side control, pull-down resistor 6 10 PWMAL I Digital input, Phase A low-side control, pull-down resistor 7 11 PWMAH I Digital input, Phase A high-side control, pull-down resistor 8 12 OE I Digital input, device output enable, pull-down resistor 91 3 F A U L T O Digital output, driver Fault, open-drain 10 — P GND Power Power 0V reference 11 14 OUT3 O Operational Amplifier 3 output 12 15 IN3- I Operation Amplifier 3 inverting input 13 16 IN3+ I Operation Amplifier 3 noninverting input 14 17 OUT2 O Operational Amplifier 2 output 15 18 IN2- I Operation Amplifier 2 inverting input 16 19 IN2+ I Operation Amplifier 2 noninverting input 17 20 OUT1 O Operational Amplifier 1 output 18 21 IN1- I Operation Amplifier 1 inverting input 19 22 IN1+ I Operation Amplifier 1 noninverting input 20 23 WAKE I HV digital edge-triggered input, devic e wake-up from Sleep, pull-down resistor 21 24 P GND Power Power 0V reference 22 25 PHC I/O Phase C high-side MOSFET driver bias reference 23 26 HSC O Phase C high-side N-channel MOSFET gate drive 24 27 VBC Power Phase C high-side MOSFET driver bias 25 28 PHB I/O Phase B high-side MOSFET driver bias reference 26 29 HSB O Phase B high-side N-channel MOSFET gate drive 27 30 VBB Power Phase B high-side MOSFET driver bias 28 31 PHA I/O Phase A high-side MOSFET driver bias reference 29 32 HSA O Phase A high-side N-channel MOSFET gate drive 30 33 VBA Power Phase A high-side MOSFET driver bias —3 4P GND Power Power 0V reference 31 35 LSC O Phase C low-side N-channel MOSFET gate drive 32 36 LSB O Phase B low-side N-channel MOSFET gate drive 33 37 LSA O Phase A low-side N-channel MOSFET gate drive 34 38 VBOOT Power Bootstrap and internal low-side gate drive circuit supply output 35 — P GND Power Power 0V reference 36 — P GND Power Power 0V reference 37 1 VREG Power Linear regulator output 38 2 V DD Power Input supply 39 3 CAP2 I/O Charge pump flying capacitor input 40 4 CAP1 I/O Charge pump flying capacitor input (1) EP EP P GND Power Exposed Pad;connect to power 0V reference (P GND) Note 1: 1A Schottky diode between the CAP1 pin and HVSS is recommended to ensure that the CAP1 pin abso- lute minimum voltage specification is maintained.

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3.1 Communications Port (DE2)

Open-drain communications node. The DE2 commu- nications is a half-duplex, 9600 baud, 8-bit, no parity communications link. The open-drain DE2 pin must be pulled high by an external pull-up resistor. The pin has a minimum drive capability of 1 mA with a V DE2 of 50 mV when driving low.

3.2 Low-Side PWM Inputs

(PWMAL, PWMBL, PWMCL) Digital PWM inputs for low-side driver control. Each input has a pull-down resistor. The PWM signals may contain dead-time timing or the system may use the CFG2 Configuration register to set the dead time.

3.3 High-Side PWM Inputs

(PWMAH, PWMBH, PWMCH) Digital PWM inputs for high-side driver control. Each input has a pull-down resistor. The PWM signals may contain dead-time timing or the system may use the CFG2 Configuration register to set the dead time.

3.4 Output Enable Input (OE)

The Output Enable input pin is used to enable/disable the output driver and the on-board functions. When OE is high, all device functions are enabled. When OE is low, the device operates in Standby or Sleep mode. When Standby mode is active, the V BOOT output supply and charge pump are disabled. The operational amplifiers in the MCP8022 are also disabled if the OPAMP bit in the CFG0 Configuration register is set. The high-side and low-side gate drive outputs are all set to a low state within 100 ns of OE going low. The device transitions to Standby or Sleep mode, 1 ms after OE goes low. The OE pin may be used to clear any hardware Faults. When a Fault occurs, the OE input may be used to clear the Fault by setting the pin low and then high again. The Fault is cleared by the rising edge of the OE signal if the hardware Fault is no longer active. The OE pin is used to enable Sleep mode when the SLEEP bit in the CFG0 Configuration register is set to a ‘1’. OE must be low for a minimum of 1 ms before the transition to Standby or Sleep mode will occur. This allows time for OE to be to ggled, to clear any Faults, without going into Sleep mode. The OE pin has an internal pull-down resistor.

3.5 Fault Output (FAULT )

Fault output pin. The latched open-drain output will go low while a Fault is active. Table 4-4 shows the Faults that cause the FAULT pin to go low. The pin will stay low until the Fault is inactive and the OE pin is toggled, from low-to-high, to clear the internal Fault latch. The FAULT pin is able to sink 1 mA of current while maintaining less than a 50 mV drop across the output. The FAULT pin will also be active (low) upon initial power-up until the state machine completes the V REG state. This may be used to signal an external host that the driver is ready.

3.6 Power Ground (P GND),

Exposed Pad (EP) Device ground. The PCB ground traces should be short, wide and form a star pattern to the power source. The Exposed Pad (EP) must be soldered to the PCB. The PCB area below the EP should be a copper pour with thermal vias to help transfer heat away from the device.

3.7 Operational Amplifier Outputs

(OUT1, OUT2, OUT3) (MCP8022) Operational amplifier output s. These general purpose amplifiers may be used for current sense gain. The amplifiers are disabled when OE = 0 and the OPAMP bit in the CFG0 Configuration register is set.

3.8 Operational Amplifier Inputs

(IN1+/-, IN2+/-, IN3+/-) (MCP8022) Operational amplifier inverting and noninverting inputs. Used in conjunction with the corresponding amplifier OUTx pin to set amplifier gain. The amplifiers are dis- abled in Standby mode when OE = 0 and the OPAMP bit in the CFG0 Configuration register is set.

3.9 Wake Input (WAKE)

The WAKE pin has an internal pull-down resistor. The device will awaken from Sleep mode, on the rising edge of the WAKE pin, afte r detecting a low state lasting > t WAIT_SETUP on the pin. The WAKE pin is capable of operating at voltage levels up to VDD.

3.10 Motor Phase Inputs

(PHA, PHB, PHC) Phase signals from the motor. These signals provide high-side N-channel MOSFET driver bias reference and Back EMF sense input. The phase signals are also used with the bootstrap capacitors to provide a high-side gate drive via the VBx inputs.

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3.11 High-Side N-MOSFET Gate Driver

Outputs (HSA, HSB, HSC) High-side N-channel MOSFET gate drive signal. Con- nect to the gate of the external MOSFETs. A resistor and gate-to-source capacitor may be used between these pins and the MOSFET gates to limit phase node slew rate and MOSFET current.

3.12 Bootstrap Inputs (VBA, VBB, VBC)

High-side MOSFET driver bias. Connect these pins between the bootstrap ch arge pump diode cathode and the bootstrap charge pump capacitor. The V BOOT output is used to provide th e bootstrap supply voltage at the diode anodes. The phase signals are connected to the other side of the bootstrap charge pump capaci- tors. The bootstrap ca pacitors charge to V BOOT when the phase signals are pulled low by the low-side drivers. When the low-side drivers turn off and the high-side drivers turn on, the phase signal is pulled to V DD, causing the bootstrap voltage to rise to VDD +1 2 V .

3.13 Low-Side N-MOSFET Gate Driver

Outputs (LSA, LSB, LSC) Low-side N-channel MOSFET drive signal. Connect to the gate of the external MOSFETs. A resistor and gate- to-source capacitor may be used between these pins and the MOSFET gates to limit current and slew rate.

3.14 Bootstrap Supply (V BOOT)

Bootstrap supply voltage regulator output. The V BOOT regulator output may be used to power external devices, such as Hall effect sensors or amplifiers. The regulator output requires an output capacitor for stability. The pos- itive side of the output c apacitor should be physically located as close to the V BOOT pin as is practical. A mini- mum capacitance of 4.7 µF is required to ensure stable operation of the VBOOT circuit. Larger capacitances may be used to increase transient performance. The VBOOT regulator is supplied by the internal charge pump when the charge pump is active. When the charge pump is inactive, the VBOOT regulator is supplied by VDD. The type of capacitor used may be ceramic, tantalum or aluminum electrolytic. The low-ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency. 3.15 +3.3V or +5V LDO (V REG) The VREG pin may be a +3.3V or a +5V Low Dropout (LDO) voltage regulator output, depending on device part number. The V REG LDO may be used to power external devices, such as Hall effect sensors, amplifiers or host processors. The VREG LDO is enabled when the device is not in Sleep mode. The LDO requires an out- put capacitor for stability. The positive side of the output capacitor should be physically located as close to the VREG pin as is practical. For most applications, a mini- mum 4.7 µF of capacitance will ensure stable operation of the LDO circuit. Larger capacitances may be used to increase transient performance. The type of capacitor used may be ceramic, tantalum or aluminum electrolytic. The low-ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency.

3.16 Power Supply Input (V DD)

Connect VDD to the main supply voltage. This voltage should be the same as the motor voltage. The driver overcurrent feature is relative to the VDD pin. When the VDD voltage is separate from the motor voltage, the overcurrent protection feature may not be available. The VDD voltage must not exceed the maximum operat- ing limits of the device. Connect a bulk capacitor close to this pin for good load step performance and transient protection. The actual capacitance should be equal to or larger than the sum of the capacitors attached to the driver supply outputs. The attached capacitors are the V REG, VBOOT and VBx (three bootstrap capacitors), and the charge pump capacitances. EQUATION 3-1: V DD BULK CAPACITOR CALCULATION The type of capacitor used may be ceramic, tantalum or aluminum electrolytic. The low-ESR characteristics of the ceramic will yield lower voltage drop, better noise and PSRR performance at high frequency.

3.17 Charge Pump Flying Capacitor

(CAP1, CAP2) Charge pump flying capacitor connection. Connect the charge pump capacitor across these two pins. The Charge Pump Flying Capacitor, C CP, supplies the power for the V BOOT voltage regulator when the charge pump is active. A Schottky diode between the CAP1 pin and HV SS is recommended to ensure that the CAP1 pin absolute minimum voltage specification is maintained. CVDD CVREG + CVBOOT + (3  CVBX) + CCAPx

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4.0 DETAILED DESCRIPTION

4.1 State Diagrams

4.1.1 MCP8021/2 STATE DIAGRAM

FIGURE 4-1: MCP8021/2 State Machine. idle Digital Reset Active POR/BOR VREG (3) vRegRdy = 1 Idle ACTIVE MTC_FAULT ovTemp = 1 (3) vRegRdy = 0 OTP read OK (4) ocMtc = 1 or uvMtc = 1 or vRegRdy = 0 (1) ovVolt = 0 and uvVolt = 0 and ovTemp = 0 (4) vBootRdy = 1 (1) OE = 1 (2) OE = 0 and time • 1 ms and de2_busy = 0 and EnableSleep = 0 ovVolt = 1 or uvVolt = 1 (4) OE = 1 Sleep ACK STDBY WFLAGS OE Time-out VREG_ACK (3) OE = 0 and time • 1 ms and de2_busy = 0 and EnableSleep = 1 VBOOT (1) (2) Sleep Time-out (5) OE = 0 and EnableSleep = 1 (1) OE = 0 and EnableSleep = 1 (1) (2) (1) (2) (3) (1) (2) (3) (1) (2) (3) (1) GoToACK ACK Time-out (5) time > 15 ms

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4.1.2 DE2 RECEIVE AND AUTO-BAUD SEQUENCE

FIGURE 4-2: DE2 Data Reception and Auto-Baud Rate Sequence (Part 1). DE2 Falling Edge Detected i = 0 Wait 8 Cycles Sample DE2 i = 9? Received ‘0000000000’ yes Test for Normal DE2 Byte (Send ACK/NACK) i = i + 1 Wait 16 Cycles no Clock is 16x the Baud Rate Sample Start Bit + 8 Data Bits + Stop Bit Common for Normal Command or Data Bytes and Break Detection

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 21 MCP8021/2 FIGURE 4-3: DE2 Data Reception and Auto-Baud Rate Sequence (Part 2). no yes yes yes yes no yes no no no Wait 16 Cycles Sample DE2 DE2 = 0? j = 0 Wait 1 Cycle j = j + 1 Sample DE2 DE2 = 0? j < 6? j > 184? Wait 166 Cycles Send 0x55 Byte Wait 332 Cycles GoTo DE2 Idle State Send NACK Auto-Baud Rate Sequence Sample at 10.5 Bits Total Minimal Break Duration: (10 + 14/16) Bit Break Time-out After: 22-Bit

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4.2 Bias Generator

The internal bias generator controls several voltage rails. Two fixed output Low Dropout linear regulators, internal bias supply LDOs and a charge pump are controlled through the bias generator. In addition, the bias generator performs supervisory functions.

4.2.1 CHARGE PUMP

An unregulated charge pump is utilized to boost the input to the V BOOT voltage regulator during low input supply voltage conditions. When the input bias to the device (V DD) drops below the CP START voltage, the charge pump is activated. When activated, 2 x V DD is presented to the input of the V BOOT regulator. The charge pump is capable of maintaining a VBOOT output of +9V @ 15 mA for a VDD supply voltage of 5.25V to 7V. The charge pump is capable of maintaining a V BOOT output of +12V @ 20 mA for a supply input voltage of 7V to 13.5V. The charge pump is disabled and bypassed at VDD voltages above 13.5V, allowing an output voltage of +12V @ 30 mA. The typical Charge Pump Flying Capacitor, C CP, is a 0.1 µF to 1.0 µF ceramic capacitor.

4.2.2 V BOOT VOLTAGE REGULATOR

The VBOOT voltage regulator rail is used to supply bias voltage for the integrated 3-phase power MOSFET bridge drivers. The regulator is capable of supplying 30 mA of external load current. The regulator has a minimum overcurrent limit of 40 mA. The regulator gets its power from the integrated charge pump. When operating at supply voltages (VDD) that are above +14V, the integrated charge pump will be disabled and the V DD supply will power the VBOOT voltage regulator. The VBOOT regulator out- put may be lower than the designed voltage, while operating in the VDD range of +12.5V to +13.0V, due to the dropout voltage of the regulator. The V BOOT regulator requires an output capacitor, connected from VBOOT to GND, to stabilize the internal control loop and to sustain the bootstrap capacitor energy. A minimum of 4.7 µF ceramic output capaci- tance is required for the V BOOT voltage regulator output; 10 µF is recommended when switching large MOSFET gate loads. The output capacitor forces a time delay between setting the OE pin high (to transi- tion from Standby mode to Active mode) and the V BOOT regulator voltage output rising above the volt- age required to set an internal VBootReady flag. The PWM inputs must not be activated while the V BOOT output is charging the output capacitors to the VBootReady voltage (typically 6.0V). The time required before allowing the PWM inputs to become active, after setting OE high to transition from Standby mode to Active mode, is dependent on output capaci- tance, any extra loads and supply voltage ramp-up time. The user should allow a minimum time of 0.94 ms for the V BOOT output voltage to rise above the VBootReady voltage. A voltage of 6V and supply cur- rent of 30 mA may be used for this delay estimation. See Equation 4-1. EQUATION 4-1: OE PIN HIGH TO V BOOT READY There is a time-out functi on that allows the state machine to move from V BOOT to active after 15 ms, regardless of the V BOOT ready voltage. This time-out function prevents the driver from hanging up if the VBOOT voltage is overloaded. There is also a capacitive voltage divider formed by the three bootstrap capacitors and the V BOOT capacitor. The VBOOT capacitor should be selected so that when the VBOOT supply is active and the bootstrap capacitors are charged, the voltage at the bootstrap capacitors will be greater than the driver undervoltage shutdown volt- age, 4.5V. For a system with V BOOT = 12V, VMIN = 4.5V and N = 3 x 1 µF C BOOTSTRAP capacitors charging at the same time, the desired CVBOOT capacitor is 1.8 µF (see Equation 4-2). Since the VBOOT supply requires a 4.7 µF capacitor, a 4.7 µF capacitor should be used. The initial voltage seen by the bootstrap capacitors using a 4.7 µF V BOOT capacitor will be 7.32V. See Equation 4-3. EQUATION 4-2: V BOOT CAPACITOR EQUATION 4-3: BOOTSTRAP VOLTAGE The V BOOT output is disabled when the driver transitions to Standby or Sleep mode. Table 4-4 shows the Faults that will also disable the VBOOT voltage regulator. dt = (C  dV)/(I) dt = (4.7 µF  6V)/(30 mA) dt = 0.94 ms (N  CBOOTSTRAP) (VBOOT)  (VMIN) – 1CVBOOT = VBOOTSTRAP = (VBOOT  CVBOOT) ((CVBOOT + N  CBOOTSTRAP)

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4.2.3 V REG LOW DROPOUT LINEAR

REGULATOR (LDO) The V REG LDO is used to bias an external micro- controller, the internal oper ational amplifiers and the gate control logic. The V REG LDO is capable of supplying 70 mA of external load current. The regulator has a minimum overcurrent limit of 80 mA. When the regulator current exceeds the overcurrent limit, the regulator will enter a True Current and Voltage Foldback mode based upon load impedance. As the load impedance decreases towards zero ohms, the regulator output current and voltage will also decrease until the final foldback current and voltage are attained. When the regulator output voltage drops below the V REG undervoltage limit, the VREGUVF undervoltage Fault bit will be set in the STAT1 register. The regulator will remain active during the Fault. Table 4-1 shows the registers and bits associated with Faults. The V REG LDO will be disabled when the V DD supply voltage undervoltage Fault occurs. The VREG LDO will be re-enabled when the conditions in Section 4.3.1 “Voltage Supervisor” are met. A minimum of 4.7 µF ceramic output capacitance is required for the V REG LDO; 10 µF is recommended to increase transient performance when a host microcontroller is attached. The VREG LDO is disabled while the system is in Sleep mode. In the case of Sleep mode, the V REG LDO output voltage is held down with a 1 kOhm pull-down resistor.

4.3 Supervisor

The bias generator incorporates a voltage supervisor and a temperature supervisor.

4.3.1 VOLTAGE SUPERVISOR

The voltage supervisor protects the device, external power MOSFETs and the external microcontroller from damage due to overvoltage or undervoltage of the input supply, V DD. In the event of an undervoltage condition, VDD <U V L OACT, or overvoltage condition, VDD >O V L OACT, or V REG LDO undervoltage condi- tion, VREG < VREGUVF ACT, the gate drivers, charge pump and VBOOT regulator are switched off. The bias generator, communication po rt, operational amplifiers and the remainder of the motor control unit remain active. The failure state is flagged on the FAULT pin and a DE2 status message is sent. In the event of a severe undervoltage condition, VDD < UVSHDNACT, the entire device will shut down except for the minimal circuitry required for a Power-on Reset recovery. A UVSHDN Fault will be set. The VREG output will be turned off and pulled low to create a “clean” shutdown of an attached host processor. The undervoltage shutdown condition is a latched state. The state machine will be restarted from the Power-on Reset state when either of the following two conditions are met: 1. V DD power is cycled. 2. V DD rises above UVLOINACT (6.0V).

4.3.2 TEMPERATURE SUPERVISOR

An integrated te mperature sensor monitors the die temperature. If the temper ature rises above the over- temperature shutdown thresh old, all device functions are turned off except for those required to send a DE2 Fault message. A Fault will be generated and a DE2 Fault message will be sent. The functions required to send the DE2 Fault message will then be shut down if pin OE is set to a low level. Active operation resumes when the temperature has cooled down below a set hysteresis value and the Fault has been cleared by toggling the OE pin from a logic low to a logic high. It is desirable to signal the microcontroller with a warn- ing message before the overtemperature threshold is reached. When the Thermal Warning Temperature WARN) set point is exceeded, a warning message will be sent to the host microcontroller. The warning message has no effect upon driver operation. The microcontroller may then take appropriate actions to reduce the temperature rise. The method to signal the microcontroller is through the DE2 pin.

4.4 Output Enable (OE)

The Output Enable (OE) pin allows the device outputs to be disabled by external control. The Output Enable pin has three modes of operation.

4.4.1 FAULT CLEARING STATE

The OE pin is used to clear any Faults and re-enable the driver. After toggling the OE pin low-to-high, the system requires a minimum time period to re-enable and start up all of the driver blocks. The start-up time is approximately 35 μs. The maximum pulse time for the high-low-high transition to clear the Faults should be less than 900 μs to prevent the system from transition- ing through Standby mode. If the high-low-high transition is longer than 1 ms, the device will start up from the Standby state. Any Fault status bits that are set will be cleared by the low-to-high transition of the OE pin, if and only if, the Fault condition has ceased to exist. If the Fault condi- tion still exists, the active Fault status bit will remain active. No additional Fault messages will be sent for a Fault that remains active.

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4.4.2 STANDBY STATE

Standby state is entered when the OE pin goes low for longer than 1 ms and the SLEEP Configuration bit is inactive. When Standby mode is entered, the following subsystems are disabled:

• High-side gate drives (HSA, HSB, HSC) forced low
• Low-side gate drives (LSA, LSB, LSC) forced low
• V BOOT LDO
• Charge pump
• Operational amplif iers if CFG0[6] = 1 (MCP8022) The VREG LDO, operational amplifiers (if CFG0[6] = 0) and DE2 communications stay active. The total current consumption of the device when OE is inactive (device disabled) stays within the “Standby mode input quiescent current” limits specified in the device characteristics table.

4.4.3 SLEEP MODE

Sleep mode is entered when both a SLEEP command is sent to the device via DE2 communications and the OE pin is low. The two conditions may occur in any order. The transition to Sleep mode occurs after the last of the two conditions occurs. The SLEEP bit in the CFG0 Configuration register indicates when the device should transition to a low-power mode. The device will operate normally until the OE pin is transi- tioned low by an external device. At that point in time, the SLEEP bit value determines whether the device transitions to Standby mode or low-power Sleep mode. The supply current (I SUP) during Sleep mode will typi- cally be 5 μA. When Sleep mode is activated, most functions will be shut off, including the V REG LDO. Only the Power-on Reset monitor and minimal state machine will remain active to detect a wake-up event. This indicates that the host processor will be shut down if the host is using the V REG LDO regulator for power. The device will stay in the low-power Sleep mode until either of the following conditions is met:

• The WAKE pin transitions high after being in a low state lasting longer than tWAIT_SETUP
• Power is cycled The MCP8021/2 devices are not required to retain configuration data while in Sleep mode. When exiting Sleep mode, the host should send a new configuration message to configure the device if the default configu- ration values are not desired. The same configuration sequence used during power-up may be used when exiting Sleep mode. When activated, Sleep mode will always be entered regardless of any active Fault. This allows a transition to Sleep mode when the host is powered by the V REG LDO and the regulator is in an unreliable state. The SLEEP bit in the Configuration register will be ignored at power-up until the system has enabled the V REG LDO and the VREG LDO has entered regulation.

4.5 Faults

4.5.1 FAULT PIN OUTPUT (FAULT )

The FAULT pin is used as a Fault indicator. The pin is capable of sinking a minimum of 1 mA of current while maintaining less than 50 mV of voltage across the output. An external pull-up resistor to the logic supply is required. The open-drain FAULT pin transitions low when a Fault occurs. Table 4-1 lists the Faults that activate the FAULT signal. Warnings do not activate the FAULT signal; Table 4-2 lists the warnings.

4.5.2 FAULT HANDLING SEQUENCE

When a Fault occurs, the following steps will occur in sequence. 1. The gate drive outputs will be immediately turned off. 2. The FAULT pin output will go low. 3. A message will be sent via the DE2 communications link. 4. The V REG LDO will be disabled immediately if the Fault is a V DD undervoltage shutdown (UVSHDNACT) Fault. 5. The V REG LDO will be disabled 5 ms after the DE2 message has been sent for an overtemperature shutdown (OTSHDN) Fault.

4.5.3 FAULT INDICATOR

A FAULT indicator bit resides in the STAT0 register. The bit is the logical ‘OR’ of all of the Fault bits in the two status registers. Warnings are not included in the FAULT indicator bit. The FAULT bit will allow the user to read the STAT0 register in order to determine if a Fault is present in the system. If the bit is set, th en the user may request the STAT1 message and interrogate the bits of both status messages to determine what Faults exist. The Faults that are logically OR’d together to generate the FAULT bit are as follows:

• STAT0:OTPF
• STAT0:UVLOF
• STAT0:OVLOF
• S T A T 1 : R E G U V F
• S T A T 1 : X U V L O F
• S T A T 1 : X O C P F

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4.5.4 POWER CONTROL STATUS (PCON)

The PCON[2:0] (STAT0[7:5]) bits are power control status bits that may be used to determine the cause of a shutdown. They are not Fault latches. The PCON power status bits will contain th e cause of the power cycle. Table 4-3 lists the power status register bits in the STAT0 register. TABLE 4-3: POWER STATUS

4.5.4.1 Internal Fu nction Block Status

Table 4-4 shows the effects of the OE pin, Faults and the SLEEP bit upon the functional status of the internal blocks of the MCP8021/2.

4.5.4.2 Start-Up/FAULT Pin State

During device start-up or Power-on Reset (POR), the FAULT pin will stay active (low) to indicate to the host that the device is in itializing. The FAULT pin will stay active until the state machine powers up the VREG LDO and completes the V REG state. After the VREG LDO is powered up, the FAULT pin logic checks the state of all of the latched FAULT bits. If any FAULT bit is still active, the FAULT pin will stay active and remain low. Fault DE2 Message Fault Active (‘OR’ of all Faults) 0x85 0x01 Overtemperature 0x85 0x04 VDD Input Undervoltage 0x85 0x08 VDD Input Overvoltage 0x85 0x10 VREG Output Undervoltage 0x86 0x01 External MOSFET Undervoltage Lockout 0x86 0x04 External MOSFET Overcurrent Detection 0x86 0x08 Fault DE2 Message Temperature Warning 0x85 0x02 PCON Status Bits [7:5] DE2 Message Overtemperature Shutdown (OTSHDN) Occurred 0x85 0xA0 Sleep Occurred 0x85 0x60 VDD Undervoltage Shutdown (UVSHDN) Occurred 0x85 0x40 Power-on Reset (POR) Occurred 0x85 0x20 Normal Operation 0x85 0x00

DS20006265D-page 26  2020-2024 Microchip Technology Inc. and its subsidiaries TABLE 4-4: INTERNAL FUNCTION BLOCK STATUS System State Fault Conditions Sleep Latch VREG LDO VBOOT LDO Motor Drivers DE2 Op Amps (MCP8022) Internal UVLO, OVLO, OTP Sleep OE = 0, SLEEP = 1 W————— — Standby OE = 0, SLEEP = 0 —A— —A C A Operating OE = 1, FAULT = 1 — AAAAA A Faults FAULT = 0 Driver OTPF T J Temperature > TSD ———— D — A VDDUVLO V DD  UVLOINACT —A— —A A A VDDUVSHDN V DD  UVSHDNINACT ———— E — — VDDOVLO V DD  OVLOINACT —A— —A A A VREG LDO UVF V REG  88% VREG —A— —A A A MOSFET UVLO V HS[A:C] < VDUVLO VLS[A:C] < VDUVLO —A A—A A A MOSFET OCPF V Drain Source > EXTOC[1:0] setting — A A — A A A Warnings FAULT = 1 Driver temperature T J Temperature > TWARN — AAAAA A Power Status Configuration lost if Power-on Reset, wake from Sleep or recover from V DD undervoltage shutdown occurred Set at initial power-up, when V DD < UVSHDNACT or when waking from Sleep — AAAAA A Legend: — = Inactive (Off); A = Active (On); C = Configurable ; D = Inactive (Off) 5 ms after sent Fault message; E = Inactive (Off); R = Receiver Only; W = Wake-up (from Sleep); OCPF = Overcurrent Protection; OTPF = Overtemperature Protection; UVLO = Undervoltage Lockout; OVLO = Overvoltage Lockout; UVF = Undervoltage Fault; UVSHDN = Undervoltage Shutdown

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 27 MCP8021/2

4.6 Motor Control Unit

The motor control unit is comprised of the following:

• External Drive for a 3-Phase Bridge with NMOS/NMOS MOSFET Pairs
• MOSFET Driver Undervoltage Lockout
• External MOSFET Short-Circuit Current
• F A U L T Pin Output
• Cross Conduction Protection
• Programmable Dead Time
• Programmable Blanking Time
• Three General Purpose Operational Amplifiers (MCP8022)

4.6.1 EXTERNAL DRIVE FOR A 3-PHASE

Each motor phase is driven with external NMOS/ NMOS MOSFET pairs. These are controlled by a low- side and a high-side gate driver. The gate drivers are controlled by the digital in put pins, PWM[A:C]H/L. A logic high turns the associated gate driver on and a logic low turns the associated gate driver off. The PWM[A:C]H/L digital inputs are equipped with internal pull-down resistors. The low-side gate drivers are biased by the V BOOT regulator output, referenced to ground. The high-side gate drivers are a floating drive biased by a bootstrap capacitor circuit. The bootstrap capacitor is charged by the V BOOT regulator whenever the accompanying low-side MOSFET is turned on. The high-side and low-side driver outputs all go to a low state whenever there is a Fault, when OE = 0 for more than 1 ms or when Sleep mode is active, regardless of the PWM[A:C]H/L inputs. The gate driver output stages have lower dynamic R DSONDYN in the time frame up to 1 ms after output activation. This is the relevant drain source on resis- tance for charging or discharging the external MOSFET gates. After elapsing 1 ms or later, the high-side gate driver, RDSON, increases slightly up to the static RDSON value.

4.6.2 MOSFET GATE DRIVE

UNDERVOLTAGE LOCKOUT (UVLO) The MOSFET gate drive undervoltage lockout Fault detection monitors the ava ilable voltage used to drive the external MOSFET gates. The Fault detection is only active while the driver is actively driving the external MOSFET gate. Any time the driver bias voltage is below the gate drive undervoltage lockout threshold (VDUVLO) for a time longer than specified by the tDUVLO parameter, the driver will not turn on when commanded on. A driver Fault will be indicated to the host microcontroller on the FAULT open-drain output pin and also via a DE2 com- munications Status_1 message. This is a latched Fault. Clearing the Fault requires either removal of device power or disablin g and re-enabling the device via the device Output Enable (OE) input. The EXTUVLO bit in the CFG0 register is used to enable or disable the driver undervoltage lockout feature. This protection feature prevents the external MOSFETs from being controlled with a gate voltage not suitable to fully enhance the device.

4.6.3 EXTERNAL MOSFET

Short-circuit protection monitors the voltage across the external MOSFETs during an on condition. The high- side driver voltage is measured from V DD to PH[A:C]. The low-side driver voltage is measured from PH[A:C] to ground. If a monitored voltage rises above a user- configurable threshold afte r the driver HS[A:C] or LS[A:C] output voltage has been driven high, all drivers will be turned off. A driver Fault will be indicated to the host microcontroller on the open-drain FAULT output pin and also via a DE2 communications Status_1 mes- sage. This is a latched Fault. Clearing the Fault requires either removal of device power or toggling the OE input pin low-to-high. This protection feature helps detect internal motor failures, such as winding to case shorts. The short-circuit voltage may be set via a DE2 Set_Cfg_0 message. The EXTOC[1 :0] bits of the CFG0 register are used to select the voltage level for the short-circuit comparison. If a monitored voltage dif- ferential between V DD and PH[A:C], or between PH[A:C] and PGND, exceeds the selected voltage level when the MOSFET gate drive is active, a Fault will be triggered. The selectable voltage levels are 250 mV, 500 mV, 750 mV and 1000 mV. The EXTSC bit of the CFG0 register is used to enable or disable the MOSFET driver short-circuit detection.

4.6.4 GATE CONTROL LOGIC

The gate control logic enables level shifting of the digital inputs, polarity control and cross conduction protection.

4.6.4.1 Cross Conduction Protection

If both MOSFETs in the same half-bridge are commanded on by the digital PWM inputs, both will be turned off. Note: The driver short-circuit protection is dependent on application parameters. A configuration message is provided for a set number of threshold levels. The MOSFET gate drive UVLO and short- circuit protection features have the option to be disabled.

DS20006265D-page 28  2020-2024 Microchip Technology Inc. and its subsidiaries

4.6.4.2 Programmable Dead Time

The gate control logic employs a break-before-make dead-time delay that is programmable. A configuration message is provided to configure the driver dead time. The programmable dead times range from 250 ns to 2000 ns (default) in 250 ns increments. The dead time allows the PWM inputs to be direct inversions of each other and still allow proper motor operation. The dead time internally modifies the PWMH/L gate drive timing to prevent cross conduction. The DRVDT[2:0] bits of the CFG2 register are used to set the dead-time value.

4.6.4.3 Programmable Blanking Time

A configuration message is provided to configure the driver current limit blanking time. The blanking time allows the driver to ignore any current spikes that may occur when switching the driver outputs. The allowable blanking times are 500 ns, 1 µs, 2 µs and 4 µs (default). The blanking time will start after the dead-time circuitry has timed out. The DRVBL[1:0] bits of the CFG2 register are used to set the blanking time value. The blanking time also affects the driver undervoltage lockout. The driver undervoltage lockout latches the external MOSFET undervoltage lockout Fault if the undervoltage condition lasts longer than the time spec- ified by the t DUVLO parameter. The t DUVLO parameter takes into account the blanking time if blanking is in progress.

4.6.5 OPERATIONAL AMPLIFIERS

(MCP8022) Three operational amplifie rs are present in the MCP8022 device. The operational amplifiers are available for general purpose use by the external system circuitry. The operational amplifiers are enabled whenever the device is powered and not in Sleep mode. The user may also select the state of the operational amplifiers for Standby mode. When the OE input is set low long enough for the system to enter Standby mode, the operational amplifiers may be enabled or disabled, depending on the value of the CFG0[6] Configuration bit. When the CFG0[6] bit is ‘0’, the operational amplifiers will be enabled during Standby mode. When the CFG0[6] bit is ‘ 1’, the operational amplifiers will be disabled during Standby mode. This allows the system to reduce power consumptio n without transitioning to Sleep mode. The V REG regulator provides the bias supply for the operational amplifiers. The amplifiers are capable of operating when the V REG regulator output voltage drops due to the supply voltage (V DD) dropping. The corresponding amplifier output voltage limits will be reduced accordingly. The output voltage range is capable of providing 200 µA of current from 0.150V to

4.7 Motor Control

The commutation loop of a BLDC motor control is a Phase-Locked Loop (PLL), which locks to the rotor’s position. Note that this inner loop does not attempt to modify the position of the rotor, but modifies the com- mutation times to match what ever position the rotor has. An outer speed loop changes the rotor velocity and the commutation loop locks to the rotor’s position to commutate the phases at the correct times.

4.7.1 SIX-STEP SENSORLESS MOTOR

Many control algorithms ca n be implemented with the MCP8021/2 in conjunction with a microcontroller. The following discussion provides a starting point for imple- menting the MCP8021 or MCP8022 in a sensorless control application of a 3-phase motor. The motor is driven by energizing two windings at a time and sequencing the windings in a six-step per electrical revolution method. This method leaves one winding unenergized at all times. The voltage (Back EMF or BEMF) on that unenergized winding can be monitored to determine the rotor position.

4.7.1.1 Start-Up Sequence

When the motor being driven is at rest, the BEMF volt- age is equal to zero. The motor needs to be rotating for the BEMF sensor to lock onto the rotor position and commutate the motor. The recommended start-up sequence is to bring the rotor from rest, up to a speed fast enough to allow BEMF sensing. Motor operation is comprised of five modes: Disabled mode, Bootstrap mode, Lock or Align mode, Ramp mode and Run mode. Refer to the commutation state machine in Table 4-5. The order in which the microcontroller steps through the commutation state machine determines the direction that the motor rotates.

4.7.1.2 Disabled Mode (OE = 0)

When the driver output is disabled (OE = 0), all of the MOSFET driver outputs are set low.

4.7.1.3 Bootstrap Mode

The high-side driver obtains the high-side biasing voltage from the V BOOT LDO, bootstrap diode and bootstrap capacitor. The bo otstrap capacitors must first be charged before the high-side drives may be used. The bootstrap capacitors are all charged by acti- vating all three low-side drivers. The active low-side drivers pull their respective phase nodes low, charging the bootstrap capacitors to the V BOOT LDO voltage. The three low-side drivers should be active for at least 1.2 ms per 1 µF of boot strap capacitance. This assumes a 12V voltage change and 30 mA (10 mA per phase) of current coming from the V BOOT LDO.

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 29 MCP8021/2

4.7.1.4 Lock Mode

Before the motor can be started, the rotor should be in a known position. In Lock mode, the microcontroller drives Phase B low and Phases A and C high. This aligns the rotor 30 electrical degrees before the center of the first commutation state. Lock mode must last long enough to allow the motor and its load to settle into this position.

4.7.1.5 Ramp Mode

At the end of Lock mode, Ramp mode is entered. In Ramp mode, the microcontro ller steps through the commutation state machine, increasing the step rate linearly, until a minimum speed is reached that will result in a usable BEMF voltage. Ramp mode is an open-loop commutation. No knowledge of the rotor position is used.

4.7.1.6 Run Mode

At the end of Ramp mode, Run mode is entered. In Run mode, the Back EMF sensor is enabled and commuta- tion is now under the control of the Phase-Locked Loop. Motor speed can be regulated by an outer speed control loop.

4.7.1.7 PWM Speed Control

The inner commutation loop is a Phase-Locked Loop, which locks to the rotor’s position. This inner loop does not attempt to modify the position of the rotor, but modifies the commutation times to match whatever position the rotor has. The outer speed loop changes the rotor velocity and the inner commutation loop locks to the rotor’s position to commutate the phase at the correct times. The outer speed loop pulse width modulates the motor drive inverter to produce the desired wave shape and voltage at the motor. The inductance of the motor then integrates this PWM pattern to produce the desired average current, thus controlling the desired torque and speed of the motor. For a trapezoidal BLDC motor drive with six-step com- mutation, the PWM is used to generate the average voltage to produce the desired motor current and motor speed. There are two basic methods to PWM the inverter switches. The first method returns the reactive energy in the motor inductance to the source by reversing the voltage on the motor winding during the current decay period. This method is referred to as fast decay or chop-chop. The second method circulates the reactive current in the motor with minimal voltage applied to the inductance. This method is referred to as slow decay or chop-coast. The preferred control method employs a chop-chop PWM for any situations where the motor is being accelerated, either positively or negatively. For improved efficiency, chop-coast PWM is employed during steady-state conditio ns. The chop-chop speed loop is implemented by hysteretic control, fixed off- time control or Average Current mode control of the motor current. This makes for a very robust controller, since the motor current is always in instantaneous control. The motor speed presented to the chop-chop loop is reduced by approximately 9%. A fixed frequency PWM that only modulates the high-side switches implements the chop-coast loop. The chop- coast loop is presented with the full motor speed, so if it is able to control the speed, the chop-chop loop will never be satisfied and will remain saturated. The chop-chop remains able to assume full control if the motor torque is exceeded, either through a load change or a change in speed that produces accelera- tion torque. The chop-coast loop will remain saturated, with the chop-chop loop in fu ll control, during start-up and acceleration to full speed. The bandwidth of the chop-coast loop is set to be slower than the chop-chop loop so that any transients will be handled by the chop-chop loop and the chop-coast loop will only be active in steady-state operation. TABLE 4-5: COMMUTATION STATE MACHINE State Outputs BEMF Phase HSA HSB HSC LSA LSB LSC OE = 0 OFF OFF OFF OFF OFF OFF N/A BOOTSTRAP OFF OFF OFF ON ON ON N/A LOCK ON OFF ON OFF ON OFF N/A

1 ON OFF OFF OFF OFF ON Phase B

2 OFF ON OFF OFF OFF ON Phase A

3 OFF ON OFF ON OFF OFF Phase C

4 OFF OFF ON ON OFF OFF Phase B

5 OFF OFF ON OFF ON OFF Phase A

6 ON OFF OFF OFF ON OFF Phase C

DS20006265D-page 30  2020-2024 Microchip Technology Inc. and its subsidiaries

4.8 DE2 Communication Port

A half-duplex 9600 baud UART interface is available to communicate with an external host. The port is used to configure the MCP8021/2 and also for status and Fault messages.

4.8.1 COMMUNICATIONS INTERFACE

A single wire, half-duplex, 9600 baud, 8-bit bidirectional communications interface is implemented using the open-drain DE2 pin. The interface consists of eight data bits, one Stop bit and one Start bit. The implementation of the interface is described in the following sections. The DE2 interface is an open-drain interface. The open-drain output is capabl e of sinking a minimum of 1 mA of current while maintaining less than 50 mV at the output. A 5K resistor should typically be used between the host transmit pin and the MCP8021/2 DE2 pin to allow the MCP8021/2 to drive the DE2 line low when the host TX pin is at an active-high level. The auto-baud frequency is temperature-dependent, as illustrated in Figure 2-5. To establish proper DE2 communication, it is recommended to synchronize the host frequency by proceeding the auto-baud function alternatively, as described in Section 4.8.5 “Auto- Baud Function”. The time from receiving the last bit of a command message to sending the first bit of the response message ranges from t DE2_RSP to tDE2_WAIT, corresponding to 0 µs to 3.125 ms. The host should refrain from sending additional messages until the previously requested message has been received in order to prevent overwrit ing the driver response message.

4.8.2 PACKET FORMAT

Every internal driver status change will cause the driver to send a message to the microcontroller. The interface uses a standard UART baud rate of 9600 bits per second. In the DE2 protocol, the transmitter and the receiver do not share a clock signal. A clock signal does not emanate from one transmitter to the other receiver. Due to this reason, the prot ocol is asynchronous. The protocol uses only one line to communicate, so the transmit/receive packet must be done in Half-Duplex mode. A new transmit message is allowed only when a complete packet has been transmitted and responded to. The host must listen to the DE2 line in order to check for contentions. In case of contention, the host must release the line and wait for at least three packet length times before initiating a new transfer. Figure 4-4 illustrates a basic DE2 data packet.

4.8.3 PACKET TIMING

While no data are being transmitted, a logic ‘ 1’ must be placed on the open-drain DE2 line by an external pull-up resistor. A data packet is composed of one Start bit, which is always a logic ‘0’, followed by eight data bits and a Stop bit. The Stop bit must always be a logic ‘1’. It takes ten bits to transmit a byte of data. The device detects the Start bit by detecting the transi- tion from logic ‘1’ to logic ‘0’ (note that while the data line is Idle, the logic level is high). Once the Start bit is detected, the next data bit’s “center” can be assured to be 24 ticks minus 2 (worst -case synchronizer uncer- tainty) later. From then on, every next data bit center is 16 clock ticks later. Figure 4-5 illustrates this point.

4.8.4 MESSAGE HANDLING

The driver will not transition to Sleep mode while a message is being received. If a message reception is in progress before the OE = 0 to Sleep mode transition delay (t SLEEP) times out, the message will be fully received and the contents applied to the Configuration registers if applicable. The SLEEP bit will then be checked and the system enters Sleep mode if the SLEEP bit is still active.

4.8.5 AUTO-BAUD FUNCTION

The MCP8021/2 devices provide an auto-baud feature that allows a host, communicating on the DE2 communications link, to determine the actual baud rate being used by the MCP8021/2 device. The feature allows the host to request a 0x55 byte transmission from the MCP8021/2. The host then determines the MCP8021/2 baud rate and adjusts the host internal Baud Rate Generator (BRG) to match the MCP8021/2 baud rate. The DE2 pin is used to tr igger the auto- baud feature. The host sets the DE2 signal to a logic low for a period of time (auto-baud Break window) that ranges between 1.29 ms and 2.0 ms. The host then releases the DE2 pin back to the host UART control. The host UART then raises the DE2 pin to a logic high value. The MCP8021/2 driver will respond with a standard NACK (‘0b00nnnnnn’, where ‘nnnnnn’ are the six Least Significant bits (LSbs) received) if the DE2 link was held low for less than 1.29 ms and the byte was not interpreted as a valid command. The MCP8021/2 driver will ignore the current message if the DE2 link is held low for more than 2.0 ms. If the driver receives a valid auto-baud request in the allotted time frame, the driver will enter an Auto-Baud state, indicating an auto-baud message has been requested. When the auto-baud function is activated, the DE2 subsystem will disable sending all unsolicited messages to the host.

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 31 MCP8021/2 If the internal Auto-Baud state is set, the driver will wait for a minimum of 0.86 ms and a maximum of 1.19 ms. After the wait time has expired, a 0x55 data byte will be immediately sent on the DE2 link by the driver. The driver will wait 2.00 ms after sending the 0x55 baud rate data over the DE2 link before transmitting any other messages. The driver will then exit the Auto- Baud state and resume normal DE2 operations. The 2.00 ms wait is needed to allow the host to complete the auto-baud verification and update the host UART Baud Rate Generator. The MCP8021/2 device will always monitor the DE2 link for a logic low before attempting to transmit. The MCP8021/2 device will preempt all DE2 communications upon receiving a logic low on the DE2 link which lasts longer than ten bit times at 9600 baud (Break sequence). The MCP8021/2 device will wait for a period up to 2 ms for the DE2 link to change to a logic high state after the initial detection of a logic low on the DE2 link. If the DE2 link fails to rise to a logic high level within 2 ms of the initial logic low level, the auto-baud message will be canceled and no message will be sent. The auto-baud function will then be complete. The driver will send any pending unsolicited messages after the auto-baud function has finished.

4.8.6 MESSAGING INTERFACE

A command byte will always have the Most Significant bit (MSb) 7 set to ‘ 1’. Bits 6 and 5 are reserved for future use and should be set to ‘0’. Bits[4:0] are used for commands. That allows for 32 possible commands.

4.8.6.1 Host to MCP8021/2

Messages sent from the host to the MCP8021/2 devices consist of either one or two 8-bit bytes. The first byte transmitted is the command byte. The second byte transmitted, if required, is the data for the command. If a multibyte command is sent to the MCP8021/2 devices and no second byte is received by the MCP8021/2 devices, then a “Command Not Acknowl- edged” message will be sent back to the host after. The host must start sending the 2nd byte of a two-byte command within 1 ms of completion of the first byte to prevent a NACK message. Once the second byte Start bit is received, the MCP8021/2 internal receiver logic will handle the reception of the data byte. If the data byte Stop bit is not received within the expected recep- tion time for the last received bit, the MCP8021/2 will respond with a NACK message.

4.8.6.2 MCP8021/2 to Host

A solicited response byte from the MCP8021/2 devices will always echo the command byte with bit 7 set to ‘ 0’ (response) and with bit 6 set to ‘ 1’ for Acknowledged (ACK) or ‘ 0’ for Not Acknowledged (NACK). The second byte, if required, will be the data for the host command. Any command that causes an error or is not supported will receive a NACK response. The MCP8021/2 may send unsolicited command messages to the host controller. All messages to the host controller do not require a response from the host controller.

4.8.7 MESSAGES

4.8.7.1 SET_CFG_0

There is a SET_CFG_0 message that is sent by the host to the MCP8021/2 devices to configure the devices. The SET_CFG_0 message may be sent to the devices at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_0 message. The SET_CFG_0 message format is indicated in Table 4-6. The response is indicated in Table 4-7.

4.8.7.2 GET_CFG_0

There is a GET_CFG_0 message that is sent by the host to the MCP8021/2 devices to retrieve the device Configuration register. The GET_CFG_0 message format is indicated in Table 4-6. The response is indicated in Table 4-7.

4.8.7.3 STATUS_0 and STATUS_1

There is a STATUS_0 and STATUS_1 message that is sent by the host to the MC P8021/2 devices to retrieve the device STAT0 and STAT1 registers. Unsolicited STATUS_0 and STATUS_1 messages may also be sent to the host by the MCP8021/2 devices to inform the host of status changes. The unsolicited STATUS_0 and STATUS_1 messages will only be sent when a status bit changes to an active state. The STATUS_0 and STATUS_1 message format is indicated in Table 4-6. The response is indicated in Table 4-7. When a STATUS_0 or STATUS_1 message is sent to the host in response to a new Fault becoming active, the FAULT bit will be cleared, either by the host issuing a STATUS_0 or STATUS_1 request message, or by the host toggling the OE pin low then high. The FAULT bit will stay active and not be cleared if the Fault condi- tion still exists at the time the host attempted to clear the Fault.

DS20006265D-page 32  2020-2024 Microchip Technology Inc. and its subsidiaries The PCON bits of the STAT0 register will be set every time the device restarts due to various events (see Table 4-3). When the driver resumes operation, a single unsolicited STATUS_0 message will be sent to the host indicating a Reset has occurred. The message will be sent five milliseconds (5 ms) after the V REG LDO has reached its active state. The host should check the PCON bits to determine the cause of the power cycle. In all cases, the configuration data may have been lost and should be re-sent to the driver. The PCON flags are reset by a host STATUS_0 request message. If the host misses the unsolicited STATUS_0 message at start-up, the host may manually request the status by sending a STATUS_0 message to the driver. The PCON bits of the STAT0 register will contain the source of the Power-on Reset until the STAT0 register is requested by the host.

4.8.7.4 SET_CFG_2

There is a SET_CFG_2 message that is sent by the host to the MCP8021/2 devices to configure the driver current limit blanking time. The SET_CFG_2 message may be sent to the devices at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_2 message. The SET_CFG_2 message format is indicated in Table 4-6. The response is indicated in Table 4-7.

4.8.7.5 GET_CFG_2

There is a GET_CFG_2 message that is sent by the host to the MCP8021/2 devices to retrieve the device Configuration Register #2. The GET_CFG_2 message format is indicated in Table 4-6. The response is indicated in Table 4-7. FIGURE 4-4: DE2 Packet Format. FIGURE 4-5: DE2 Packet Timing. STOPSTARTDE2 Message Format B0 B1 B2 B3 B4 B5 B6 B7 T = 1/Baud Rate (bit cell period)Detect Start Bit by Sensing Transition from Logic ‘1’ to Logic ‘0’ TS = T/16 (oversampled bit cell period) Receiver Samples the Incoming Data Using x16 Baud Rate Clock T START = 1.5T – Uncertainty on Start Detection (worst-case: 2x TS) Sample Incoming Data at the Bit Cell Center START TSTART TS STOPB0 B1 B4B3B2 B5 B6 B7

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 33 MCP8021/2 TABLE 4-6: DE2 COMMUNICATION COMMANDS FROM HOST TO MCP8021/2 Command Byte Bit Value Description SET_CFG_0 1 10000001 (81h) Set Configuration Register 0 27 0 Reserved 6 0 Reserved (MCP8021)

0 Enable operational amplifiers in Standby mode (default) (MCP8022)

1 Disable operational amplifiers in Standby mode (MCP8022)

5 0 System enters Standby mode when OE = 0, SLEEP = 0 for more than 1 ms

1 System enters Sleep mode when OE = 0, SLEEP = 1 for more than

3 0 Enable external MOSFET undervoltage lockout (default)

1 Disable external MOSFET undervoltage lockout

2 0 Enable external MOSFET short-circuit detection (default)

1 Disable external MOSFET short-circuit detection

1:0 00 Set external MOSFET overcurrent limit to 0.250V (default) 01 Set external MOSFET overcurrent limit to 0.500V 10 Set external MOSFET overcurrent limit to 0.750V 11 Set external MOSFET overcurrent limit to 1.000V GET_CFG_0 1 10000010 (82h) Get Configuration Register 0 STATUS_0 1 10000101 (85h) Get Status Register 0 STATUS_1 1 10000110 (86h) Get Status Register 1 SET_CFG_2 1 10000111 (87h) Set Configuration Register 2 2 7:5 00h Reserved 4:2 — Driver dead time (for PWMH /PWML inputs) 000 2000 ns (default) 001 1750 ns 010 1500 ns 011 1250 ns 100 1000 ns 101 750 ns 110 500 ns 111 250 ns 1:0 — Driver blanking time (ignore switching current spikes) 00 4 µs (default) 01 2µ s 10 1µ s 11 500 ns GET_CFG_2 1 10001000 (88h) Get Configuration Register 2 GET_REV_ID 1 10010000 (90h) Get device hardware revision

DS20006265D-page 34  2020-2024 Microchip Technology Inc. and its subsidiaries TABLE 4-7: DE2 COMMUNICATION M ESSAGES FROM MCP8021/2 TO HOST MESSAGE BYTE BIT VALUE DESCRIPTION SET_CFG_0 17 : 0 00000001 (01h) Command not Acknowledged (response) 01000001 (41h) Command Acknowledged (response) 27 0 Reserved 6 0 Reserved (MCP8021)

0 Operational amplifiers enabled in Standby mode (default) (MCP8022)

1 Operational amplifiers disabled in Standby mode (MCP8022)

5 0 System enters Standby mode when OE = 0, SLEEP = 0 for more than 1m s 3 0 External MOSFET undervoltage lockout enabled (default)

1 External MOSFET undervoltage lockout disabled

2 0 External MOSFET short-circuit detection enabled (default)

1 External MOSFET short-circuit detection disabled

1:0 00 0.250V external MOSFET overcurrent limit (default) 01 0.500V external MOSFET overcurrent limit 10 0.750V external MOSFET overcurrent limit 11 1.000V external MOSFET overcurrent limit GET_CFG_0 17 : 0 00000010 (02h) Command not Acknowledged (response) 01000010 (42h) Command Acknowledged (response) 27 0 Reserved 6 0 Reserved (MCP8021)

0 Operational amplifiers enabled in Standby mode (MCP8022)

5 0 System enters Standby mode when OE = 0, SLEEP = 0 for more than 1m s 3 0 External MOSFET undervoltage lockout enabled 2 0 External MOSFET short-circuit detection enabled 1:0 00 0.250V external MOSFET overcurrent limit 01 0.500V external MOSFET overcurrent limit 10 0.750V external MOSFET overcurrent limit 11 1.000V external MOSFET overcurrent limit

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 35 MCP8021/2 STATUS_0 17 : 0 00000101 (05h) Command not Acknowledged (response) 01000101 (45h) Command Acknowledged (response) 10000101 (85h) Command sent to host (unsolicited) 27 : 5 101 Overtemperature Shutdown (OTSHDN) occurred

011 Sleep Shutdown (SLEEP) occurred

010 Undervoltage Shutdown (UVSHDN) occurred

001 Power-on Reset (POR) occurred

000 Normal operation

4 1 Input Overvoltage (OVLOF), VDD > 32V 3 1 Input Undervoltage (UVLOF), VDD < 5.5V 2 1 Overtemperature (OTPF), TJ > TSD 1 1 Overtemperature Warning (OTPW), TJ > TWARN 0 0 No Fault condition exists

1 A Fault condition exists

STATUS_1 17 : 0 00000110 (06h) Command not Acknowledged (response) 01000110 (46h) Command Acknowledged (response) 10000110 (86h) Command sent to host (unsolicited) 27 : 4 0 Reserved 3 1 External MOSFET Overcurrent (XOCPF) detected 2 1 External MOSFET Undervoltage Lockout (XUVLOF) 1 0 Reserved 0 1 VREG LDO Undervoltage Fault (VREGUVF) SET_CFG_2 17 : 0 00000111 (07h) Command not Acknowledged (response) 01000111 (47h) Command Acknowledged (response) 2 7:5 00h Reserved 4:2 — Driver dead time (f or PWMH /PWML inputs) 000 2000 ns (default) 001 1750 ns 010 1500 ns 011 1250 ns 100 1000 ns 101 750 ns 110 500 ns 111 250 ns 1:0 — Driver blanking time (ignore Faults) 00 4000 ns (default) 01 2000 ns 10 1000 ns 11 500 ns TABLE 4-7: DE2 COMMUNICATION MESSAGES FR OM MCP8021/2 TO HOST (CONTINUED) MESSAGE BYTE BIT VALUE DESCRIPTION

DS20006265D-page 36  2020-2024 Microchip Technology Inc. and its subsidiaries GET_CFG_2 17 : 0 00001000 (08h) Command not Acknowledged (response) 01001000 (48h) Command Acknowledged (response) 2 7:5 00h Reserved 4:2 — Driver dead time (f or PWMH /PWML inputs) 000 2000 ns 001 1750 ns 010 1500 ns 011 1250 ns 100 1000 ns 101 750 ns 110 500 ns 111 250 ns 1:0 — Driver blanking time (ignore Faults) 00 4000 ns 01 2000 ns 10 1000 ns 11 500 ns GET_REV_ID 17 : 0 00010000 (10h) Command not Acknowledged (response) 01010000 (50h) Command Acknowledged (response) 2 7:4 00h Reserved 3:0 00h-0Fh Device hardware revision TABLE 4-7: DE2 COMMUNICATION MESSAGES FR OM MCP8021/2 TO HOST (CONTINUED) MESSAGE BYTE BIT VALUE DESCRIPTION

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 37 MCP8021/2

4.9 Register Definitions

REGISTER 4-1: CFG0: CONFIGURATION REGISTER 0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 —O P A M P (1) SLEEP — EXTUVLO EXTSC EXTOC1 EXTOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 OPAMP: Internal Operational Amplifier Power-Down (MCP8022)(1) 1 = Disables operational amplifiers during Standby mode 0 = Enables operational amplifiers during Standby mode bit 5 SLEEP: Sleep Mode Bit may only be changed while in Standby mode. 1 = System enters Sleep mode when OE = 0 0 = System enters Standby mode when OE = 0 bit 4 Unimplemented: Read as ‘0’ bit 3 EXTUVLO: External MOSFET Undervoltage Lockout 1 = Disable 0 = Enable bit 2 EXTSC: External MOSFET Short-Circuit Detection 1 = Disables 0 = Enables bit 1-0 EXTOC[1:0]: External MOSFET Overcurrent Threshold 00 = Overcurrent Threshold limit set to 0.250V 01 = Overcurrent Threshold limit set to 0.500V 10 = Overcurrent Threshold limit set to 0.750V 11 = Overcurrent Threshold limit set to 1.000V Note 1: The OPAMP bit has no effect on MCP8021.

DS20006265D-page 38  2020-2024 Microchip Technology Inc. and its subsidiaries REGISTER 4-2: CFG2: CONFIGURATION REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DRVDT2 DRVDT1 DRVDT0 DRVBL1 DRVBL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 DRVDT[2:0]: Driver Dead-Time Selection 000 = 2000 ns (default) 001 = 1750 ns 010 = 1500 ns 011 = 1250 ns 100 = 1000 ns 101 = 750 ns 110 = 500 ns 111 = 250 ns bit 1-0 DRVBL[1:0]: Driver Blanking Time Selection Bit may only be changed while in Standby mode. 00 = 4000 ns (default) 01 = 2000 ns 10 = 1000 ns 111 = 500 ns

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 39 MCP8021/2 REGISTER 4-3: STAT0: STATUS REGISTER 0 R-0 R-0 R-1 R-0 R-0 R-0 R-0 R-0 PCON2 PCON1 PCON0 OVLOF UVLOF OTPF OTPW FAULT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 PCON[2:0]: Power Control Status (configuration lost if non-zero value) 101 = Overtemperature Shutdown (OTSHDN) occurred 011 = Sleep (SLEEP) shutdown occurred 010 = Undervoltage Shutdown (UVSHDN) occurred 001 = Power-on Reset (POR) occurred 000 = Normal operation bit 4 OVLOF: Input Overvoltage Lockout Fault 1 = VDD input voltage > 32V 0 = VDD input voltage < 32V bit 3 UVLOF: Input Undervoltage Fault 1 = VDD input voltage < 5.5V 0 = VDD input voltage > 5.5V bit 2 OTPF: Overtemperature Protection Fault 1 = Device junction temperature is > TSD 0 = Device junction temperature is < TSD bit 1 OTPW: Overtemperature Protection Warning 1 = Device junction temperature is > TWARN 0 = Device junction temperature is < TWARN bit 0 FAULT: Fault Status 1 = At least one Fault is active 0 = No active Faults

DS20006265D-page 40  2020-2024 Microchip Technology Inc. and its subsidiaries REGISTER 4-4: STAT1: STATUS REGISTER 1 U-0 U-0 U-0 U-0 R-0 R-0 U-0 R-0 — — — — XOCPF XUVLOF —V R E G U V F bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 XOCPF: External MOSFET Overcurrent Protection Fault Only Valid when EXTSC (CFG0[2]) = 0. 1 = External MOSFET VDS > EXTOC[1:0] (CFG0[1:0]) value 0 = External MOSFET VDS < EXTOC[1:0] (CFG0[1:0]) value bit 2 XUVLOF: External MOSFET Gate Drive Undervoltage Fault Only Valid when EXTUVLO (CFG0[3]) = 0. 1 = HSx output voltage < VDUVLO 0 = HSx output voltage > VDUVLO bit 1 Unimplemented: Read as ‘0’ bit 0 VREGUVF: VREG LDO Undervoltage Fault 1 = VREG LDO output voltage < 88% of target VREG 0 = VREG LDO output voltage > 92% of target VREG REGISTER 4-5: REV_ID: HARDWARE REVISION ID — — — — REVID3 REVID2 REVID1 REVID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 REVID[3:0]: Device Revision 0111 = Device Revision D1 1000 = Device Revision D2

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 41 MCP8021/2

5.0 APPLICATION INFORMATION

5.1 Component Calculations

5.1.1 CHARGE PUMP CAPACITORS

FIGURE 5-1: Charge Pump. Let:

• I OUT = 20 mA
• f CP = 75 kHz (charge/discharge in one cycle)
• 50% duty cycle DDH = 5.5V (worst case)
• R DSON = 7.5 (RPMOS), 3.5 (RNMOS)
• V12P = 2  VDDH (ideal)
• C ESR = 20 m (ceramic capacitors)
• V DROP = 100 mV (VOUT ripple)
• T CHG= TDCHG = 0.5  1/75 kHz = 6.67 µs

5.1.1.1 Flying Capacitor

The flying capacitor should be chosen to charge to a minimum of 95% (3 ) of V DDH within one half of a switching cycle.

• 3  = TCHG
•  = TCHG/3
• RC = T CHG/3
• C = TCHG/(R  3)
• C = 158 nF Choose a 180 nF capacitor.

5.1.1.2 Charge Pump Output Capacitor

Solve for the charge pu mp output capacitance, connected between V12P and ground, that will supply the 20 mA load for one switch cycle. The VBOOT pin on the MCP8021/2 is the “V12P” pin referenced in the calculations.

• C = IOUT  dt/dV
• C = IOUT  13.3 µs/(VDROP + IOUT  CESR)
• C = 2 0 m A  13.3 µs/(0.1V + 20 mA  20 m)
• C  2.65 µF For stability reasons, the V BOOT LDO and V REG LDO capacitors must be at least 4.7 µF, so choose: C  4.7 µF.

5.1.1.3 Charging Path (Flying Capacitor

Across CAP1 and CAP2)

• V CAP = VDDH (1 – e-T/) VCAP = 5.31V available for transfer on the first cycle.

5.1.1.4 Transfer Path (Flying and Output

Capacitors)

• V12P = V DDH + VCAP – IOUT  dt/C
• V12P = 5.5V + 5.31V – (20 mA  6.67 µs/180 nF)
• V12P = 10.066V

5.1.1.5 Calculate the Flying Capacitor

Voltage Drop in One Cycle While Supplying 20 mA

• d V = IOUT  dt/C
• d V = 2 0 m A  6.67 µs/180 nF
• dV = 0.741V @ 20 mA The second and subsequent transfer cycles will have a higher voltage available for transfer, since the capacitor is not complete ly depleted with each cycle. V CAP will then be V CAP – dV after the first transfer, plus VDDH – (VCAP – dV) times the RC constant. This repeats for each subsequent cycle, allowing a larger charge pump capacitor to be used if the system will tolerate several charge transfers before requiring full output voltage and current. Repeating Section 5.1.1.3 “Charging Path (Flying Capacitor Across CAP1 and CAP2)” for the second cycle (and subsequent by re calculating for each new value of V CAP after each transfer):
• V CAP = (VCAP – dV) + (VDDH – (VCAP – dV)) (1 – e-T/t)
• V CAP = 4.567V + 0.934V  0.96535 VCAP = 5.468V available for transfer on second cycle.

5.1.1.6 Charge Pump Results

The maximum charge pump flying capacitor value is 202 nF to maintain a 95% voltage transfer ratio on the first charge pump cycle. Larger capacitor values may be used, but they will require more cycles to charge to maximum voltage. The minimum required output capacitor value is 2.65 µF to supply 20 mA for 13.3 µs with a 100 mV drop. A lar ger output capacitor may be used to cover losses due to capacitor tolerance over temperature, capacitor dielectric and PCB losses. These are approximate calculations. The actual voltages may vary due to incomplete charging or dis- charging of capacitors per cycle due to load changes. The charge pump calculations assume the charge pump is able to charge up the external boot cap within a few cycles. Transfer Charge VDDH VDDH

DS20006265D-page 42  2020-2024 Microchip Technology Inc. and its subsidiaries

5.1.2 BOOTSTRAP CAPACITOR

The high-side driver bootstrap capacitor needs to power the high-side driver and gate for 1/3 of the motor electrical period for a 3-phase BLDC motor operating in Six-Step mode. Let: Solve for the smallest capacitance that can supply:

• 130 nC of charge to the MOSFET gate
• 1 Megohm gate source resistor current
• Driver bias current and switching losses Sum all of the energy requirements:
• C = ( Q MOSFET + QRESISTOR + QDRIVER)/VDROP
• C = (130 nC + 0.594 nC + 0.99 nC)/3V
• C = 43.86 nF Choose a bootstrap capacitor value that is larger than 43.86 nF.

5.2 Device Protection

5.2.1 MOSFET VOLTAGE SUPPRESSION

When a motor shaft is rotating and power is removed, the magnetism of the motor components will cause the motor to act like a generator. The current that was flowing into the motor will now flow out of the motor. As the motor magnetic field de cays, the generator output will also decay. The voltage across the generator terminals will be proportional to the generator current and circuit impedance of the generator circuit. If the power supply is part of the return path for the current and the power supply is di sconnected, then the volt- age at the generator termi nals will increase until the current flows. This voltage increase must be handled externally to the driver. A voltage suppression device may be used to clamp the motor terminal voltage to a level that will not exceed the maximum system operat- ing voltage during the high-voltage transients. A voltage suppressor circuit may be connected from power ground to the motor power supply rail to create a path for the motor current when the supply is discon- nected (Figure 5-2). The PCB traces must be capable of carrying the motor curr ent with minimum voltage and temperature rise. FIGURE 5-2: Transient Voltage Clamp. An additional method is to inactivate the high-side drivers and to activate the low-side drivers. This allows current to flow through the low-side external MOSFETs and prevents the voltage from increasing at the power supply terminals. MOSFET Driver Current = 300 mA PWM Period = 50 µs (20 kHz) Minimum Duty Cycle = 1% (500 ns) Maximum Duty Cycle = 99% (49.5 µs) VIN =1 2 V Minimum Gate Drive Voltage = 8V (V GS) Total Gate Charge = 130 nC (80A MOSFET) Allowable VGS Drop (VDROP)=3 V Switch RDSON =1 0 0 m Driver Internal Bias Current = 20 µA (I BIAS) QMOSFET =1 3 0 n C QRESISTOR =[ ( V GS/R)  TON] QDRIVER =( I BIAS  TON) TON = 49.5 µs (99% DC) for worst case QRESISTOR =Q RESISTOR QDRIVER =2 0 µ A  49.5 µs = 0.99 nC DC MOTOR TVS CLAMP

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 43 MCP8021/2

5.2.2 BOOTSTRAP VOLTAGE

The pins which handle the highest voltage during motor operation are the boo tstrap pins (VBx). The bootstrap pin voltage is typically V BOOT (12V) higher than the associated phase voltage. When the high- side MOSFET is conducting, the phase pin voltage is typically at V DD and the bootstrap pin voltage is typically at V DD + 12V. When the phase MOSFETs switch, current induced voltage transients occur on the phase pins. These currents are caused by the MOSFET body diode revers e recovery and MOSFET turn-on/turn-off times. Those induced voltages cause the bootstrap pin voltages to also increase. Depending on the magnitude of the phase pin voltage, the bootstrap pin voltage may exceed the safe operating voltage of the device. The current induced transients may be reduced by slowing down the turn-on and turn- off times of the MOSFETs. The external MOSFETs may be slowed down by adding a 10 to 100 ohm resis- tor in series with the gate drive. A 1 nF to 10 nF ceramic capacitor may be added that connects each MOSFET gate and source terminal. The added capac- itance slows down the switching times of the MOSFET while allowing the gate resistance to remain small enough to keep the gate clamped off. The added capacitance also results in a lower slew rate of the phase node and limits the shoot-through current caused by the body diode reverse recovery. The high-side MOSFETs may also be slowed down by inserting a 10  to 25  resistor between each boot- strap pin and the associated bootstrap diode capacitor junction. Another 25  to 50  resistor is then added between the gate drive and the MOSFET gate. This results in a high-side turn-on resistance of 25  plus the series gate resistor. The high-side turn-off resistance only consists of the series gate resistance and allows for a faster shut-off time. Care must be taken to make sure the voltage drop across the boot- strap pin resistor does not cause an external MOSFET undervoltage Fault. When a system motor power supply voltage clamp is not used, 33V or 36V transzorbs may be connected from each bootstrap pin (VBx) to the ground. This will ensure that the bootstrap voltage does not exceed the absolute maximum voltage allowed on the pins. The resistors connected between the bootstrap pins and the bootstrap diode/capacito r junctions, mentioned in the previous paragraph, may also be used in order to limit the transzorb current and reduce the transzorb package size.

5.2.3 FLOATING GATE SUPPRESSION

The gate drive pins may float when the supply voltage is lost or an overvoltage situation shuts down the driver. When an overvoltage condition exists, the driver high-side and low- side outputs are tri-state. Each external MOSFET that is connected to the gate driver should have a gate-to-source resistor to bleed off any charge that may accumulate due to the tri- state. This will help prevent inadvertent turn-on of the MOSFET. Figure 5-3 shows the location of the overvoltage transzorbs (or equivalent circuits), gate resistors, bootstrap resistors and gate-to-source resistors.

5.2.4 MOSFET BODY DIODE REVERSE

When motor current is flowing through the external MOSFET body diodes and the complimentary MOSFET of the phase pair turns on, the body diode reverse recovery creates a momentary short circuit until the reverse recovery time is complete. When the body diode reverse recovery is complete, the current path is opened, causing the phase node voltage to slew rapidly towards ground or V DD levels. The rapid slew rate may cause an inversion of the gate-to- source voltage on the MOSFET that is turning on and result in that MOSFET turning off. The fast slew rate may also cause ringing on the phase node and also the sense resistor if the turn-off is too fast. The first remedy for the low-side turn-off is to slow down the MOSFET gate-to-source turn-off. This remedy the RDSON of the low-side MOSFET to gradually increase as the gate voltage drops and the low-side MOSFET slowly turns off. The slow turn-off allows the phase volt- age, generated by the motor current flowing through the low-side MOSFET R DSON, to slowly rise towards the positive motor supply level. The same scenario is also valid for turning on the low- side MOSFET when the high-side MOSFET has just been turned off and current was flowing from the high- side into the motor.

DS20006265D-page 44  2020-2024 Microchip Technology Inc. and its subsidiaries The MOSFET body diode reverse recovery situation occurs when the low-side MOSFETs are turned on while the motor current is flowing to the positive source through the high-side MOSFET body diode. The diode reverse recovery time allows a short circuit to exist between the positive supply and the low-side MOSFET drain until the high-side diode is reverse biased and the reverse recovery time has elapsed. The first remedies above should be used to slow the switching speeds of the MOSFETs. Then, a snubber is added to each MOSFET to fine-tune the phase node slew rate and eliminate any further transients. Adding a drain-to-source snubber slows down the slew rate of the phase node and results in a more controlled excur- sion of the phase node voltage. The snubber consists of a resistor and a capac itor connected in series between the drain and source of the MOSFET. The resistor is chosen to keep the initial snubber voltage below a few volts when peak motor current is flowing through the body diode. Th e capacitor is then chosen to provide an RC time constant longer than the MOSFET body diode reverse recovery time. A 0.1  resistor is typically used, along with a 0.1 μF capacitor to provide an RC of 10 ns. The power dissipated by the capacitor is calculated by applying Equation 5-1. EQUATION 5-1: SNUBBER CAPACITOR POWER DISSIPATION The capacitor and resistor form factors are chosen to handle the dissipated power.

5.2.5 MOTOR CURRENT SENSE

A sense resistor in series with the bridge ground return provides a current signal for feedback. This resistor should be non-inductive to minimize ringing from high di/dt. Any inductance in the power circuit represents potential problems in the form of additional voltage stress and ringing, as we ll as increasing switching times. While impractical to eliminate, careful layout and bypassing will minimize these effects. The output stage should be as compact as heat sinking will allow, with wide, short traces carrying all pulsed currents. Each half-bridge should be separately bypassed with a low-ESR/ESL capacitor, decoupling it from the rest of the circuit. Some layouts will allow the input filter capacitor to be split into three smaller values and serve double duty as the half-bridge bypass capacitors. PDISS = 2    f  C  V2  Dissipation Factor Where: f = PWM Frequency C = Capacitance V = Motor Voltage Dissipation Factor = 2  p  f  C  ESR = ESR/XC

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 45 MCP8021/2

5.2.6 AUTO-BAUD CODE EXAMPLE

Example 5-1 is a dsPIC ® DSC code example using the auto-baud function. EXAMPLE 5-1: dsPIC ® DSC AUTO-BAUD EXAMPLE // #define FCY 70000000UL #define TypBaudrate 9600uL #define U1BRG_BAUDRATE (FCY/(16 * TypBaudrate)) - 1 #define U1BRG_BAUD_MIN ((((FCY/(16 * TypBaudrate)) - 1)*1.07f)) //plus 7% #define U1BRG_BAUD_MAX ((((FCY/(16 * TypBaudrate)) - 1)*0.93f)) //minus 7% #define U1BRG_BREAK (FCY/(16 * 7880uL)) - 1 //7880 baud-rate is midpoint of //required break window for MCP8021 void UART1_Init(void){ //UART configuration - setup PPS connections U1MODEbits.UARTEN = 1; // enable UART //and UART module enable here void UART1_AutoBaud(void){ U1MODEbits.ABAUD = 0; int lastBRG = U1BRG; //save last known good BRG value - on POR BRG value //will be 0x0 U1STAbits.UTXEN = 1; //Transmit enabled, UxTX pin controlled by UARTx while(U1STAbits.UTXBF); //Wait for transmit buffer to empty while(!U1STAbits.TRMT); //wait for last byte to finish transmitting U1BRG = U1BRG_BREAK; //7880baud representing 1.65ms dominant //with 13bit BREAK U1STAbits.UTXBRK = 1; //Send BREAK command U1TXREG = 0x00; //Dummy write to start BREAK command while (U1STAbits.UTXBRK); //wait for completion of BREAK sequence while (!U1STAbits.TRMT); //wait for last break bit to transmit U1STAbits.UTXEN = 0; //disable TX while waiting on 0x55 from MCP8021 U1MODEbits.ABAUD = 1; //start the ABAUD counter upon receipt of //next byte (0x55) while(U1MODEbits.ABAUD); //application should handle timeout if auto-baud //does not complete and attempt auto-baud routine again //verify new baud clock is within limits of MCP8021 min and //max baud-rate if ((U1BRG > U1BRG_BAUD_MAX) && (U1BRG < U1BRG_BAUD_MIN)){ //success, use new baud-rate //generator value else{ U1BRG = lastBRG; //auto-baud out of range, reload last known good BRG value //and attempt auto-baud routine again

DS20006265D-page 46  2020-2024 Microchip Technology Inc. and its subsidiaries FIGURE 5-3: Overvoltage Protection. VBOOT VBA VBB VBC HSA HSB HSC PHA PHB PHC LSA LSB LSC TVS 33V VDD TVS 24V 10K 30.7V Clamp A B C

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 47 MCP8021/2

6.0 PACKAGE INFORMATION

6.1 Package Marking Information

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part num ber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. XXXXXXX 28-Lead VQFN (5x5 mm) PIN 1 XXXX XXX YYWWNNN MCP8021 Example PIN 1 3315 9PX 1913256 XXXXXXXXXXXXX 28-Lead TSSOP (4.4 mm) XXXXXXXXXXXXX YYWWNNN MCP8021 Example 5015KEX 1913256 MCP8021

DS20006265D-page 48  2020-2024 Microchip Technology Inc. and its subsidiaries XXXXXXX 40-Lead VQFN (5x5 mm) PIN 1 XXXXXXX XXXXXXX YYWWNNN MCP8022 Example PIN 1 3315 NHX 1913256 XXXXXXXXXXXXX 38-Lead TSSOP (4.4 mm) XXXXXXXXXXXXX YYWWNNN MCP8022 Example 3315SBX 1913256 MCP8022

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 49 MCP8021/2 BA 0.05 C 0.05 C

0.07 C A B

0.04 C (DATUM B) (DATUM A) C SEATING PLANE N TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N

0.10 C A B

0.10 C 0.08 C Microchip Technology Drawing C04-426 Rev D Sheet 1 of 2 28X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 28-Lead Very Thin Plastic Quad Flat, No Lead Package (9PX) - 5x5 mm Body [VQFN] With Stepped Wettable Flanks, 3.25x3.25mm Exposed Pad D E K (CH) L e 28X b NOTE 1 AA (A3) A A1 © 2023 Microchip Technology Inc.

DS20006265D-page 50  2020-2024 Microchip Technology Inc. and its subsidiaries REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: SECTION A-A ROTATED 180° Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

0.203 REF

0.35 0.20 0.80 0.00 0.25 0.40 0.85 0.02

5.00 BSC

0.45 0.30 0.90 0.05 MAX K- 0.20 -Terminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 3.15 3.25 3.35 3.15 3.25 3.35 Exposed Pad Chamfer CH 0.35 REF Microchip Technology Drawing C04-426 Rev D Sheet 2 of 2 28-Lead Very Thin Plastic Quad Flat, No Lead Package (9PX) - 5x5 mm Body [VQFN] With Stepped Wettable Flanks, 3.25x3.25mm Exposed Pad Wettable Flank Height A4 – Wettable Flank Width E3 – – 0.085 0.10 0.19

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 51 MCP8021/2 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Contact Pad Spacing Optional Center Pad Length Contact Pitch 3.35 3.35 MILLIMETERS E MAX 4.90 Contact Pad Length (X28) Contact Pad Width (X28) 0.85 0.30 Microchip Technology Drawing C04-2426 Rev D NOM C1Contact Pad Spacing 4.90 Contact Pad to Center Pad (X28) G1 0.35 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: EV EV E ØV SILK SCREEN Contact Pad to Contact Pad (X24) G2 0.20 28-Lead Very Thin Plastic Quad Flat, No Lead Package (9PX) - 5x5 mm Body [VQFN] With Stepped Wettable Flanks, 3.25x3.25mm Exposed Pad 0.20

DS20006265D-page 52  2020-2024 Microchip Technology Inc. and its subsidiaries TOP VIEW BOTTOM VIEW SIDE VIEW Sheet 1 of 2 Note: http://www.microchip.com/packaging For the most current package drawings, please see the Microchip Packaging Specification located at 28-Lead Shrink SmalO Outline Package (KEX) - 4.4 mm (.300 In.) Body [TSSOP] With 3.1x4.6 mm Exposed Pad Microchip Technology Drawing C04-521 Rev A A B D C SEATING PLANE 0.20 C 2X 14 TIPS

0.10 C A-B D

0.10 C D

0.10 C A-B

N 0.05 C NOTE 1 D E EE1 e A A2 28X b 0.05 C END VIEW SEE DETAIL A

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 53 MCP8021/2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 H DETAIL A Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Molded Package Width Molded Package Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.65 BSC

0.90 0.50 0.19 0.05 0.60 MILLIMETERS MIN NOM 0.70 0.30 1.10 0.15 MAX L1 1.00 REFFootprint Overall Length D 9.70 BSC Terminal Thickness c 0.09 - 0.20 ș -0.09 -Lead Bend Radius -0.09 -Lead Bend Radius -0° 8°Foot Angle ș2 14°Mold Draft Angle 0.85 0.95 ș3 14°Mold Draft Angle

6.40 BSC

4.40 BSC

R ș c 4X ș3 (L1) L 4X ș2 28-Lead Shrink SmalOOutline Package (KEX) - 4.4 mm (.300 In.) Body [TSSOP] With 3.1x4.6 mm Exposed Pad Microchip Technology Drawing C04-521 Rev A Exposed Pad Length D1 4.50 4.60 4.70 Exposed Pad Width E2 3.00 3.10 3.20

DS20006265D-page 54  2020-2024 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Optional Center Pad Length Contact Pitch 4.70 3.20 MILLIMETERS E MAX Contact Pad Length (X28) Contact Pad Width (X28) 1.50 0.45 NOM CContact Pad Spacing 5.90 Contact Pad to Contact Pad (X26) G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Contact Pad to Center Pad (X28) G1 0.60 Microchip Technology Drawing C04-2521 Rev A 28-Lead Shrink SmalO Outline Package (KEX) - 4.4 mm (.300 In.) Body [TSSOP] With 3.1x4.6 mm Exposed Pad C EV EV E SILK SCREEN ØV

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 55 MCP8021/2 B A 0.05 C 0.05 C 0.04 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 N 2X TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N 0.10 C 0.08 C Microchip Technology Drawing C04-425 Rev D Sheet 1 of 2 40X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 40-Lead Very Thin Plastic Quad Flat, No Lead Package (NHX) - 5x5x0.9 mm Body [VQFN] With 3.7x3.7 mm Exposed Pad and Wettable Flanks D E 40X b e A (A3) (K) L e AA SECTION A-A ROTATED 180°

DS20006265D-page 56  2020-2024 Microchip Technology Inc. and its subsidiaries Microchip Technology Drawing C04-425 Rev D Sheet 2 of 2 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.40 BSC

3.60 0.30 0.15 0.80 0.00 0.20 0.40 3.70 0.85 0.02 3.80 0.50 0.25 0.90 0.05 MAX K 0.25 REFTerminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 3.60 3.70 3.80 40-Lead Very Thin Plastic Quad Flat, No Lead Package (NHX) - 5x5x0.9 mm Body [VQFN] With 3.7x3.7 mm Exposed Pad and Wettable Flanks Wettable Flank Height A4 – Wettable Flank Width E3 – – 0.085 0.10 0.19

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 57 MCP8021/2 RECOMMENDED LAND PATTERN Dimension Limits Units Optional Center Pad Width Contact Pad Spacing Optional Center Pad Length Contact Pitch 3.80 3.80 MILLIMETERS E MAX 5.00 Contact Pad Length (X40) Contact Pad Width (X40) 0.80 0.20 Microchip Technology Drawing C04-2425 Rev D NOM C1Contact Pad Spacing 5.00 Contact Pad to Center Pad (X40) G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: EV EV C2 Y2 CH E ØV Contact Pad to Pad (X36) G1 0.20 Chamfer CH 0.38 SILK SCREEN 40-Lead Very Thin Plastic Quad Flat, No Lead Package (NHX) - 5x5x0.9 mm Body [VQFN] With 3.7x3.7 mm Exposed Pad and Wettable Flanks

DS20006265D-page 58  2020-2024 Microchip Technology Inc. and its subsidiaries BA

0.20 C B A

C SEATING PLANE N TOP VIEW SIDE VIEW BOTTOM VIEW 0.076 C Microchip Technology Drawing C04-424A Sheet 1 of 2 38X 38X For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 38-Lead Thin Shrink Small Outline Package (SBX) - 4.4 mm Body [TSSOP] With 4.6x 3.2 mm Exposed Pad D EE1 E 38X b e A 0.05 EXPOSED THERMAL PAD NOTE 1 c SEE DETAIL A END VIEW

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 59 MCP8021/2 Microchip Technology Drawing C04-424A Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N 3.10 0.50 0.17 0.05 0.60 3.20 3.30 0.70 0.27 1.10 0.15 MAX 14° REF REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Dimensioning and tolerancing per ASME Y14.5M Mold Draft Angle 38-Lead Thin Shrink Small Outline Package (SBX) - 4.4 mm Body [TSSOP] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 4.6x 3.2 mm Exposed Pad Overall Length Exposed Pad Length D D1 4.50 4.60 4.70 L (L1) ș1° (ș°) (ș°) S R DETAIL A Molded Package Width E1 4.40 0.85 0.90 0.95 9.60 9.70 9.80 4.30 4.60 Terminal Width c 0.09 - 0.20 Terminal Foot Angle 0° - 8° S0 . 2 0 - -Lead Shoulder Terminal Length L1 1.00 REF ș

DS20006265D-page 60  2020-2024 Microchip Technology Inc. and its subsidiaries RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Center Pad Length Contact Pitch 3.30 4.70 MILLIMETERS E MAX Contact Pad Length (X38) Contact Pad Width (X38) 1.50 0.30 Microchip Technology Drawing C04-2424A NOM 38-Lead Thin Shrink Small Outline Package (SBX) - 4.4 mm Body [TSSOP] CContact Pad Spacing 5.90 Thermal Via Diameter V Thermal Via Pitch EV 0.30 1.00 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: With 4.6x 3.2 mm Exposed Pad C e SILK SCREEN ØV EV EV

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 61 MCP8021/2 APPENDIX A: REVISION HISTORY Revision D (April 2024)

• Updated Register 4-5.
• Added automotive qualification to Features and examples to Product Identification System.
• Made minor text and format changes throughout the document. Revision C (February 2023)
• Updated Applications.
• Updated Product Identification System.
• Updated Package Information. Revision B (April 2022)
• Updated Features.
• Updated Description.
• Updated Package Types – MCP8022.
• Updated Functional Block Diagram.
• Updated Typical Application Circuit.
• Updated Section 1.0 “Electrical Characteristics”.
• Updated AC/DC Characteristics table.
• Replaced graph in Figure 2-3.
• Updated Table 3-1: MCP8021 Pin Function Table.
• Updated Table 3-2: MCP8022 Pin Function Table.
• Updated Section 3.2 “Low-Side PWM Inputs (PWMAL, PWMBL, PWMCL)”.
• Updated Section 3.3 “High-Side PWM Inputs (PWMAH, PWMBH, PWMCH)”.
• Updated Section 3.4 “Output Enable Input (OE)”.
• Updated Section 3.9 “Wake Input (WAKE)”.
• R e p l a c e d Figure 4-1. Revision A (July 2020)
• Initial release of this document.

DS20006265D-page 62  2020-2024 Microchip Technology Inc. and its subsidiaries NOTES:

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 63 MCP8021/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XXX PackageTemperature Range Device Device: MCP8021 = 3-Phase BLDC Motor Gate Driver (VQFN-28, TSSOP-28) MCP8021T = 3-Phase BLDC Motor Gate Driver, Tape and Reel (VQFN-28, TSSOP-28) MCP8022 = 3-Phase BLDC Motor Gate Driver (VQFN-40, TSSOP-38) MCP8022T = 3-Phase BLDC Motor Gate Driver, Tape and Reel (VQFN-40, TSSOP-38) Tape and Reel: T = Tape and Reel (1) Blank = Standard packaging (tube) Output Voltage Option: 3315 = 3.3V 5015 = 5.0V Temperature Range: H= - 4 0 C to +150 C (High) Package: 9PX = 28-Lead VQFN KEX = 28-Lead TSSOP NHX = 40-Lead VQFN SBX = 38-Lead TSSOP Qualification: VAO = AEC-Q100 Automotive Qualified Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. X Tape and Reel Option -XXXX Output Voltage Examples: a) MCP8021T-5015H/9PXVAO: Tape and Reel, 5.0V Output Voltage, High Temperature, 28-Lead 5x5 VQFN package, AEC-Q100 Automotive Qualified b) MCP8022T-5015H/NHXVAO: Tape and Reel, 5.0V Output Voltage, High Temperature, 40-Lead 5x5 VQFN package, AEC-Q100 Automotive Qualified c) MCP8021T-3315H/9PXVAO: Tape and Reel, 3.3V Output Voltage, High Temperature, 28-Lead 5x5 VQFN package, AEC-Q100 Automotive Qualified d) MCP8022T-3315H/NHXVAO: Tape and Reel, 3.3V Output Voltage, High Temperature, 40-Lead 5x5 VQFN package, AEC-Q100 Automotive Qualified e) MCP8021T-3315H/KEXVAO: Tape and Reel 3.3V Output Voltage, High Temperature, 28-Lead 4x4 TSSOP package, AEC-Q100 Automotive Qualified f) MCP8022T-3315H/SBXVAO: Tape and Reel, 3.3V Output Voltage, High Temperature, 38-Lead 4x4 TSSOP package, AEC-Q100 Automotive Qualified g) MCP8021-3315H/KEXVAO: Standard package (tube), 3.3V Output Voltage, High Temperature, 28-Lead 4x4 TSSOP package, AEC-Q100 Automotive Qualified h) MCP8022-5015H/NHXVAO: Standard package (tube), 5.0V Output Voltage, High Temperature, 40-Lead 5x5 VQFN package AEC-Q100 Automotive Qualified XXX Qualification

DS20006265D-page 64  2020-2024 Microchip Technology Inc. and its subsidiaries NOTES:

 2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 65 This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this informa- tion in any other manner violates these terms. Information regarding device applications is provided only for your conve- nience and may be superseded by updates. It is your responsi- bility to ensure t hat your applicatio n meets with your specifications. Contact your lo cal Microchip sales office for additional support or, obtai n additional support at https:// www.microchip.com/en-us/support/design-help/client-support- services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON- INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- RECT, SPECIAL, PUNITIVE , INCIDENTAL, OR CONSE- QUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applica- tions is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses ar e conveyed, implicitly or otherwise, under any Microchip intellectual pr operty rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter- Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART- I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY , ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020-2024, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-6683-4306-7 Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications c ontained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure w hen used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semic onductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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