MCP4011 MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

  • Volatile Digital Potentiometer in SOT-23, SOIC, MSOP and DFN packages
  • 64 Taps: 63 Resistors with Taps to terminal A and terminal B
  • Simple Up/Down (U/D) Protocol
  • Power-on Recall of Default Wiper Setting - Custom POR wiper settings available (contact factory)
  • Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ
  • Low Tempco: - Absolute (Rheostat): 50 ppm (0°C to 70°C typ.) - Ratiometric (Potentiometer): 10 ppm (typ.)
  • Low Wiper Resistance: 75Ω (typ.)
  • High-Voltage Tolerant Digital Inputs: Up to 12.5V
  • Low-Power Operation: 1 µA Max Static Current
  • Wide Operating Voltage Range: - 1.8V to 5.5V - Device Operation - 2.7V to 5.5V - Resistor Characteristics Specified
  • Extended Temperature Range: -40°C to +125°C
  • Wide Bandwidth (-3 dB) Operation: - 4 MHz (typ.) for 2.1 kΩ device

Description

The MCP4011/2/3/4 devices are volatile, 6-bit Digital Potentiometers that can be configured as either a potentiometer or rheostat. The wiper setting is controlled through a simple Up/Down (U/D) serial interface. Package Types Block Diagram Device Features A W B MCP4011 SOIC, MSOP, DFN MCP4012 SOT-23-6 MCP4013 SOT-23-6 MCP4014 SOT-23-5 Rheostat Potentiometer Potentiometer Rheostat A VSS W VDD U/D NC B CS 5 W CS VDD VSS U/D 6 A CS VDD VSS U/D 5 W A W B 6 A CS VDD VSS U/D 5 W A W W A B B VDD VSS U/D W B (Resistor Array) Wiper Register CS A 2-Wire Interface and Control Logic Power-Up and Brown-Out Control Device Wiper Configuration Memory Type POR Wiper Setting Resistance (typical) # of Steps VDD Operating Range (2) Control Interface WiperLock™ Technology Options (kΩ) Wiper (Ω) MCP4011 Potentiometer (1) RAM Mid-Scale 1.8V to 5.5V U/D No MCP4012 Rheostat RAM Mid-Scale 1.8V to 5.5V U/D No MCP4013 Potentiometer RAM Mid-Scale 1.8V to 5.5V U/D No MCP4014 Rheostat RAM Mid-Scale 1.8V to 5.5V U/D No Note 1: Floating either terminal (A or B) allows the device to be used in Rheostat mode. 2: Analog characteristics (resistor) tested from 2.7V to 5.5V. Low-Cost 64-Step Volatile Digital POT

© 2006 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V, VSS = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Operating Voltage Range VDD 2.7 5.5 V VDD 1.8 V VDD = 1.8V, CS:VIHH = 8.5V, VIH = 1.8V, VIL = 0V, U/D:VIH = 1.8V, VIL = 0V CS Input Voltage VCS VSS 12.5 V The CS pin will be at one of three input levels (VIL, VIH or VIHH). (Note 6) Supply Current IDD µA 5.5V, CS = VSS, fU/D = 1 MHz µA 2.7V, CS = VSS, fU/D = 1 MHz 0.3 µA Serial Interface Inactive (CS = VIH, U/D = VIH) Resistance (± 20%) RAB 1.68 2.1 2.52 kΩ -202 devices (Note 1) 4.0 6.0 kΩ -502 devices (Note 1) 8.0 12.0 kΩ -103 devices (Note 1) 40.0 60.0 kΩ -503 devices (Note 1) Note Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4012/14 only, test conditions are: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”. The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested. Device Resistance Current at Voltage Comments 5.5V 2.7V 2.1 kΩ 2.25 mA 1.1 mA MCP4012 includes VWZSE MCP4014 includes VWFSE 5 kΩ 1.4 mA 450 µA 10 kΩ 450 µA 210 µA 50 kΩ 90 µA 40 µA

© 2006 Microchip Technology Inc. DS21978C-page 3 MCP4011/2/3/4 Resolution N Taps No Missing Codes Step Resistance RS RAB / 63 Ω Note 6 Wiper Resistance (Note 3, Note 4) RW 125 Ω 5.5V 325 Ω 2.7V Nominal Resistance Tempco ΔR/ΔT ppm/°C TA = -20°C to +70°C 100 ppm/°C TA = -40°C to +85°C 150 ppm/°C TA = -40°C to +125°C Ratiometeric Tempco ΔVWA/Δ T ppm/°C MCP4011 and MCP4013 only, code = 1Fh Full-Scale Error (MCP4011/13 only) VWFSE -0.5 -0.1 +0.5 LSb Code 3Fh, 2.7V ≤ VDD ≤ 5.5V Zero-Scale Error (MCP4011/13 only) VWZSE -0.5 +0.1 +0.5 LSb Code 00h, 2.7V ≤ VDD ≤ 5.5V Monotonicity N Yes Bits Resistor Terminal Input Voltage Range (Terminals A, B and W) VA,VW, VB Vss VDD V Note 5, Note 6 Current through A, W or B IW 2.5 mA Note 6 Leakage current into A, W or B IWL 100 nA MCP4011 A = W = B = VSS 100 nA MCP4012/13 A = W = VSS 100 nA MCP4014 W = VSS Capacitance (PA) CAW pF f =1 MHz, code = 1Fh Capacitance (Pw) CW 120 pF f =1 MHz, code = 1Fh Capacitance (PB) CBW pF f =1 MHz, code = 1Fh Bandwidth -3 dB BW MHz -202 devices Code = 1F, output load = 30 pF MHz -502 devices MHz -103 devices 200 kHz -503 devices AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V, VSS = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Note Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4012/14 only, test conditions are: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”. The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested. Device Resistance Current at Voltage Comments 5.5V 2.7V 2.1 kΩ 2.25 mA 1.1 mA MCP4012 includes VWZSE MCP4014 includes VWFSE 5 kΩ 1.4 mA 450 µA 10 kΩ 450 µA 210 µA 50 kΩ 90 µA 40 µA

© 2006 Microchip Technology Inc. Potentiometer Integral Non-linearity INL -0.5 ±0.25 +0.5 LSb MCP4011/13 only (Note 2) Potentiometer Differential Non-linearity DNL -0.5 ±0.25 +0.5 LSb MCP4011/13 only (Note 2) Rheostat Integral Non-linearity MCP4011 (Note 4, Note 9) MCP4012 and MCP4014 (Note 4) R-INL -0.5 ±0.25 +0.5 LSb -202 devices (2.1 kΩ) 5.5V -8.5 +4.5 +8.5 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -502 devices (5 kΩ) 5.5V -5.5 +2.5 +5.5 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -103 devices (10 kΩ) 5.5V LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -503 devices (50 kΩ) 5.5V +0.25 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) Rheostat Differential Non-linearity MCP4011 (Note 4, Note 9) MCP4012 and MCP4014 (Note 4) R-DNL -0.5 ±0.25 +0.5 LSb -202 devices (2.1 kΩ) 5.5V +0.5 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -502 devices (5 kΩ) 5.5V +0.25 +1.25 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -103 devices (10 kΩ) 5.5V LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) -0.5 ±0.25 +0.5 LSb -503 devices (50 kΩ) 5.5V -0.5 +0.5 LSb 2.7V (Note 7) See Section 2.0 LSb 1.8V (Note 7, Note 8) AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V, VSS = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Note Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4012/14 only, test conditions are: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”. The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested. Device Resistance Current at Voltage Comments 5.5V 2.7V 2.1 kΩ 2.25 mA 1.1 mA MCP4012 includes VWZSE MCP4014 includes VWFSE 5 kΩ 1.4 mA 450 µA 10 kΩ 450 µA 210 µA 50 kΩ 90 µA 40 µA

© 2006 Microchip Technology Inc. DS21978C-page 5 MCP4011/2/3/4 Digital Inputs/Outputs (CS, U/D) Input High Voltage VIH

0.7 VDD

V Input Low Voltage VIL

0.3 VDD

V High-Voltage Input Entry Voltage VIHH 8.5 12.5 (6) V Threshold for WiperLock™ Technology High-Voltage Input Exit Voltage VIHH VDD+0.8(6) V CS Pull-up/Pull-down Resistance RCS kΩ VDD = 5.5V, VCS = 3V CS Weak Pull-up/Pull-down Current IPU 170 µA VDD = 5.5V, VCS = 3V Input Leakage Current IIL µA VIN = VDD CS and U/D Pin Capacitance CIN, COUT pF fC = 1 MHz, VDD ≥ 2.7V RAM (Wiper) Value Value Range N 3Fh hex Default POR Setting N 1Fh hex Power Requirements Power Supply Sensitivity (MCP4011 and MCP4013 only) PSS 0.0015 0.0035 %/% VDD = 4.5V to 5.5V, VA = 4.5V, Code = 1Fh 0.0015 0.0035 %/% VDD = 2.7V to 4.5V, VA = 2.7V, Code = 1Fh AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 2.7V to 5.5V, VSS = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Note Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4011/13 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4012/14 only, test conditions are: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. For voltages below 2.7V, refer to Section 2.0 “Typical Performance Curves”. The MCP4011 is externally connected to match the configurations of the MCP4012 and MCP4014 and then tested. Device Resistance Current at Voltage Comments 5.5V 2.7V 2.1 kΩ 2.25 mA 1.1 mA MCP4012 includes VWZSE MCP4014 includes VWFSE 5 kΩ 1.4 mA 450 µA 10 kΩ 450 µA 210 µA 50 kΩ 90 µA 40 µA

© 2006 Microchip Technology Inc. FIGURE 1-1: Increment Timing Waveform. CS U/D tLCUR tLO tHI tLUC W tCSHI tS 1/fUD tCSLO tS tLCUF tLUC tLCUF SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions CS Low Time tCSLO µs CS High Time tCSHI 500 ns 2.7V ≤ VDD ≤ 5.5V ns 1.8V ≤ VDD < 2.7V U/D to CS Hold Time tLUC 500 ns 2.7V ≤ VDD ≤ 5.5V 750 ns 1.8V ≤ VDD < 2.7V CS to U/D Low Setup Time tLCUF 500 ns CS to U/D High Setup Time tLCUR µs U/D High Time tHI 500 ns U/D Low Time tLO 500 ns Up/Down Toggle Frequency fUD MHz Wiper Settling Time tS 0.5 µs 2.1 kΩ, CL = 100 pF µs 5 kΩ, CL = 100 pF µs 10 kΩ, CL = 100 pF µs 50 kΩ, CL = 100 pF Wiper Response on Power-up tPU 200 ns

© 2006 Microchip Technology Inc. DS21978C-page 7 MCP4011/2/3/4 FIGURE 1-2: Decrement Timing Waveform. CS U/D tLCUR tHI tLO W tS tCSLO tLUC tCSHI tLUC tLCUF tS 1/fUD SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions CS Low Time tCSLO µs CS High Time tCSHI 500 ns 2.7V ≤ VDD ≤ 5.5V ns 1.8V ≤ VDD < 2.7V U/D to CS Hold Time tLUC 500 ns 2.7V ≤ VDD ≤ 5.5V 750 ns 1.8V ≤ VDD < 2.7V CS to U/D Low Setup Time tLCUF 500 ns CS to U/D High Setup Time tLCUR µs U/D High Time tHI 500 ns U/D Low Time tLO 500 ns Up/Down Toggle Frequency fUD MHz Wiper Settling Time tS 0.5 µs 2.1 kΩ, CL = 100 pF µs 5 kΩ, CL = 100 pF µs 10 kΩ, CL = 100 pF µs 50 kΩ, CL = 100 pF Wiper Response on Power-up tPU 200 ns

© 2006 Microchip Technology Inc. FIGURE 1-3: High-Voltage Increment Timing Waveform. CS U/D tHCUR tLO tHI tHUC W tCSHI tS 1/fUD tCSLO tS tHCUF tHUC tHCUF 12V SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions CS Low Time tCSLO µs CS High Time tCSHI 500 ns 2.7V ≤ VDD ≤ 5.5V ns 1.8V ≤ VDD < 2.7V U/D High Time tHI 500 ns U/D Low Time tLO 500 ns Up/Down Toggle Frequency fUD MHz HV U/D to CS Hold Time tHUC 1.5 µs HV CS to U/D Low Setup Time tHCUF µs HV CS to U/D High Setup Time tHCUR 4.5 µs Wiper Settling Time tS 0.5 µs 2.1 kΩ, CL = 100 pF µs 5 kΩ, CL = 100 pF µs 10 kΩ, CL = 100 pF µs 50 kΩ, CL = 100 pF Wiper Response on Power-up tPU 200 ns

© 2006 Microchip Technology Inc. DS21978C-page 9 MCP4011/2/3/4 FIGURE 1-4: High-Voltage Decrement Timing Waveform. CS U/D tHCUR tHI tLO W tS tCSLO tHUC tCSHI tHUC tHCUF tS 12V 1/fUD SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +1.8V to 5.5V, TA = -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions CS Low Time tCSLO µs CS High Time tCSHI 500 ns 2.7V ≤ VDD ≤ 5.5V ns 1.8V ≤ VDD < 2.7V U/D High Time tHI 500 ns U/D Low Time tLO 500 ns Up/Down Toggle Frequency fUD MHz HV U/D to CS Hold Time tHUC 1.5 µs HV CS to U/D Low Setup Time tHCUF µs HV CS to U/D High Setup Time tHCUR 4.5 µs Wiper Settling Time tS 0.5 µs 2.1 kΩ, CL = 100 pF µs 5 kΩ, CL = 100 pF µs 10 kΩ, CL = 100 pF µs 50 kΩ, CL = 100 pF Wiper Response on Power-up tPU 200 ns

© 2006 Microchip Technology Inc. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range TA -40 +125 Operating Temperature Range TA -40 +125 Storage Temperature Range TA -65 +150 Thermal Package Resistances Thermal Resistance, 5L-SOT-23 θJA °C/W Thermal Resistance, 6L-SOT-23 θJA 120 °C/W Thermal Resistance, 8L-DFN (2x3) θJA °C/W Thermal Resistance, 8L-MSOP θJA 206 °C/W Thermal Resistance, 8L-SOIC θJA 163 °C/W

© 2006 Microchip Technology Inc. DS21978C-page 25 MCP4011/2/3/4 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE 3.1 Positive Power Supply Input (VDD) The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS and can range from 1.8V to 5.5V. A decoupling capacitor on VDD (to VSS) is recommended to achieve maximum performance. 3.2 Ground (VSS) The VSS pin is the device ground reference. 3.3 Potentiometer Terminal A The terminal A pin is connected to the internal potenti- ometer’s terminal A (available on some devices). The potentiometer’s terminal A is the fixed connection to the 0x3F terminal of the digital potentiometer. The terminal A pin is available on the MCP4011, MCP4012 and MCP4013 devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4014. The potentiometer’s terminal A is internally floating. 3.4 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potenti- ometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. 3.5 Potentiometer Terminal B The terminal B pin is connected to the internal potenti- ometer’s terminal B (available on some devices). The potentiometer’s terminal B is the fixed connection to the 0x00 terminal of the digital potentiometer. The terminal B pin is available on the MCP4011 device. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. The terminal B pin is not available on the MCP4012, MCP4013 and MCP4014 devices. For the MCP4013 and MCP4014, the internal potenti- ometer’s terminal B is internally connected to VSS. Terminal B does not have a polarity relative to terminals W or A. Terminal B can support both positive and negative current. For the MCP4012, terminal B is internally floating. Pin Number Symbol Pin Type Buffer Type Function MCP4011 (SOIC-8) MCP4012 MCP4013 (SOT-23-6) MCP4014 (SOT-23-5) VDD P Positive Power Supply Input VSS P Ground A I/O A Potentiometer Terminal A W I/O A Potentiometer Wiper Terminal CS I TTL Chip Select Input B I/O A Potentiometer Terminal B NC No Connection U/D I TTL Increment/Decrement Input Legend: TTL = TTL compatible input A = Analog input I = Input O = Output P = Power

© 2006 Microchip Technology Inc. 3.6 Chip Select (CS) The CS pin is the chip select input. Forcing the CS pin to VIL enables the serial commands. These commands can increment and decrement the wiper. Forcing the CS pin to VIHH enables the high-voltage serial commands. These commands can increment and decrement the wiper and are compatibe with the MCP402X devices. The wiper is saved to volatile memory (RAM). The CS pin has an internal pull-up resistor. The resistor will become “disabled” when the voltage on the CS pin is below the VIH level. This means that when the CS pin is “floating”, the CS pin will be pulled to the VIH level (serial communication (the U/D pin) is ignored). And when the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption when serial commands are occurring. See Figure 2-3 for additional information. 3.7 Increment/Decrement (U/D) The U/D pin input is used to increment or decrement the wiper on the digital potentiometer. An increment moves the wiper one step toward terminal A, while a decrement moves the wiper one step toward terminal B.

© 2006 Microchip Technology Inc. DS21978C-page 27 MCP4011/2/3/4 4.0 GENERAL OVERVIEW The MCP4011/2/3/4 devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. devices include:

  • Set point or offset trimming
  • Sensor calibration
  • Selectable gain and offset amplifier designs
  • Cost-sensitive mechanical trim pot replacement The digital potentiometer is available in four nominal resistances (RAB), where the nominal resistance is defined as the resistance between terminal A and terminal B. The four nominal resistances are 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ. There are 63 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 63 resistors thus providing 64 possible settings (including terminal A and terminal B). Figure 4-1 shows a block diagram for the resistive network of the device. Equation 4-1 shows the calculation for the step resistance, while Equation 4-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. FIGURE 4-1: Resistor Block Diagram. EQUATION 4-1: RS CALCULATION EQUATION 4-2: RWB CALCULATION

1 LSb is the ideal resistance difference between two

successive codes. If we use N = 1 and RW = 0 in Equation 4-2, we can calculate the step size for each increment or decrement command. The MCP4011 device offers a voltage divider (potentiometer) with all terminals available on pins. The MCP4012 is a true rheostat, with terminal A and the wiper (W) of the variable resistor available on pins. The MCP4013 device offers a voltage divider (potenti- ometer) with terminal B connected to ground. The MCP4014 device is a Rheostat device with terminal A of the resistor floating, terminal B connected to ground, and the wiper (W) available on pin. The MCP4011 can be externally configured to implement any of the MCP4012, MCP4013 or MCP4014 configurations. 4.1 Serial Interface A 2-wire synchronous serial protocol is used to increment or decrement the digital potentiometer’s wiper terminal. The Increment/Decrement (U/D) protocol utilizes the CS and U/D input pins. Both inputs are tolerant of signals up to 12.5V without damaging the device. The CS pin can differenciate between two high-voltage levels, VIH and VIHH. This enables additional commands without requiring additional input pins. The high-voltage commands (VIHH on the CS pin) are similar to the standard commands and are supported for compatability to the MCP401X family of devices. The simple U/D protocol uses the state of the U/D pin at the falling edge of the CS pin to determine if Increment or Decrement mode is desired. Subsequent rising edges of the U/D pin move the wiper. The wiper value will not underflow or overflow. RS A RS RS RS B N = 63 N = 62 N = 61 N = 1 N = 0 RW (1) W 01h Analog Mux RW (1) 00h RW (1) 3Dh RW (1) 3Eh RW (1) 3Fh Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation effects the smaller resistance devices (2.1 kΩ) more. RS RAB RWB RABN RW N = 0 to 63 (decimal)

© 2006 Microchip Technology Inc. DS21978C-page 29 MCP4011/2/3/4 5.0 SERIAL INTERFACE 5.1 Overview The MCP4011/2/3/4 utilizes a simple 2-wire interface to increment or decrement the digital potentiometer’s wiper terminal (W). This interface uses the CS and U/D pins. The CS pin is the Chip Select input, while the U/D pin is the Up/Down input. The Increment/Decrement protocol enables the device to move one step at a time through the range of possible resistance values. The wiper value is initialized with the “default” value upon power-up. A wiper value of 00h connects the wiper to terminal B. A wiper value of 3Fh connects the wiper to terminal A. Increment commands move the wiper toward terminal A, but will not increment to a value greater than 3Fh. Decrement commands move the wiper toward terminal B, but will not decrement below 00h. Refer to Section 1.0 “Electrical Characteristics”, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. Communication is unidirectional. Therefore, the value of the current wiper setting cannot be read out of the MCP401X device. 5.2 Serial Commands The MCP401X devices support eight serial commands. Six of these commands are for support and to ease migration with the MCP402X family of devices. The commands can be grouped into the following types:

  • Serial Commands
  • High-voltage Serial Commands All the commands are shown in Table 5-1. The command type is determined by the voltage level the CS pin is driven to. The initial state that the CS pin must be driven is VIH. From VIH, the two levels that the CS pin can be driven are:
  • VIL
  • VIHH If the CS pin is driven from VIH to VIL, a serial command is selected. If the CS pin is driven from VIH to VIHH, a high-voltage serial command is selected. Support of the high-voltage serial commands is for compatiblity with the MCP402X devices. TABLE 5-1: COMMANDS Command Name High Voltage on CS pin? Increment Increment (for MCP402X Compatibility) Decrement Decrement (for MCP402X Compatibility) High-Voltage Increment 1 (for MCP402X Compatibility) Yes High-Voltage Increment 2 (for MCP402X Compatibility) Yes High-Voltage Decrement 1 (for MCP402X Compatibility) Yes High-Voltage Decrement 2 (for MCP402X Compatibility) Yes

© 2006 Microchip Technology Inc. 5.2.1 INCREMENT This mode is achieved by initializing the U/D pin to a high state (VIH) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. This is shown in Figure 5-1. After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. When the device voltage falls below the RAM retention voltage of the device, the wiper state may be corrupted. When the device returns to the operating range, the wiper will be loaded with the default POR wiper setting. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-1: Increment. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. U/D CS Wiper X+1 X X+2 X+3 X+4 VIH VIH VIL VIL

© 2006 Microchip Technology Inc. DS21978C-page 31 MCP4011/2/3/4 5.2.2 INCREMENT (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to a high state (VIH) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin increments the wiper setting toward terminal A. This is shown in Figure 5-2. After the wiper is incremented to the desired position, the U/D pin should be driven low (VIL), and the CS pin should be forced to VIH to ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. When the device voltage falls below the RAM retention voltage of the device, the wiper state may be corrupted. When the device returns to the operating range, the wiper will be loaded with the Default POR wiper setting. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-2: Increment (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. U/D CS Wiper X+1 X X+2 X+3 X+4 VIH VIH VIH VIL VIL

© 2006 Microchip Technology Inc. 5.2.3 DECREMENT This mode is achieved by initializing the U/D pin to a low state (VIL) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin will decrement the wiper setting toward terminal B. This is shown in Figure 5-3. After the wiper is decremented to the desired position, the U/D pin should be forced low (VIL) and the CS pin should be forced to VIH. This will ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to decrement. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. When the device voltage falls below the RAM retention voltage of the device, the wiper state may be corrupted. When the device returns to the operating range, the wiper will be loaded with the default POR wiper setting. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-3: Decrement. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. U/D CS Wiper X-1 X X-2 X-3 X-4 VIH VIH VIL VIL VIL

© 2006 Microchip Technology Inc. DS21978C-page 33 MCP4011/2/3/4 5.2.4 DECREMENT (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to a low state (VIL) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. This is shown in Figure 5-4. After the wiper is decremented to the desired position, the U/D pin should remain high (VIH), and the CS pin should be forced to VIH to ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. When the device voltage falls below the RAM retention voltage of the device, the wiper state may be corrupted. When the device returns to the operating range, the wiper will be loaded with the default POR wiper setting. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-4: Decrement (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. U/D CS Wiper X-1 X X-2 X-3 X-4 VIH VIH VIL VIL

© 2006 Microchip Technology Inc. 5.2.5 HIGH-VOLTAGE INCREMENT 1 (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to a high state (VIH) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the high state (VIH) prior to forcing the CS pin to VIH. This is shown in Figure 5-5. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-5: High-Voltage Increment 1 (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting with the WiperLock Technology feature. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. U/D CS Wiper X+1 X X+2 X+3 X+4 VIHH VIH VIH VIH VIL VIH

© 2006 Microchip Technology Inc. DS21978C-page 35 MCP4011/2/3/4 5.2.6 HIGH-VOLTAGE INCREMENT 2 (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to a high state (VIH) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the low state (VIL) prior to forcing the CS pin to VIH. This is shown in Figure 5-6. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-6: High-Voltage Increment 2 (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting with the WiperLock Technology feature. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. U/D CS Wiper X+1 X X+2 X+3 X+4 VIHH VIH VIH VIL VIH VIL

© 2006 Microchip Technology Inc. 5.2.7 HIGH-VOLTAGE DECREMENT 1 (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to a low state (VIL) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to the low state (VIL) prior to forcing the CS pin to VIH. This is shown in Figure 5-7. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-7: High-Voltage Decrement 1 (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting with the WiperLock Technology feature. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. U/D CS Wiper X-1 X X-2 X-3 X-4 VIHH VIH VIH VIL VIH VIL

© 2006 Microchip Technology Inc. DS21978C-page 37 MCP4011/2/3/4 5.2.8 HIGH-VOLTAGE DECREMENT 2 (FOR MCP402X COMPATIBILITY) This mode is achieved by initializing the U/D pin to the low state (VIL) prior to driving the CS pin to VIHH. Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to a high state (VIH) prior to forcing the CS pin to VIH. This is shown in Figure 5-8. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. FIGURE 5-8: High-Voltage Decrement 2 (For MCP402X Compatibility). Note: This command allows compatibility with the MCP402X family, which supports updating of the non-volatile wiper setting with the WiperLock Technology feature. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. U/D CS Wiper X-1 X X-2 X-3 X-4 VIHH VDD VIH VIH VIH VIL

© 2006 Microchip Technology Inc. 6.3.2 MONOTONIC OPERATION Monotonic operation means that the device’s resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A). The wiper resistance is different at each tap location. When changing from one tap position to the next (either increasing or decreasing), the ΔRW is less than the ΔRS. When this change occurs, the device voltage and temperature are “the same” for the two tap positions. FIGURE 6-7: Resistance RBW. 0x3F 0x3E 0x3D 0x03 0x02 0x01 0x00 Digital Input Code Resistance (RBW) RW (@ tap) RS0 RS1 RS3 RS62 RS63 RBW = RSn + RW(@ Tap n) n = 0 n = ?

© 2006 Microchip Technology Inc. DS21978C-page 43 MCP4011/2/3/4 7.0 DESIGN CONSIDERATIONS In the design of a system with the MCP401X devices, the following considerations should be taken into account:

  • The Power Supply
  • The Layout 7.1 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 7-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. FIGURE 7-1: Typical Microcontroller Connections. 7.2 Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP4011/2/3/4’s performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended. VDD VDD VSS VSS MCP4011/2/3/4 0.1 µF PIC® Microcontroller 0.1 µF U/D CS W B A

© 2006 Microchip Technology Inc. DS21978C-page 47 MCP4011/2/3/4 9.0 DEVELOPMENT SUPPORT 9.1 Evaluation/Demonstration Boards Currently there are three boards that are available that can be used to evaluate the MCP401X family of devices. The MCP402X Digital Potentiometer Evaluation Board kit (MCP402XEV) contains a simple dem- onstration board utilizing a PIC10F206, the MCP401X and a blank PCB, which can be pop- ulated with any desired MCP4011/2/3/4 device in a SOT-23-5, SOT-23-6 or 150 mil SOIC 8-pin package. This board has two push buttons to control when the PIC® microcontroller generates MCP402X serial commands. The example firmware demonstrates the following commands:

  • Increment
  • Decrement
  • High-Voltage Increment and Enable WiperLock Technology
  • High-Voltage Decrement and Enable WiperLock Technology
  • High-Voltage Increment and Disable WiperLock Technology
  • High-Voltage Decrement and Disable WiperLock Technology The populated board (with the MCP4011) can be used to evaluate the other MCP401X devices by appropriately jumpering the PCB pads. The SOT-23-5/6 Evaluation Board (VSUPEV2) can be used to evaluate the characteristics of the MCP4012, MCP4013 and MCP4014 devices. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board (SOIC8EV) can be used to evaluate the characteristics of the MCP4011 device in either the SOIC or MSOP package. The MCP4XXX Digital Potentiometer Daughter Board allows the system designer to quickly evaluate the operation of Microchip Technol- ogy's MCP42XXX and MCP402X Digital Poten- tiometers. The board supports two MCP42XXX devices and an MCP402X device, which can be replaced with an MCP401X device. The board also has a voltage doubler device (TC1240A), which can be used to show the WiperLock™ Technology feature of the MCP4021. These boards may be purchased directly from the Microchip web site at www.microchip.com.

© 2006 Microchip Technology Inc. 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 5-Lead SOT-23 (MCP4014) Example: XXNN JU25 Part Number Code MCP4014T-202E/OT JUNN MCP4014T-502E/OT JVNN MCP4014T-103E/OT JWNN MCP4014T-503E/OT JXNN Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP4012 / MCP4013) Example: XXNN BJ25 Part Number Code MCP4012 MCP4013 MCP401xT-202E/CH BJNN BPNN MCP401xT-502E/CH BKNN BQNN MCP401xT-103E/CH BLNN BRNN MCP401xT-503E/CH BMNN BSNN Note: Applies to 6-Lead SOT-23 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e

© 2006 Microchip Technology Inc. DS21978C-page 49 MCP4011/2/3/4 Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e 8-Lead MSOP (MCP4011) Example: XXXXXX YWWNNN 401122 534256 Example: 8-Lead DFN (2x3) (MCP4011) XXX YWW NNN ABE 534 256 8-Lead SOIC (150 mil) (MCP4011) Example: XXXXXXXX XXXXYYWW NNN 401152E SN^^ 0534 256 e Part Number Code MCP4011T-202E/MC ABE MCP4011T-502E/MC ABF MCP4011T-103E/MC ABG MCP4011T-503E/MC ABH Note: Applies to 8-Lead DFN Part Numbers Code 8L-MSOP 8L-SOIC MCP4011-202E/MS MCP4011-202E/SN MCP4011-502E/MS MCP4011-502E/SN MCP4011-103E/MS MCP4011-103E/SN MCP4011-503E/MS MCP4011-503E/SN

© 2006 Microchip Technology Inc. 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging p D B n E L c β φ α A b Mold Draft Angle Bottom a Mold Draft Angle Top 0.50 0.43 0.35 .020 .017 .014 B Lead Width 0.20 0.15 0.09 .008 .006 .004 c Lead Thickness f Foot Angle 0.55 0.45 0.35 .022 .018 .014 L Foot Length 3.10 2.95 2.80 .122 .116 .110 D Overall Length 1.75 1.63 1.50 .069 .064 .059 Molded Package Width 3.00 2.80 2.60 .118 .110 .102 E Overall Width 0.15 0.08 0.00 .006 .003 .000 Standoff 1.30 1.10 0.90 .051 .043 .035 Molded Package Thickness 1.45 1.18 0.90 .057 .046 .035 A Overall Height 1.90 .075 Outside lead pitch (basic) 0.95 .038 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. Notes: EIAJ Equivalent: SC-74A Drawing No. C04-091 * Controlling Parameter Revised 09-12-05

© 2006 Microchip Technology Inc. DS21978C-page 51 MCP4011/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D B n E L c β φ α A β Mold Draft Angle Bottom α Mold Draft Angle Top 0.50 0.43 0.35 .020 .017 .014 B Lead Width 0.20 0.15 0.09 .008 .006 .004 c Lead Thickness φ Foot Angle 0.55 0.45 0.35 .022 .018 .014 L Foot Length 3.10 2.95 2.80 .122 .116 .110 D Overall Length 1.75 1.63 1.50 .069 .064 .059 Molded Package Width 3.00 2.80 2.60 .118 .110 .102 E Overall Width 0.15 0.08 0.00 .006 .003 .000 Standoff 1.30 1.10 0.90 .051 .043 .035 Molded Package Thickness 1.45 1.18 0.90 .057 .046 .035 A Overall Height

1.90 BSC

.075 BSC Outside lead pitch

0.95 BSC

.038 BSC p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. Notes: JEITA (formerly EIAJ) equivalent: SC-74A * Controlling Parameter Drawing No. C04-120 BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M Revised 09-12-05

© 2006 Microchip Technology Inc. 8-Lead Plastic Dual-Flat No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length Overall Width Exposed Pad Length Exposed Pad Width Contact Width Contact Length § Contact-to-Exposed Pad § Units Dimension Limits N e A D E b L K 0.80 0.00 1.30 1.50 0.18 0.30 0.20

0.50 BSC

0.90 0.02

0.20 REF

2.00 BSC

3.00 BSC

0.25 0.40 1.00 0.05 1.75 1.90 0.30 0.50 MIN NOM MAX MILLIMETERS Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. § Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–123, Sept. 8, 2006 NOTE 2 NOTE 1 NOTE 1 BOTTOM VIEW EXPOSED PAD K L N e b TOP VIEW N D E A

© 2006 Microchip Technology Inc. DS21978C-page 53 MCP4011/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging L ϕ c A b NOTE 1 e E D N Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width Units Dimension Limits N e A E D L ϕ c b 0.75 0.00 0.40 0.08 0.22

0.65 BSC

0.85

4.90 BSC

0.60

0.95 REF

1.10 0.95 0.15 0.80 0.23 0.40 MIN NOM MAX MILLIMETERS Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–111, Sept. 8, 2006

© 2006 Microchip Technology Inc. 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Foot Angle φ β Mold Draft Angle Bottom α Mold Draft Angle Top 0.51 0.42 0.33 .020 .017 .013 B Lead Width 0.25 0.23 0.20 .010 .009 .008 c Lead Thickness 0.76 0.62 0.48 .030 .025 .019 L Foot Length 0.51 0.38 0.25 .020 .015 .010 h Chamfer Distance 5.00 4.90 4.80 .197 .193 .189 D Overall Length 3.99 3.91 3.71 .157 .154 .146 Molded Package Width 6.20 6.02 5.79 .244 .237 .228 E Overall Width 0.25 0.18 0.10 .010 .007 .004 Standoff 1.55 1.42 1.32 .061 .056 .052 Molded Package Thickness 1.75 1.55 1.35 .069 .061 .053 A Overall Height 1.27 .050 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units D n p B E h L β c 45° φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 § Significant Characteristic

© 2006 Microchip Technology Inc. DS21978C-page 55 MCP4011/2/3/4 APPENDIX A:

REVISION HISTORY

Revision C (December 2006)

  • Added device designators in conditions column to associate units (MHz) in Bandwidth -3 dB parameter in AC/DC Characteristics table.
  • Added device designations in conditions column for R-INL and R-DNL specifications. Revision B (October 2006)
  • For the 10 kΩ device, the rheostat differential non-linearity specification at 2.7V was changed from ±0.5 LSb to ±1 LSb.
  • Figure 2-9 in Section 2.0 “Typical Performance Curves” was updated with the correct data.
  • Added Figure 2-55 for -3 db Bandwidth information.
  • Added Figure 2-56 for -3 db Bandwidth test circuit.
  • Updated available Development Tools
  • Added disclaimer to package outline drawings and updated changed drawings as needed. Revision A (November 2005)
  • Original Release of this Document.

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21978C-page 57 MCP4011/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: MCP4011: Single Potentiometer with U/D Interface MCP4011T: Single Potentiometer with U/D Interface (Tape and Reel) (SOIC, MSOP) MCP4012: Single Rheostat with U/D interface MCP4012T: Single Rheostat with U/D interface (Tape and Reel) (SOT-23-6) MCP4013: Single Potentiometer to GND with U/D Interface MCP4013T: Single Potentiometer to GND with U/D Interface (Tape and Reel) (SOT-23-6) MCP4014: Single Rheostat to GND with U/D Interface MCP4014T: Single Rheostat to GND with U/D Interface (Tape and Reel)(SOT-23-5) Resistance Version: 202 = 2.1 kΩ 502 = 5 kΩ 103 = 10 kΩ 503 = 50 kΩ Temperature Range: E = -40°C to +125°C Package: CH = Plastic Small Outline Transistor, 6-lead MC = Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead MS = Plastic MSOP, 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead OT = Plastic Small Outline Transistor, 5-lead PART NO. X /XX Package Temperature Range Device Examples: MCP4011-103E/MS: 10 kΩ, 8-LD MSOP MCP4011-103E/SN: 10 kΩ, 8-LD SOIC MCP4011T-103E/MC: T/R, 10 kΩ, 8-LD DFN MCP4011T-103E/MS: T/R, 10 kΩ, 8-LD MSOP MCP4011T-103E/SN: T/R, 10 kΩ, 8-LD SOIC MCP4011-202E/MS: 2.1 kΩ, 8-LD MSOP MCP4011-202E/SN: 2.1 kΩ, 8-LD SOIC MCP4011T-202E/MC: T/R, 2.1 kΩ, 8-LD DFN MCP4011T-202E/MS: T/R, 2.1 kΩ, 8-LD MSOP MCP4011T-202E/SN: T/R, 2.1 kΩ, 8-LD SOIC MCP4011-502E/MS: 5 kΩ, 8-LD MSOP MCP4011-502E/SN: 5 kΩ, 8-LD SOIC MCP4011T-502E/MC: T/R, 5 kΩ, 8-LD DFN MCP4011T-502E/MS: T/R, 5 kΩ, 8-LD MSOP MCP4011T-502E/SN: T/R, 5 kΩ, 8-LD SOIC MCP4011-503E/MS: 50 kΩ, 8-LD MSOP MCP4011-503E/SN: 50 kΩ, 8-LD SOIC MCP4011T-503E/MC: T/R, 50 kΩ, 8-LD DFN MCP4011T-503E/MS: T/R, 50 kΩ, 8-LD MSOP MCP4011T-503E/SN: T/R, 50 kΩ, 8-LD SOIC MCP4012T-202E/CH 2.1 kΩ, 6-LD SOT-23 MCP4012T-502E/CH 5 kΩ, 6-LD SOT-23 MCP4012T-103E/CH 10 kΩ, 6-LD SOT-23 MCP4012T-503E/CH 50 kΩ, 6-LD SOT-23 MCP4013T-202E/CH 2.1 kΩ, 6-LD SOT-23 MCP4013T-502E/CH 5 kΩ, 6-LD SOT-23 MCP4013T-103E/CH 10 kΩ, 6-LD SOT-23 MCP4013T-503E/CH 50 kΩ, 6-LD SOT-23 MCP4014T-202E/OT 2.1 kΩ, 5-LD SOT-23 MCP4014T-502E/OT 5 kΩ, 5-LD SOT-23 MCP4014T-103E/OT 10 kΩ, 5-LD SOT-23 MCP4014T-503E/OT 50 kΩ, 5-LD SOT-23 XXX Resistance Version

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21978C-page 59 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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