MCP3204-BISL

MCP3204 MICROCHIP | Alldatasheet

Document overview

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Technical content

 1999 Microchip Technology Inc. Preliminary DS21298B-page 1 MCP3204/3208

FEATURES

• 12-bit resolution
• ± 1 LSB max DNL
• ± 1 LSB max INL (MCP3204/3208-B)
• ± 2 LSB max INL (MCP3204/3208-C)
• 4 (MCP3204) or 8 (MCP3208) input channels
• Analog inputs programmable as single-ended or pseudo differential pairs
• On-chip sample and hold
• SPI ® serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100ksps max. sampling rate at V DD = 5V
• 50ksps max. sampling rate at VDD = 2.7V
• Low power CMOS technology - 500 nA typical standby current, 2µA max. - 400 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• Available in PDIP , SOIC and TSSOP packages

APPLICATIONS

• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems

DESCRIPTION

The Microchip Technology Inc. MCP3204/3208 devices are successive approximation 12-bit Ana- log-to-Digital (A/D) Converters with on-board sample and hold circuitry. The MCP3204 is programmable to provide two pseudo-differential input pairs or four sin- gle-ended inputs. The MCP3208 is programmable to provide four pseudo-differential input pairs or eight sin- gle-ended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB (MCP3204/3208-C) versions. Communication with the devices is done using a simple serial interface compat- ible with the SPI protocol. The devices are capable of conversion rates of up to 100ksps. The MCP3204/3208 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typi- cal standby and active currents of only 500nA and 320µA, respectively. The MCP3204 is offered in 14-pin PDIP , 150mil SOIC and TSSOP packages, and the MCP3208 is offered in 16-pin PDIP and SOIC pack- ages. PACKAGE TYPES FUNCTIONAL BLOCK DIAGRAM VDD CLK D OUT MCP3204 VREF D IN CH0 CH1 CH2 CH3 CS /SHDNDGND AGND NC VDD CLK D OUT MCP3208 VREF D IN CS /SHDN DGND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 NC AGND PDIP, SOIC, TSSOP PDIP, SOIC Comparator Sample and Hold 12-Bit SAR DAC Control Logic CS /SHDN VREF VSSVDD CLK D OUT Shift Register CH0 Channel Mux InputCH1 CH7* *Note: Channels 5-7 available on MCP3208 Only D IN 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI® Serial Interface

DS21298B-page 2 Preliminary  1999 Microchip Technology Inc.

1.0 ELECTRICAL

1.1 Maximum Ratings*

Soldering temperature of leads (10 seconds) ..+300°C *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. PIN FUNCTION TABLE NAME FUNCTION VDD DGND AGND CH0-CH7 CLK D IN D OUT CS /SHDN VREF +2.7V to 5.5V Power Supply Digital Ground Analog Ground Analog Inputs Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input Reference Voltage Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 20*fSAMPLE , unless otherwise noted. PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS Conversion Rate Conversion Time t CONV 12 clock cycles Analog Input Sample Time t SAMPLE 1.5 clock cycles Throughput Rate f SAMPLE 100 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution 12 bits Integral Nonlinearity INL ±0.75 LSB MCP3204/3208-B MCP3204/3208-C Differential Nonlinearity DNL ±0.5 ±1 LSB No missing codes over temperature Offset Error ±1.25 ±3 LSB Gain Error ±1.25 ±5 LSB Dynamic Performance Total Harmonic Distortion -82 dB V IN = 0.1V to 4.9V@1kHz Signal to Noise and Distortion (SINAD) 72 dB V IN = 0.1V to 4.9V@1kHz Spurious Free Dynamic Range 86 dB V IN = 0.1V to 4.9V@1kHz Reference Input Voltage Range 0.25 V DD VN o t e 2 Current Drain 100 0.001 150 µA µA CS = VDD = 5V Analog Inputs Input Voltage Range for CH0-CH7 in Single-Ended Mode V SS VREF V Input Voltage Range for IN+ In pseudo-differential Mode IN- V REF +IN- Input Voltage Range for IN- In pseudo-differential Mode VSS -100 V SS +100 mV Leakage Current 0.001 ±1 µA

 1999 Microchip Technology Inc. Preliminary DS21298B-page 3 MCP3204/3208 Analog Inputs (Continued) Switch Resistance 1K Ω See Figure 4-1 Sample Capacitor 20 pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V IH 0.7 VDD V Low Level Input Voltage V IL 0.3 VDD V High Level Output Voltage V OH 4.1 V I OH = -1mA, VDD = 4.5V Low Level Output Voltage V OL 0.4 V I OL = 1mA, VDD = 4.5V Input Leakage Current I LI -10 10 µA V IN = VSS or VDD Output Leakage Current I LO -10 10 µA V OUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) C IN, COUT 10 pF V DD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters Clock Frequency f CLK 2.0 1.0 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time t HI 250 ns Clock Low Time t LO 250 ns CS Fall To First Rising CLK Edge tSUCS 100 ns Data Input Setup Time t SU 50 ns Data Input Hold Time t HD 50 ns CLK Fall To Output Data Valid tDO 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable t EN 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable t DIS 100 ns See Test Circuits, Figure 1-2 CS Disable Time t CSH 500 ns D OUT Rise Time t R 100 ns See Test Circuits, Figure 1-2 (Note 1) D OUT Fall Time t F 100 ns See Test Circuits, Figure 1-2 (Note 1) Power Requirements Operating Voltage V DD 2.7 5.5 V Operating Current I DD 320 225 400 µA V DD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V , DOUT unloaded Standby Current I DDS 0.5 2 µA CS = VDD = 5.0V Note 1:This parameter is guaranteed by characterization and not 100% tested. Note 2:See graphs that relate linearity performance to VREF levels. Note 3:Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 20*fSAMPLE , unless otherwise noted. PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS

 1999 Microchip Technology Inc. Preliminary DS21298B-page 5 MCP3204/3208

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V , VSS = 0V , fSAMPLE = 100ksps, fCLK = 20* fSAMPLE ,TA = 25°C FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF . FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 Sample Rate (ksps) INL (LSB) Positive INL Negative INL -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 VREF (V) INL(LSB) Positive INL Negative INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 1 02 03 04 05 06 07 08 0 Sample Rate (ksps) INL (LSB) Positive INL Negative INL VDD = VREF = 2.7V -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 VREF (V) INL(LSB) Positive INL Negative INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) VDD = VREF = 2.7V FSAMPLE = 50ksps

DS21298B-page 12 Preliminary  1999 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

3.1 CH0 - CH7

Analog inputs for channels 0 - 7 respectively for the multiplexed inputs. Each pair of channels can be pro- grammed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 4.1 and Section 5.0 for information on pro- gramming the channel configuration.

3.2 CS /SHDN(Chip Select/Shutdown)

The CS /SHDN pin is used to initiate communication with the device when pulled low and will end a conver- sion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.

3.3 CLK (Serial Clock)

The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.

3.4 D IN (Serial Data Input)

The SPI port serial data input pin is used to load chan- nel configuration data into the device.

3.5 D OUT (Serial Data output)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.

3.6 AGND

Analog ground connection to internal analog circuitry.

3.7 DGND

Digital ground connection to internal digital circuitry.

4.0 DEVICE OPERATION

The MCP3204/3208 A/D Converters employ a conven- tional SAR architecture. With this architecture, a sam- ple is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. Follow- ing this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3204/3208. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 4-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. the MCP3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each con- version begins. When used in the pseudo-differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (V REF + IN-). The IN- input is limited to ±100mV from the VSS rail. The IN- input can be used to cancel small signal com- mon-mode noise which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[V REF + (IN-)] - 1 LSB}, then the out- put code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS , then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS , then the FFFh code will not be seen unless the IN+ input level goes above V REF level. For the A/D Converter to meet specification, the charge holding capacitor, (CSAMPLE ) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram it is shown that the source impedance S) adds to the internal sampling switch (RSS ) imped- ance, directly affecting the time that is required to charge the capacitor, CSAMPLE . Consequently, larger source impedances increase the offset, gain, and inte- gral linearity errors of the conversion. See Figure 4-2.

4.2 R eference Input

For each device in the family, the reference input (VREF ) determines the analog input voltage range. As the ref- erence input is reduced, the LSB size is reduced accordingly. The theoretical digital output code pro- duced by the A/D Converter is a function of the analog input signal and the reference input as shown below. where: VIN = analog input voltage VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- ity in the operation of the reference device will have a direct effect on the operation of the A/D Converter. Digital Output Code = 4096 * VIN VREF

DS21298B-page 14 Preliminary  1999 Microchip Technology Inc.

5.0 SERIAL COMMUNICATIONS

Communication with the MCP3204/3208 devices is done using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the config- uration bits for the MCP3204 and MCP3208, respec- tively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. After the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a don’t care for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3204/3208 devices with hardware SPI ports. CONTROL BIT SELECTIONS INPUT CONFIGURATION CHANNEL SELECTIONSINGLE/ DIFF D2* D1 D0

1 X 0 0 single ended CH0

1 X 0 1 single ended CH1

1 X 1 0 single ended CH2

1 X 1 1 single ended CH3

0 X 0 0 differential CH0 = IN+

CH1 = IN-

0 X 0 1 differential CH0 = IN-

CH1 = IN+

0 X 1 0 differential CH2 = IN+

CH3 = IN-

0 X 1 1 differential CH2 = IN-

CH3 = IN+ *D2 is don’t care for MCP3204 TABLE 5-1: Configuration Bits for the MCP3204. CONTROL BIT SELECTIONS INPUT CONFIGURATION CHANNEL SELECTIONSINGLE/ DIFF D2 D1 D0 1 0 0 0 single ended CH0 1 0 0 1 single ended CH1 1 0 1 0 single ended CH2 1 0 1 1 single ended CH3 1 1 0 0 single ended CH4 1 1 0 1 single ended CH5 1 1 1 0 single ended CH6 1 1 1 1 single ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+ TABLE 5-2: Configuration Bits for the MCP3208.

DS21298B-page 16 Preliminary  1999 Microchip Technology Inc.

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3204/3208 with

Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3204/3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure 6-1 and Figure 6-2 shows how the MCP3204/3208 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0 which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains five leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Con- verter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCUs receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conver- sion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the con- verted data can be obtained by using this method. Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 16 CS SCLK D IN X = Don’t Care Bits 17 18 19 20 21 22 23 24 D OUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z MCU latches data from A/D Converter Data is clocked out of A/D Converter on falling edges on rising edges of SCLK DO Don’t CareSGL/ DIFF D1D2Start 00000 1 XX XXXD O XXXXX XXX D1D2SGL/ DIFF Start Bit (Null) MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 16 CS SCLK D IN X = Don’t Care Bits 17 18 19 20 21 22 23 24 D OUT DO Don’t Care NULL BIT B11 B10 B9 B8 B6 B5 B4 B3 B2 B1 B0HI-Z 00000 1 XX XXXDO SGL/ DIFF XXXXX XXX MCU latches data from A/D Converter on rising edges of SCLK Data is clocked out of A/D Converter on falling edges D1D2SGL/ DIFF Start Bit (Null) D1D2Start MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits

 1999 Microchip Technology Inc. Preliminary DS21298B-page 17 MCP3204/3208

6.2 Maintaining Minimum Clock Speed

When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2ms (effective clock fre- quency of 10kHz). Failure to meet this criterion may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.

6.3 Buffering/Filtering the Analog Inputs

If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccu- rate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive the analog input of the MCP3204/3208. This amplifier provides a low imped- ance source for the converter input and a low pass fil- ter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip’s free interactive FilterLab™ software. Fil- terLab will calculate capacitor and resistors values, as well as determine the number of poles that are required for the application. For more information on filtering sig- nals, see the application note AN699 “Anti-Aliasing Analog Filters for Data Acquisition Systems.” FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3204.

6.4 Layout Considerations

When laying out a printed circuit board for use with ana- log components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1µF is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possi- ble from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a “star” configuration can also reduce noise by eliminating return current paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 “Lay- out Tips for 12-Bit A/D Converter Applications”. FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. FilterLab is a trademark of Microchip T echnology Inc. in the U.S.A and other countries. All rights reserved. MCP3204 VDD 10µF IN- IN+ VIN C 1 C 2 VREF 4.096V Reference ADI REF198 1µF 1µF 0.1µFTant. 0.1µF MCP601R 1 R 2 R 3 R 4 VDD Connection Device 1 Device 2 Device 3 Device 4

DS21298B-page 18 Preliminary  1999 Microchip Technology Inc.

6.5 U tilizing the Digital and Analog

The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the sub- strate which has a resistance of 5 -10 Ω . If no ground plane is utilized, then both grounds must be connected to V SS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. FIGURE 6-5: Separation of Analog and Digital Ground Pins. VDD Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator Substrate 5 - 10 Ω Analog Ground Pin Digital Ground Pin

 1999 Microchip Technology Inc. Preliminary DS21298B-page 19 MCP3204/3208 MCP3204 PRODUCT IDENTIFICATION SYSTEMS To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3208 PRODUCT IDENTIFICATION SYSTEMS To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Package: P = PDIP (14 lead) SL = SOIC (150 mil Body), 14 lead ST = TSSOP , 14 lead (C Grade only) Temperature I= –40°C to +85°C Range: Performance B = ±1 LSB INL (TSSOP not available in this grade) Grade: C = ±2 LSB INL Device: MCP3204 = 4-Channel 12-Bit Serial A/D Converter MCP3204T = 4-Channel 12-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only) MCP3204 - G T /P Package: P = PDIP (16 lead) SL = SOIC (150 mil Body), 16 lead Temperature I= –40°C to +85°C Range: Performance B = ±1 LSB INL (TSSOP not available in this grade) Grade: C = ±2 LSB INL Device: MCP3208 = 8-Channel 12-Bit Serial A/D Converter MCP3208T = 8-Channel 12-Bit Serial A/D Converter on tape and reel (SOIC packages only) MCP3208 - G T /P Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Y our local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

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Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Beijing Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104 India Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Y okohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg.

2077 Y an’an Road West, Hong Qiao District

Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 ASIA/PACIFIC (continued) Singapore Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Taiwan, R.O.C Microchip T echnology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE United Kingdom Arizona Microchip Technology Ltd.

505 Eskdale Road

Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Arizona Microchip Technology SARL Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

91300 Massy, France

Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 München, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 11/15/99 WORLDWIDE SALES AND SERVICE Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.