MCP3202T-BI/P

MCP3202_06 MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

• 12-bit resolution
• ±1 LSB max DNL
• ±1 LSB max INL (MCP3202-B)
• ±2 LSB max INL (MCP3202-C)
• Analog inputs programmable as single-ended or pseudo-differential pairs
• On-chip sample and hold
• SPI serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V-5.5V
• 100 ksps max. sampling rate at VDD = 5V
• 50 ksps max. sampling rate at VDD = 2.7V
• Low power CMOS technology - 500 nA typical standby current, 5 μA max. - 550 µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin MSOP, PDIP, SOIC and TSSOP packages

Applications

• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems

Description

The Microchip Technology Inc. MCP3202 is a succes- sive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudo- differential input pair or dual single-ended inputs. Differ- ential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100 ksps at 5V and 50 ksps at 2.7V. The MCP3202 device oper- ates over a broad voltage range (2.7V-5.5V). Low- current design permits operation with typical standby and active currents of only 500 nA and 375 μA, respec- tively. The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Package Types Functional Block Diagram MCP3202 CH0 CH1 VSS CS/SHDN VDD/VREF CLK DOUT DIN PDIP, MSOP, SOIC, TSSOP Comparator Sample and Hold 12-Bit SAR DAC Control Logic CS/SHDN VSS VDD CLK DOUT Shift Register CH0 Channel Mux Input CH1 DIN 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface

© 2006 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TABLE Name Function VDD/VREF +2.7V to 5.5V Power Supply and Reference Voltage Input CH0 Channel 0 Analog Input CH1 Channel 1 Analog Input CLK Serial Clock DIN Serial Data In DOUT Serial Data Out CS/SHDN Chip Select/Shutdown Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE unless otherwise noted. Parameter Sym Min. Typ. Max. Units Conditions Conversion Rate: Conversion Time tCONV clock cycles Analog Input Sample Time tSAMPLE 1.5 clock cycles Throughput Rate fSAMPLE 100 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy: Resolution bits Integral Nonlinearity INL ±0.75 LSB LSB MCP3202-B MCP3202-C Differential Nonlinearity DNL ±0.5 LSB No missing codes over temperature Offset Error ±1.25 LSB Gain Error ±1.25 LSB Dynamic Performance: Total Harmonic Distortion THD -82 dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) SINAD dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range SFDR dB VIN = 0.1V to 4.9V@1 kHz Analog Inputs: Input Voltage Range for CH0 or CH1 in Single-Ended Mode VSS VDD V Input Voltage Range for IN+ in Pseudo-Differential Mode IN+ IN- VDD+IN- See Sections 3.1 and 4.1 Input Voltage Range for IN- in Pseudo-Differential Mode IN- VSS-100 VSS+100 mV See Sections 3.1 and 4.1 Leakage Current .001 μA Switch Resistance RSS 1 k Ω See Figure 4-1 Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.

© 2006 Microchip Technology Inc. DS21034D-page 3 MCP3202 Sample Capacitor CSAMPLE pF See Figure 4-1 Digital Input/Output: Data Coding Format Straight Binary High Level Input Voltage VIH

0.7 VDD

V Low Level Input Voltage VIL

0.3 VDD

V High Level Output Voltage VOH 4.1 V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 µA VIN = VSS or VDD Output Leakage Current ILO -10 µA VOUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN, COUT pF VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters: Clock Frequency fCLK 1.8 0.9 MHz MHz VDD = 5V (Note 2) VDD = 2.7V (Note 2) Clock High Time tHI 250 ns Clock Low Time tLO 250 ns CS Fall To First Rising CLK Edge tSUCS 100 ns Data Input Setup Time tSU ns Data Input Hold Time tHD ns CLK Fall To Output Data Valid tDO 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable tEN 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable tDIS 100 ns See Test Circuits, Figure 1-2 Note 1 CS Disable Time tCSH 500 ns DOUT Rise Time tR 100 ns See Test Circuits, Figure 1-2 Note 1 DOUT Fall Time tF 100 ns See Test Circuits, Figure 1-2 Note 1 Power Requirements: Operating Voltage VDD 2.7 5.5 V Operating Current IDD 375 550 µA VDD = 5.0V, DOUT unloaded Standby Current IDDS 0.5 µA CS = VDD = 5.0V Temperature Ranges: Specified Temperature Range TA -40 +85 Operating Temperature Range TA -40 +85 Storage Temperature Range TA -65 +150 Thermal Package Resistance: Thermal Resistance, 8L-PDIP θJA °C/W Thermal Resistance, 8L-SOIC θJA 163 °C/W Thermal Resistance, 8L-MSOP θJA 206 °C/W Thermal Resistance, 8L-TSSOP θJA °C/W ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE unless otherwise noted. Parameter Sym Min. Typ. Max. Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.

© 2006 Microchip Technology Inc. DS21034D-page 11 MCP3202 3.0 PIN DESCRIPTIONS 3.1 CH0/CH1 Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two indepen- dent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 for information on programming the channel configuration. 3.2 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conver- sion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.3 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 3.4 Serial Data Input (DIN) The SPI port serial data input pin is used to clock in input channel configuration data. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 4.0 DEVICE OPERATION The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the con- verter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3202. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface. 4.1 Analog Inputs The MCP3202 device offers the choice of using the analog input channels configured as two single-ended inputs or a single pseudo-differential input. Configura- tion is done as part of the serial command before each conversion begins. When used in the pseudo-differen- tial mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmit- ted to the device. The IN+ input can range from IN- to VREF (VDD + IN-). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) imped- ance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and inte- gral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational ampli- fier such as the MCP601 which has a closed loop out- put impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] – 1 LSB}, then the out- put code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VDD level. 4.2 Digital Output Code The digital output code produced by an A/D Converter is a function of the input signal and the reference volt- age. For the MCP3202, VDD is used as the reference voltage. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. where: VIN = analog input voltage VDD = supply voltage Digital Output Code 4096•VIN VDD

© 2006 Microchip Technology Inc. DS21034D-page 13 MCP3202 5.0 SERIAL COMMUNICATIONS 5.1 Overview Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel config- uration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmit- ted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device con- tinues to receive clocks while the CS is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are pro- vided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3202 devices with hardware SPI ports. FIGURE 5-1: Communication with the MCP3202 using MSB first format only. Config Bits Channel Selection GND Sgl/ Diff Odd/ sign Single Ended Mode Pseudo- DifferentiaL Mode IN+ IN- IN- IN+ TABLE 5-1: Configuration Bits for the MCP3202. CS CLK DIN DOUT MS HI-Z Null Bit B11 B10 B9 B4 B3 B1 B0* HI-Z tSAMPLE tCONV SGL/ DIFF Start tCYC tCSH tCYC * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 below for details on obtaining LSB first data. tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. tDATA tSUCS ODD/ SIGN BF Don’t Care SGL/ DIFF Start ODD/ SIGN

© 2006 Microchip Technology Inc. FIGURE 5-2: Communication with MCP3202 using LSB first format. Null Bit B11 B10 B9 B10 B11 CS CLK DOUT HI-Z HI-Z (MSB) tCONV tDATA ** Power Down tSAMPLE DIN tCYC tCSH * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. tSUCS ODD/ SIGN Start SGL/ DIFF MSBF Don’t Care

© 2006 Microchip Technology Inc. DS21034D-page 17 MCP3202 7.0 PACKAGING INFORMATION 7.1 Package Marking Information XXXXXXXX XXXXXNNN YYWW 8-Lead PDIP (300 mil) Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN 8-Lead TSSOP Example: MCP3202 I/PNNN YYWW MCP3202 ISNYYWW NNN 8-Lead MSOP Example: XXXX YYWW NNN XXXXXX YWWNNN 3202 IYWW NNN 3202I YWWNNN Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e e e e

© 2006 Microchip Technology Inc. 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging B A L p α E eB β c n D Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α Mold Draft Angle Bottom β * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 § Significant Characteristic

© 2006 Microchip Technology Inc. DS21034D-page 19 MCP3202 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Foot Angle φ β Mold Draft Angle Bottom α Mold Draft Angle Top 0.51 0.42 0.33 .020 .017 .013 B Lead Width 0.25 0.23 0.20 .010 .009 .008 c Lead Thickness 0.76 0.62 0.48 .030 .025 .019 L Foot Length 0.51 0.38 0.25 .020 .015 .010 h Chamfer Distance 5.00 4.90 4.80 .197 .193 .189 D Overall Length 3.99 3.91 3.71 .157 .154 .146 Molded Package Width 6.20 6.02 5.79 .244 .237 .228 E Overall Width 0.25 0.18 0.10 .010 .007 .004 Standoff 1.55 1.42 1.32 .061 .056 .052 Molded Package Thickness 1.75 1.55 1.35 .069 .061 .053 A Overall Height 1.27 .050 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units D n p B E h L β c 45° φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 § Significant Characteristic

© 2006 Microchip Technology Inc. 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging L ϕ c A b NOTE 1 e E D N Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width Units Dimension Limits N e A E D L ϕ c b 0.75 0.00 0.40 0.08 0.22

0.65 BSC

0.85

4.90 BSC

3.00 BSC

0.60

0.95 REF

1.10 0.95 0.15 0.80 0.23 0.40 MIN NOM MAX MILLIMETERS Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–111, Sept. 8, 2006

© 2006 Microchip Technology Inc. DS21034D-page 21 MCP3202 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E D e n b c L A ϕ β α MILLIMETERS* MIN NOM MAX 1.20 1.05 0.15 4.50 3.10 0.75 0.20 0.30 1.00 4.40 3.00 0.60 0.80 0.05 4.30 2.90 0.45 0.09 0.19 INCHES MIN NOM MAX .039 .173 .118 .024 .047 .041 .006 .177 .122 .030 .008 .012 .031 .002 .169 .114 .018 .004 .007 .026 BSC .252 BSC

6.40 BSC

12° REF 12° REF 12° REF 12° REF Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom *Controlling Parameter Notes: 1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M Drawing No. C04-086 Revised 7-25-06 n e A E D L ϕ c b α β

© 2006 Microchip Technology Inc. NOTES:

© 2001 Microchip Technology Inc. DS21034C-page23 MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Package Performance Grade Device Device: MCP3202: 12-Bit Serial A/d Converter MCP3202T: 12-Bit Serial A/D Converter (Tape and Reel) (SOIC, MSOP and TSSOP package only) Performance Grade: B = ±1 LSB INL (TSSOP not available) C = ±2 LSB INL Temperature Range: I = -40°C to +85°C Package: MS = Plastic Micro Small Outline (MSOP), 8-Lead P = Plastic DIP (300 mil Body), 8-Lead SN = Plastic SOIC (150 mil Body), 8-Lead ST = TSSOP (4.4 mm Body), 8-Lead (C Grade only) Examples: MCP3202-I/MS: = Industrial temperature, MSOP package. MCP3202-BI/P: = B Performance grade, industrial temp., PDIP package MCP3202-CI/SN: = C Performance grade, industrial temp., SOIC package MCP3202T-BI/SN: = Tape and Reel, B Per- formance grade, industrial temp., SOIC package MCP3202T-CI/ST: = Tape and Reel, C Per- formance grade, industrial temp., TSSOP package. X Temperature Range

© 2001 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21034D-page 25 MCP3202 APPENDIX A:

REVISION HISTORY

Revision D (December 2006) This revision includes updates to the packaging dia- grams.

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21034D-page 27 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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