Interface

MCP3202

Microchip Technology

2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface 2008

Manufacturer: Microchip Technology

Document: 32 Pages / 606Kb

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MCP3202_08 MICROCHIP | Alldatasheet

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PDF pages: 32

Technical content

Features

12-Bit resolution
±1 LSB maximum DNL
±1 LSB maximum INL (MCP3202-B)
±2 LSB maximum INL (MCP3202-C)
Analog inputs programmable as single-ended or pseudo-differential pairs
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V-5.5V
100 ksps maximum sampling rate at V DD =5 V
50 ksps maximum sampling rate at V DD =2 . 7 V
Low power CMOS technology
500 nA typical standby current, 5 µA maximum
550 µA maximum active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP , PDIP, SOIC and TSSOP packages

Applications

Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems Functional Block Diagram

Description

The Microchip Technology Inc. MCP3202 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudo-differential input pair or dual single- ended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100 ksps at 5V and 50 ksps at 2.7V. The MCP3202 devic e operates over a broad voltage range (2.7V - 5.5V). Low-current design permits operation with typical standby and active currents of only 500 nA and 375 µA, respectively. The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Package Types Comparator Sample and Hold 12-Bit SAR DAC Control Logic CS/SHDN VSSVDD CLK DOUT Shift Register CH0 Channel Mux Input CH1 DIN MCP32021 CH0 CH1 VSS CS/SHDN VDD/VREF CLK DOUT DIN PDIP, MSOP , SOIC, TSSOP 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface

1.0 ELECTRICAL

Absolute Maximum Ratings † Maximum Junction Temperature (T † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE. Parameter Sym Min. Typ. Max. Units Conditions Conversion Rate: Conversion Time t CONV — — 12 clock cycles Analog Input Sample Time t SAMPLE 1.5 clock cycles Throughput Rate f SAMPL — 100 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy: Resolution 12 bits Integral Nonlinearity INL — ±0.75 LSB LSB MCP3202-B MCP3202-C Differential Nonlinearity DNL — ±0.5 ±1 LSB No missing codes over temperature Offset Error — ±1.25 ±3 LSB Gain Error — ±1.25 ±5 LSB Dynamic Performance: Total Harmonic Distortion THD — -82 — dB V IN = 0.1V to 4.9V@1 kHz Signal-to-Noise and Distortion (SINAD) SINAD — 72 — dB V IN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range SFDR — 86 — dB V IN = 0.1V to 4.9V@1 kHz Analog Inputs: Input Voltage Range for CH0 or CH1 in Single-Ended Mode V SS —V DD V Input Voltage Range for IN+ in Pseudo-Differential Mode IN+ IN- — V DD+IN- See Sections 3.1 and 4.1 Input Voltage Range for IN- in Pseudo-Differential Mode IN- V SS-100 — V SS+100 mV See Sections 3.1 and 4.1 Leakage Current — .001 ±1 μA Switch Resistance R SS —1 k— Ω See Figure 4-1 Sample Capacitor C SAMPLE — 20 — pF See Figure 4-1 Digital Input/Output: Data Coding Format Straight Binary High Level Input Voltage V IH 0.7 VDD —— V Low Level Input Voltage V IL — — 0.3 V DD V Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

DS21034E-page 4 © 2008 Microchip Technology Inc. TEMPERATURE CHARACTERISTICS High Level Output Voltage V OH 4.1 — — V I OH = -1 mA, VDD = 4.5V Low Level Output Voltage V OL ——0 . 4 V I OL = 1 mA, VDD = 4.5V Input Leakage Current I LI -10 — 10 µA V IN = VSS or VDD Output Leakage Current I LO -10 — 10 µA V OUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN, COUT — — 10 pF V DD = 5.0V (Note 1) TA = +25°C, f = 1 MHz Timing Parameters: Clock Frequency f CLK ——1 . 8 0.9 MHz MHz VDD = 5V (Note 2) VDD = 2.7V (Note 2) Clock High Time t HI —2M H z Clock Low Time t LO —2M H z CS Fall To First Rising CLK Edge tSUCS 100 — — ns Data Input Setup Time t SU 50 — — ns Data Input Hold Time t HD 50 — — ns CLK Fall To Output Data Valid t DO — — 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable t EN — — 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable t DIS — — 100 ns See Test Circuits, Figure 1-2 Note 1 CS Disable Time t CSH 500 — — ns DOUT Rise Time t R — — 100 ns See Test Circuits, Figure 1-2 Note 1 DOUT Fall Time t F — — 100 ns See Test Circuits, Figure 1-2 Note 1 Power Requirements: Operating Voltage V DD 2.7 — 5.5 V Operating Current I DD — 375 550 µA V DD = 5.0V, DOUT unloaded Standby Current I DDS —0 . 5 5 µ A C S = VDD = 5.0V Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS =G N D . Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T A -40 — +85 °C Operating Temperature Range T A -40 — +85 °C Storage Temperature Range T A -65 — +150 °C Thermal Package Resistances Thermal Resistance, 8L-MSOP θJA —2 1 1 — ° C / W Thermal Resistance, 8L-PDIP θJA — 89.5 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 8L-TSSOP θJA —1 3 9 — ° C / W ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE. Parameter Sym Min. Typ. Max. Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

2.0 TYPICAL PERFORMA NCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). Note: The graphs provided following this note are a statisti cal summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 Sample Rate (ksps) INL (LSB) Positiv e INL Negativ e INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 VDD(V) INL (LSB) Positive INL Negative INL fSAMPLE = 100 ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 20 40 60 80 100 Sample Rate (ksps) INL (LSB) VDD = 2.7V Positive INL Negative INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 VDD(V) INL (LSB) Positive INL Negative INL fSAMPLE = 50 ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) VDD = 2.7V FSAMPLE = 50 ksps

3.0 PIN DESCRIPTIONS

The descriptions of t he pins are listed in Table 3.1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Inputs (CH0/CH1)

Analog inputs for channels 0 and 1 respectively. These channels can be programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN–. See Section 5.0 “Serial Communications” for information on programming the channel configuration.

3.2 Chip Select/Shutdown (CS /SHDN)

The CS /SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS /SHDN pin must be pulled high between conversions.

3.3 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 “Maintaining Minimum Clock Speed” for constraints on clock speed.

3.4 Serial Data Input (D IN)

The SPI port serial data input pin is used to clock in input channel configuration data.

3.5 Serial Data Output (D OUT)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. MCP3202 Symbol DescriptionMSOP , PDIP, SOIC, TSSOP 1C S /SHDN Chip Select/Shutdown Input

2 CH0 Channel 0 Analog Input

3 CH1 Channel 1 Analog Input

7 CLK Serial Clock

DD/VREF +2.7V to 5.5V Power Supply and Reference Voltage Input

4.0 DEVICE OPERATION

The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3202. See Section 6.2 “Maintaining Minimum Clock Speed” for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3202 device offers the choice of using the analog input channels configured as two single- ended inputs or a single pseudo-differential input. Configuration is done as pa rt of the serial command before each conversion begins. When used in the pseudo-differential mode, CH0 and CH1 are programmed as the IN+ and IN– inputs as part of the command string transmitted to the device. The IN+ input can range from IN– to V REF (VDD + IN–). The IN– input is limited to ±100 mV from the V SS rail. The IN– input can be used to cancel small signal com- mon-mode noise which is present on both the IN+ and IN– inputs. For the A/D Converter to meet specification, the charge holding capacitor (C SAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (R SS) impedance, directly affecting the time that is required to charge the capacitor, C SAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN–, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[V DD + (IN–)] – 1 LSB}, then the output code will be FFFh. If the voltage level at IN– is more than 1 LSB below V SS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VDD level.

4.2 Digital Output Code

The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3202, V DD is used as the reference voltage. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. EQUATION 4-1: Digital Output Code 4096•VIN VDD where: VIN = analog input voltage VDD = supply voltage

0.1 LSB deviation in INL from nominal

conditions. CPINVA RSS CHx 7p F VT = 0.6V VT= 0.6V ILEAKAGE Sampling Switch SS RS = 1 kW CSAMPLE = DAC capacitance VSS VDD = 20 pF±1 nA Legend VA = signal source RSS = source impedance CHx = input channel pad CPIN = input pin capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions SS = sampling switch RS = sampling switch resistor CSAMPLE = sample/hold capacitance 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 100 1000 10000 Input Resistance (Ohms) Clock Frequency (MHz) VDD = 5V VDD = 2.7V

5.0 SERIAL COMMUNICATIONS

5.1 Overview

Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate commu nication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the resu lt of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receiv e clocks while the CS is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 “Using the MCP3202 with Microcon- troller (MCU) SPI Ports” for more details on using the MCP3202 devices with hardware SPI ports. FIGURE 5-1: Communication with the MCP3202 using MSB first format only. TABLE 5-1: CONFIGURATION BITS FOR THE MCP3202 Config Bits Channel Selection GND SGL/ DIFF ODD/ SIGN 01 Single Ended Mode 10+ —- 11 — +- Pseudo- Differential Mode

00 I N + I N -

01 I N - I N +

Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* HI-Z tSAMPLE tCONV SGL/ DIFF Start tCYC tCSH tCYC * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 below for details on obtaining LSB first data. tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros. tDATA tSUCS ODD/ SIGN BF Don’t Care SGL/ DIFF Start ODD/ SIGN

DS21034E-page 18 © 2008 Microchip Technology Inc. FIGURE 5-2: Communication with MCP3202 using LSB first format. Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 CS CLK DOUT HI-Z HI-Z (MSB) tCONV tDATA ** Power Down tSAMPLE DIN tCYC tCSH * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparat or power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. tSUCS ODD/ SIGN Start SGL/ DIFF MSBF Don’t Care

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3202 with

Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are ac tually required. This is usually done by sending ‘leading zeros’ before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3202 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCU receive buffer will contain three unknown bits (the output is at high-impedan ce until the null bit is clocked out), the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). 12345678 9 1 0 1 1 1 2 1 3 1 4 1 5 16 CS SCLK DIN X = Don’t Care Bits 17 18 19 20 21 22 23 24 DOUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z MCU latches data from A/D Converter Data is clocked out of A/D Converter on falling edges on rising edges of SCLK MSBF Don’t Care ODD/ SIGN Start XXXXX XX XXX XXXXXXXX B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B80X X X X X X X X X X X Start Bit (Null) MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) MSBF SGL/ DIFF XX SGL/ DIFF ODD/ SIGN Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits 1234 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 16 CS SCLK DIN X = Don’t Care Bits 17 18 19 20 21 22 23 24 DOUT Don’t Care NULL BIT B11 B10 B9 B8 B6 B5 B4 B3 B2 B1 B0HI-Z 00000 0 XX XXX XXXXX XXX B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B80XXXXXXXX XXX MCU latches data from A/D Converter on rising edges of SCLK Data is clocked out of A/D Converter on falling edges Start Bit (Null) Start MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) SGL/ DIFF MSBF ODD/ SIGN

0 SGL/

Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits

6.2 Maintaining Minimum Clock Speed

When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (e ffective clock frequency of 10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.

6.3 Buffering/Filtering the Analog

If the signal source for the A/D Converter is not a low- impedance source, it will have to be buffered or inaccurate conversion result s may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive the analog input of the MCP3202. This amplifier provides a low-impedance output for the converter input and a low-pass filter, which eliminates unwanted high frequency noise. Low-pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab ® software. FilterLab will calculate capacitor and resistor values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 “Anti-Aliasing Analog Filters for Data Acquisition Systems”. FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3202.

6.4 Layout Considerations

When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 “Layout Tips for 12-Bit A/D Converter FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. MCP3202 VDD 10 µF IN- IN+ +VIN 0.1 µFMCP601R1 VDD Connection Device 1 Device 2 Device 3 Device 4

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

8-Lead PDIP (300 mil) Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN 8-Lead TSSOP Example: 3202-B I/P^^256 0817 3202-BI SN^^ 0817 256 8-Lead MSOP Example: XXXX YYWW NNN XXXXXX YWWNNN 202C I817 256 3202CI 817256 Legend: XX...X Customer-speci fic information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information.

© 2008 Microchip Technology Inc. DS21034E-page 27 MCP3202 APPENDIX A: REVISION HISTORY Revision E (December 2008) The following is the list of modifications: 1. Updates to packaging outline drawings. Revision D (December 2006) The following is the list of modifications: 1. Updates to packaging outline drawings. Revision C (August 2001) The following is the list of modifications: 1. Undocumented changes. Revision B (June 2000) The following is the list of modifications: 1. Undocumented changes. Revision A (August 1999)

Initial release of this document.

© 2008 Microchip Technology Inc. DS21034E-page 29 MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTemperature Range Device Device MCP3202: 12-Bit Serial A/d Converter MCP3202T: 12-Bit Serial A/D Converter (Tape and Reel) (MSOP, SOIC and TSSOP package only) Performance Grade: B = ±1 LSB INL (TSSOP not available) C= ± 2 L S B I N L Temperature Range I = -40 °C to +85 °C (Industrial) E= - 4 0 °C to +125 °C (Extended) Package MS = Plastic Micro Small Outline (MSOP), 8-Lead P = Plastic DIP (300 mil Body), 8-Lead SN = Plastic SOIC (150 mil Body), 8-Lead ST = TSSOP (4.4 mm Body), 8-Lead (C Grade only) Examples: a) MCP3202-CI/MS: Industrial temperature, 8LD MSOP package. b) MCP3202-BI/P: B Performance grade, Industrial temperature, 8LD PDIP package c) MCP3202-BI/SN: C Performance grade, Industrial temperature, 8LD SOIC package d) MCP3202T-BI/SN: Tape and Reel, B Performance grade, Industrial temperature., 8LD SOIC package e) MCP3202T-CI/ST: Tape and Reel, C Performance grade, Industrial temperature, 8LD TSSOP package. Performance Grade

© 2008 Microchip Technology Inc. DS21034E-page 31 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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Product Information

MCP3202 specifications and overview.

Summary

2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface 2008

Description

2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface 2008

Source title MCP3202 Datasheet(PDF) - Microchip Technology

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