MCP3201

MCP3201 MICROCHIP | Alldatasheet

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Technical content

 1999 Microchip Technology Inc. Preliminary DS21290B-page 1 MCP3201

FEATURES

• 12-bit resolution
• ±1 LSB max DNL
• ±1 LSB max INL (MCP3201-B)
• ±2 LSB max INL (MCP3201-C)
• On-chip sample and hold
• SPI ® serial interface (modes 0,0 and 1,1)
• Single supply operation: 2.7V - 5.5V
• 100ksps max. sampling rate at V DD = 5V
• 50ksps max. sampling rate at VDD = 2.7V
• Low power CMOS technology - 500nA typical standby current, 2µA max. - 400µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin PDIP , SOIC and TSSOP packages

APPLICATIONS

• Sensor Interface
• Process Control
• Data Acquisition
• Battery Operated Systems

DESCRIPTION

The Microchip Technology Inc. MCP3201 is a succes- sive approximation 12-bit Analog-to-Digital (A/D) Con- verter with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Dif- ferential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 100ksps at a clock rate of 1.6MHz. The MCP3201 operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active cur- rents of only 500nA and 300µA, respectively. The device is offered in 8-pin PDIP , TSSOP and 150mil SOIC packages. PACKAGE TYPES FUNCTIONAL BLOCK DIAGRAM VREF IN+ IN– VSS VDD CLK D OUT CS /SHDN PDIP SOIC, TSSOP MCP3201 VREF IN+ IN– VSS VDD CLK D OUT CS /SHDN MCP3201 Comparator Sample and Hold 12-Bit SAR DAC Control Logic CS /SHDN VREF IN+ IN- VSSVDD CLK D OUT Shift Register 2.7V 12-Bit A/D Converter with SPI® Serial Interface

DS21290B-page 2 Preliminary  1999 Microchip Technology Inc.

1.0 ELECTRICAL

1.1 Maximum Ratings*

Soldering temperature of leads (10 seconds) ..+300°C *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. PIN FUNCTION TABLE NAME FUNCTION VDD VSS IN+ IN- CLK D OUT CS /SHDN VREF +2.7V to 5.5V Power Supply Ground Positive Analog Input Negative Analog Input Serial Clock Serial Data Out Chip select/Shutdown Input Reference Voltage Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 16*fSAMPLE unless otherwise noted. PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS Conversion Rate Conversion Time t CONV 12 clock cycles Analog Input Sample Time t SAMPLE 1.5 clock cycles Throughput Rate f SAMPLE 100 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution 12 bits Integral Nonlinearity INL ±0.75 LSB LSB MCP3201-B MCP3201-C Differential Nonlinearity DNL ±0.5 ±1 LSB No missing codes over tem- perature Offset Error ±1.25 ±3 LSB Gain Error ±1.25 ±5 LSB Dynamic Performance Total Harmonic Distortion -82 dB V IN = 0.1V to 4.9V@1kHz Signal to Noise and Distortion (SINAD) 72 dB V IN = 0.1V to 4.9V@1kHz Spurious Free Dynamic Range 86 dB V IN = 0.1V to 4.9V@1kHz Reference Input Voltage Range 0.25 V DD VN o t e 2 Current Drain 100 .001 150 µA µA CS = VDD = 5V Analog Inputs Input Voltage Range (IN+) IN- V REF +IN- V Input Voltage Range (IN-) V SS -100 V SS +100 mV Leakage Current 0.001 ±1 µA Switch Resistance R SS 1K Ω See Figure 4-1 Sample Capacitor C SAMPLE 20 pF See Figure 4-1

 1999 Microchip Technology Inc. Preliminary DS21290B-page 3 MCP3201 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V IH 0.7 VDD V Low Level Input Voltage V IL 0.3 VDD V High Level Output Voltage V OH 4.1 V I OH = -1mA, VDD = 4.5V Low Level Output Voltage V OL 0.4 V I OL = 1mA, VDD = 4.5V Input Leakage Current I LI -10 10 µA V IN = VSS or VDD Output Leakage Current I LO -10 10 µA V OUT = VSS or VDD Pin Capacitance (all inputs/outputs) C IN, COUT 10 pF V DD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters Clock Frequency f CLK 1.6 0.8 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time t HI 312 ns Clock Low Time t LO 312 ns CS Fall To First Rising CLK Edge tSUCS 100 ns CLK Fall To Output Data Valid tDO 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable t EN 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable t DIS 100 ns See Test Circuits, Figure 1-2 (Note 1) CS Disable Time t CSH 625 ns D OUT Rise Time t R 100 ns See Test Circuits, Figure 1-2 (Note 1) D OUT Fall Time t F 100 ns See Test Circuits, Figure 1-2 (Note 1) Power Requirements Operating Voltage V DD 2.7 5.5 V Operating Current IDD 300 210 400 µA µA VDD = 5.0V , DOUT unloaded VDD = 2.7V , DOUT unloaded Standby Current I DDS 0.5 2 µA CS = VDD = 5.0V Note 1:This parameter is guaranteed by characterization and not 100% tested. 2: See graph that relates linearity performance to VREF level. 3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information. ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps and fCLK = 16*fSAMPLE unless otherwise noted. PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITIONS

 1999 Microchip Technology Inc. Preliminary DS21290B-page 5 MCP3201

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V , VSS = 0V , fSAMPLE = 100ksps, fCLK = 16*fSAMPLE ,TA = 25°C FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF . FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 Sample Rate (ksps) INL (LSB) Positive INL Negative INL -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 012345 VREF (V) INL (LSB) Positive INL Negative INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 2 04 06 08 0 1 0 0 Sample Rate (ksps) INL (LSB) V DD = VREF = 2.7V Positive INL Negative INL -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 VREF (V) INL (LSB) Positive INL Negative INL VDD = 2.7V FSAMPLE = 50ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code INL (LSB) VDD = VREF = 2.7V FSAMPLE = 50ksps

DS21290B-page 12 Preliminary  1999 Microchip Technology Inc.

3.0 PIN DESCRIPTIONS

3.1 IN+

Positive analog input. This input can vary from IN- to VREF + IN-.

3.2 IN-

Negative analog input. This input can vary ±100mV from VSS .

3.3 CS /SHDN(Chip Select/Shutdown)

The CS /SHDN pin is used to initiate communication with the device when pulled low and will end a conver- sion and put the device in low power standby when pulled high. The CS /SHDN pin must be pulled high between conversions.

3.4 CLK (Serial Clock)

The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.

3.5 D OUT (Serial Data output)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.

4.0 DEVICE OPERATION

The MCP3201 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the inter- nal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3201. See Section 6.2 for informa- tion on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3201 provides a single pseudo-differential input. The IN+ input can range from IN- to VREF (VREF +IN-). The IN- input is limited to ±100mV from the VSS rail. The IN- input can be used to cancel small sig- nal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE ) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance S) adds to the internal sampling switch (RSS ) imped- ance, directly affecting the time that is required to charge the capacitor (CSAMPLE ). Consequently, a larger source impedance increases the offset, gain, and inte- gral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational ampli- fier such as the MCP601, which has a closed loop out- put impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. If the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[V REF + (IN-)] - 1 LSB}, then the out- put code will be FFFh. If the voltage level at IN- is more than 1 LSB below V SS , then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above Vss, then the FFFh code will not be seen unless the IN+ input level goes above V REF level.

4.2 R eference Input

The reference input (VREF ) determines the analog input voltage range and the LSB size, as shown below. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the ana- log input signal and the reference input as shown below. where: VIN = analog input voltage = V(IN+) - V(IN-) VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- ity in the operation of the reference device will have a direct effect on the operation of the A/D Converter. LSB Size = VREF 4096 Digital Output Code = 4096 * VIN VREF

DS21290B-page 14 Preliminary  1999 Microchip Technology Inc.

5.0 SERIAL COMMUNICATIONS

Communication with the device is done using a stan- dard SPI-compatible serial interface. Initiating commu- nication with the MCP3201 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate commu- nication. The device will begin to sample the analog input on the first rising edge after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 12 clocks will output the result of the conver- sion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are pro- vided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. FIGURE 5-1: Communication with MCP3201 using MSB first Format. FIGURE 5-2: Communication with MCP3201 using LSB first Format. CS CLK D OUT tCYC Power DowntSUCS tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure below. ** tDATA : during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. tCSH NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 *HI-Z HI-Z NULL BIT B11 B10 B9 B8 CS CLK D OUT tCYC Power DowntSUCS tSAMPLE tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA : during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. tCSH NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 HI-Z B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z

 1999 Microchip Technology Inc. Preliminary DS21290B-page 15 MCP3201

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3201 with

With most microcontroller SPI ports, it is required to clock out eight bits at a time. If this is the case, it will be necessary to provide more clocks than are required for the MCP3201. As an example, Figure 6-1 and Figure 6-2 show how the MCP3201 can be interfaced to a microcontroller with a standard SPI port. Since the MCP3201 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3201. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the ‘low’ state. As shown in the diagram, the MSB is clocked out of the A/D Converter on the falling edge of the third clock pulse. After the first eight clocks have been sent to the device, the micro- controller’s receive buffer will contain two unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order five bits of the conver- sion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest order seven bits and the B1 bit repeated as the A/D Converter has begun to shift out LSB first data with the extra clock. Typical procedure would then call for the lower order byte of data to be shifted right by one bit to remove the extra B1 bit. The B7 bit is then trans- ferred from the high order byte to the lower order byte, and then the higher order byte is shifted one bit to the right as well. Easier manipulation of the converted data can be obtained by using this method. Figure 6-2 shows the same thing in SPI Mode 1,1 which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). CS CLK 91 0 1 1 1 2 1 3 1 4 1 5 16 D OUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8??0 MCU latches data from A/D Converter Data is clocked out of A/D Converter on falling edges on rising edges of SCLK 12345678 HI-ZB1 LSB first data begins to come out Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits CS CLK 9 1 01 1 1 21 3 1 41 5 16 D OUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8??0 MCU latches data from A/D Converter Data is clocked out of A/D Converter on falling edges on rising edges of SCLK 1234 567 8 LSB first data begins to come out HI-Z Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits

DS21290B-page 16 Preliminary  1999 Microchip Technology Inc.

6.2 Maintaining Minimum Clock Speed

When the MCP3201 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2ms (effective clock fre- quency of 10kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.

6.3 Buffering/Filtering the Analog Inputs

If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccu- rate conversion results may occur. See Figure 4-2. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 where an op amp is used to drive the analog input of the MCP3201. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab™ software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 “Anti-Aliasing Analog Filters for Data Acquisition Systems.” FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3201.

6.4 Layout Considerations

When laying out a printed circuit board for use with ana- log components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1µF is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possi- ble from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converter, refer to AN688 “Layout Tips for 12-Bit A/D Converter Applications”. FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. FilterLab is a trademark of Microchip T echnology Inc. in the U.S.A and other countries. All rights reserved. MCP3201 VDD 10µF IN- IN+ VIN C 1 C 2 VREF 4.096V Reference ADI REF198 1µF 1µF 0.1µFTant. 0.1µF MCP601R 1 R 2 R 3 R 4 VDD Connection Device 1 Device 2 Device 3 Device 4

 1999 Microchip Technology Inc. Preliminary DS21290B-page 17 MCP3201 MCP3201 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Package: P = PDIP (8 lead) SN = SOIC (150 mil Body), 8 lead ST = TSSOP , 8 lead (C Grade only) Temperature I= –40°C to +85°C Range: Performance B = ±1 LSB INL (TSSOP not available in this grade) Grade: C=± 2 L S B I N L Device: MCP3201 = 12-Bit Serial A/D Converter MCP3201T = 12-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only) MCP3201 - G T /P Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Y our local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

DS21290B-page 18 Preliminary  1999 Microchip Technology Inc. NOTES:

 1999 Microchip Technology Inc. Preliminary DS21290B-page 19 MCP3201 NOTES:

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip  1999 Microchip Technology Inc. All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper. AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 T echnical Support: 480-786-7627 Web Address: http://www.microchip.com Atlanta Microchip Technology Inc.

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