MCP3201-I/MS | DigiCamel IC Datasheet

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MCP3201_07 MICROCHIP | Alldatasheet

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PDF pages: 28

Technical content

Features

12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3201-B)
±2 LSB max INL (MCP3201-C)
On-chip sample and hold
SPI™ serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at VDD = 5V
50ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology
500 nA typical standby current, 2 µA max.
400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages

Applications

Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems

Description

The Microchip Technology Inc. MCP3201 is a succes- sive approximation 12-bit Analog-to-Digital (A/D) Con- verter with on-board sample and hold circuitry. The device provides a single pseudo-differential input. Dif- ferential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of sample rates of up to 100 ksps at a clock rate of 1.6 MHz. The MCP3201 operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500 nA and 300 µA, respec- tively. The device is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Package Types Functional Block Diagram VREF IN+ IN– VSS VDD CLK DOUT CS/SHDN MSOP, PDIP, SOIC, TSSOP MCP3201 Comparator Sample and Hold 12-Bit SAR DAC Control Logic CS/SHDN VREF IN+ IN- VSS VDD CLK DOUT Shift Register 2.7V 12-Bit A/D Converter with SPI™ Serial Interface

© 2007 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may affect device reliability. PIN FUNCTION TABLE Name Function VDD +2.7V to 5.5V Power Supply VSS Ground IN+ Positive Analog Input IN- Negative Analog Input CLK Serial Clock DOUT Serial Data Out CS/SHDN Chip Select/Shutdown Input VREF Reference Voltage Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE unless otherwise noted. Parameter Sym Min Typ Max Units Conditions Conversion Rate: Conversion Time tCONV clock cycles Analog Input Sample Time tSAMPLE 1.5 clock cycles Throughput Rate fSAMPLE 100 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy: Resolution bits Integral Nonlinearity INL ±0.75 LSB LSB MCP3201-B MCP3201-C Differential Nonlinearity DNL ±0.5 LSB No missing codes over temperature Offset Error ±1.25 LSB Gain Error ±1.25 LSB Dynamic Performance: Total Harmonic Distortion THD -82 dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) SINAD dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range SFDR dB VIN = 0.1V to 4.9V@1 kHz Reference Input: Voltage Range 0.25 VDD V Note 2 Current Drain 100 .001 150 µA µA CS = VDD = 5V Analog Inputs: Input Voltage Range (IN+) IN+ IN- VREF+IN- V Input Voltage Range (IN-) IN- VSS-100 VSS+100 mV Leakage Current 0.001 µA Switch Resistance RSS W See Figure 4-1 Note 1: This parameter is established by characterization and not 100% tested. See graph that relates linearity performance to VREF level. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.

0.7 VDD

V Low Level Input Voltage VIL

0.3 VDD

V High Level Output Voltage VOH 4.1 V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 µA VIN = VSS or VDD Output Leakage Current ILO -10 µA VOUT = VSS or VDD Pin Capacitance (all inputs/outputs) CIN, COUT pF VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters: Clock Frequency fCLK 1.6 0.8 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 312 ns Clock Low Time tLO 312 ns CS Fall To First Rising CLK Edge tSUCS 100 ns CLK Fall To Output Data Valid tDO 200 ns See Test Circuits, Figure 1-2 CLK Fall To Output Enable tEN 200 ns See Test Circuits, Figure 1-2 CS Rise To Output Disable tDIS 100 ns See Test Circuits, Figure 1-2 (Note 1) CS Disable Time tCSH 625 ns DOUT Rise Time tR 100 ns See Test Circuits, Figure 1-2 (Note 1) DOUT Fall Time tF 100 ns See Test Circuits, Figure 1-2 (Note 1) Power Requirements: Operating Voltage VDD 2.7 5.5 V Operating Current IDD 300 210 400 µA µA VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded Standby Current IDDS 0.5 µA CS = VDD = 5.0V Temperature Ranges: Specified Temperature Range TA -40 +85 Operating Temperature Range TA -40 +85 Storage Temperature Range TA -65 +150 Thermal Package Resistance: Thermal Resistance, 8L-PDIP qJA °C/W Thermal Resistance, 8L-SOIC qJA 163 °C/W Thermal Resistance, 8L-MSOP qJA 206 °C/W Thermal Resistance, 8L-TSSOP qJA 124 °C/W ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE unless otherwise noted. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. See graph that relates linearity performance to VREF level. Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.

© 2007 Microchip Technology Inc. 3.0 PIN DESCRIPTIONS 3.1 IN+ Positive analog input. This input can vary from IN- to VREF + IN-. 3.2 IN- Negative analog input. This input can vary ±100 mV from VSS. 3.3 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conver- sion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 4.0 DEVICE OPERATION The MCP3201 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock after CS has been pulled low. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the inter- nal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3201. See Section 6.2 for informa- tion on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface. 4.1 Analog Inputs The MCP3201 provides a single pseudo-differential input. The IN+ input can range from IN- to VREF (VREF +IN-). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small sig- nal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) imped- ance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset, gain, and inte- gral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational ampli- fier such as the MCP601, which has a closed loop out- put impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. If the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the out- put code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above Vss, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. 4.2 Reference Input The reference input (VREF) determines the analog input voltage range and the LSB size, as shown below. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is a function of the ana- log input signal and the reference input as shown below. where: VIN = analog input voltage = V(IN+) - V(IN-) VREF = reference voltage When using an external voltage reference device, the system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- ity in the operation of the reference device will have a direct effect on the operation of the A/D Converter. LSB Size VREF 4096 Digital Output Code 4096*VIN VREF

© 2007 Microchip Technology Inc. DS21290D-page 17 MCP3201 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e XXXXXXXX XXXXXNNN YYWW 8-Lead PDIP (300 mil) Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN 8-Lead TSSOP Example: MCP3201 I/PNNN 0725 MCP3201 ISN 0725 NNN 8-Lead MSOP Example: XXXX YYWW NNN XXXXXX YWWNNN 3201 0725 NNN 3201I 725NNN e e e e

© 2007 Microchip Technology Inc. 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N Pitch e .100 BSC Top to Seating Plane A .210 Molded Package Thickness .115 .130 .195 Base to Seating Plane .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB .430 N NOTE 1 D A L b e E eB c Microchip Technology Drawing C04-018B

© 2007 Microchip Technology Inc. DS21290D-page 19 MCP3201 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

1.27 BSC

A 1.75 Molded Package Thickness 1.25 Standoff § 0.10 0.25 Overall Width E

6.00 BSC

3.90 BSC

D

4.90 BSC

Chamfer (optional) h 0.25 0.50 Foot Length L 0.40 1.27 Footprint

1.04 REF

φ Lead Thickness c 0.17 0.25 Lead Width b 0.31 0.51 Mold Draft Angle Top α 15° Mold Draft Angle Bottom β 15° D N e E NOTE 1 b A L c h h φ β α Microchip Technology Drawing C04-057B

© 2007 Microchip Technology Inc. 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

0.65 BSC

A 1.10 Molded Package Thickness 0.75 0.85 0.95 Standoff 0.00 0.15 Overall Width E

3.00 BSC

D L 0.40 0.60 0.80 Footprint

0.95 REF

φ Lead Thickness c 0.08 0.23 Lead Width b 0.22 0.40 D N E NOTE 1 e b A c L φ Microchip Technology Drawing C04-111B

© 2007 Microchip Technology Inc. DS21290D-page 21 MCP3201 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e A 1.20 Molded Package Thickness 0.80 1.00 1.05 Standoff 0.05 0.15 Overall Width E

6.40 BSC

4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint

1.00 REF

φ Lead Thickness c 0.09 0.20 Lead Width b 0.19 0.30 D N E NOTE 1 b e c A L φ Microchip Technology Drawing C04-086B

REVISION HISTORY

Revision D (January 2007) This revision includes updates to the packaging diagrams.

© 2007 Microchip Technology Inc. DS21290D-page25 MCP3201 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Package Temperature Range Device Device: MCP3201: 12-Bit A/D Converter w/SPI Interface MCP3201T: 12-Bit A/D Converter w/SPI Interface (Tape and Reel) (SOIC and TSSOP only) Temperature Range: I = -40°C to +85°C Package: MS = Plastic Micro Small Outline (MSOP), 8-lead P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead ST = Plastic TSSOP (4.4 mm), 8-lead Examples: MCP3201-I/P: Industrial Temperature, PDIP package. MCP3201-I/SN: Industrial Temperature, SOIC package. MCP3201-I/ST: Industrial Temperature, TSSOP package. MCP3201-I/MS: Industrial Temperature, MSOP package.

© 2007 Microchip Technology Inc. DS21290D-page 27 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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Product Information

MCP3201-I/MS specifications and overview.

Summary

2.7V 12-Bit A/D Converter with SPI Serial Interface 2007

Description

2.7V 12-Bit A/D Converter with SPI Serial Interface 2007

Source title MCP3201-I/MS Datasheet(PDF) - Microchip Technology

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