MCP3004_07 MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

  • 10-bit resolution
  • ± 1 LSB max DNL
  • ± 1 LSB max INL
  • 4 (MCP3004) or 8 (MCP3008) input channels
  • Analog inputs programmable as single-ended or pseudo-differential pairs
  • On-chip sample and hold
  • SPI serial interface (modes 0,0 and 1,1)
  • Single supply operation: 2.7V - 5.5V
  • 200 ksps max. sampling rate at VDD = 5V
  • 75 ksps max. sampling rate at VDD = 2.7V
  • Low power CMOS technology
  • 5 nA typical standby current, 2 µA max.
  • 500 µA max. active current at 5V
  • Industrial temp range: -40°C to +85°C
  • Available in PDIP, SOIC and TSSOP packages

Applications

  • Sensor Interface
  • Process Control
  • Data Acquisition
  • Battery Operated Systems Package Types

Description

Inc. MCP3004/3008 devices are successive approximation 10-bit Analog- to-Digital (A/D) converters with on-board sample and hold circuitry. The MCP3004 is programmable to pro- vide two pseudo-differential input pairs or four single- ended inputs. The MCP3008 is programmable to pro- vide four pseudo-differential input pairs or eight single- ended inputs. Differential Nonlinearity (DNL) and Inte- gral Nonlinearity (INL) are specified at ±1 LSB. Com- munication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 200 ksps. The MCP3004/3008 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby currents of only 5 nA and typical active currents of 320 µA. The MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages, while the MCP3008 is offered in 16- pin PDIP and SOIC packages. Functional Block Diagram VDD CLK DOUT MCP3004 VREF DIN CH0 CH1 CH2 CH3 CS/SHDN DGND AGND NC VDD CLK DOUT MCP3008 VREF DIN CS/SHDN DGND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 NC AGND PDIP, SOIC, TSSOP PDIP, SOIC Comparator Sample and Hold 10-Bit SAR DAC Control Logic CS/SHDN VREF VSS VDD CLK DOUT Shift Register CH0 Channel Max Input CH1 CH7* * Note: Channels 4-7 available on MCP3008 Only DIN 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI™ Serial Interface

© 2007 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings* Soldering temperature of leads (10 seconds) ..+300°C *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TABLE Name Function VDD +2.7V to 5.5V Power Supply DGND Digital Ground AGND Analog Ground CH0-CH7 Analog Inputs CLK Serial Clock DIN Serial Data In DOUT Serial Data Out CS/SHDN Chip Select/Shutdown Input VREF Reference Voltage Input ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25°C. Parameter Sym Min Typ Max Units Conditions Conversion Rate Conversion Time tCONV clock cycles Analog Input Sample Time tSAMPLE 1.5 clock cycles Throughput Rate fSAMPLE 200 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution bits Integral Nonlinearity INL ±0.5 LSB Differential Nonlinearity DNL ±0.25 LSB No missing codes over temperature Offset Error ±1.5 LSB Gain Error ±1.0 LSB Dynamic Performance Total Harmonic Distortion -76 dB VIN = 0.1V to 4.9V@1 kHz Signal to Noise and Distortion (SINAD) dB VIN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range dB VIN = 0.1V to 4.9V@1 kHz Reference Input Voltage Range 0.25 VDD V Note 2 Current Drain 100 0.001 150 µA µA CS = VDD = 5V Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information.

© 2007 Microchip Technology Inc. DS21295C-page 3 MCP3004/3008 Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode VSS VREF V Input Voltage Range for IN+ in pseudo-differential mode IN- VREF+IN- Input Voltage Range for IN- in pseudo-differential mode VSS-100 VSS+100 mV Leakage Current 0.001 µA Switch Resistance 1000 Ω See Figure 4-1 Sample Capacitor pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage VIH

0.7 VDD

V Low Level Input Voltage VIL

0.3 VDD

V High Level Output Voltage VOH 4.1 V IOH = -1 mA, VDD = 4.5V Low Level Output Voltage VOL 0.4 V IOL = 1 mA, VDD = 4.5V Input Leakage Current ILI -10 µA VIN = VSS or VDD Output Leakage Current ILO -10 µA VOUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN, COUT pF VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz Timing Parameters Clock Frequency fCLK 3.6 1.35 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time tHI 125 ns Clock Low Time tLO 125 ns CS Fall To First Rising CLK Edge tSUCS 100 ns CS Fall To Falling CLK Edge tCSD ns Data Input Setup Time tSU ns Data Input Hold Time tHD ns CLK Fall To Output Data Valid tDO 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CLK Fall To Output Enable tEN 125 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CS Rise To Output Disable tDIS 100 ns See Test Circuits, Figure 1-2 CS Disable Time tCSH 270 ns DOUT Rise Time tR 100 ns See Test Circuits, Figure 1-2 (Note 1) DOUT Fall Time tF 100 ns See Test Circuits, Figure 1-2 (Note 1) ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25°C. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information.

© 2007 Microchip Technology Inc. FIGURE 1-1: Serial Interface Timing. Power Requirements Operating Voltage VDD 2.7 5.5 V Operating Current IDD 425 225 550 µA VDD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded Standby Current IDDS 0.005 µA CS = VDD = 5.0V Temperature Ranges Specified Temperature Range TA -40 +85 Operating Temperature Range TA -40 +85 Storage Temperature Range TA -65 +150 Thermal Package Resistance Thermal Resistance, 14L-PDIP θJA °C/W Thermal Resistance, 14L-SOIC θJA 108 °C/W Thermal Resistance, 14L-TSSOP θJA 100 °C/W Thermal Resistance, 16L-PDIP θJA °C/W Thermal Resistance, 16L-SOIC θJA °C/W ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TAMB = 25°C. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information. CS CLK DIN MSB IN TSU THD TSUCS TCSH THI TLO DOUT TEN TDO TR TF LSB MSB OUT TDIS NULL BIT

© 2007 Microchip Technology Inc. DS21295C-page 13 MCP3004/3008 3.0 PIN DESCRIPTIONS TABLE 3-1: PIN FUNCTION TABLE 3.1 DGND Digital ground connection to internal digital circuitry. 3.2 AGND Analog ground connection to internal analog circuitry. 3.3 CH0 - CH7 Analog inputs for channels 0 - 7, respectively, for the multiplexed inputs. Each pair of channels can be pro- grammed to be used as two independent channels in single-ended mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN. See Section 4.1, “Analog Inputs”, and Section 5.0, “Serial Communication”, for information on programming the channel configuration. 3.4 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2, “Maintaining Minimum Clock Speed”, for constraints on clock speed. 3.5 Serial Data Input (DIN) The SPI port serial data input pin is used to load channel configuration data into the device. 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 3.7 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low. When pulled high, it will end a conversion and put the device in low power standby. The CS/SHDN pin must be pulled high between conversions. 4.0 DEVICE OPERATION The MCP3004/3008 A/D converters employ a conven- tional SAR architecture. With this architecture, a sam- ple is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock once CS has been pulled low. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3004/3008. See Section 6.2, “Maintaining Minimum Clock Speed”, for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPI- compatible interface. 4.1 Analog Inputs The MCP3004/3008 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3004 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each con- version begins. When used in the pseudo-differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN-). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common- mode noise, which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, the 3FFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, larger source impedances increase the offset, gain and integral lin- earity errors of the conversion (see Figure 4-2). Name Function VDD +2.7V to 5.5V Power Supply DGND Digital Ground AGND Analog Ground CH0-CH7 Analog Inputs CLK Serial Clock DIN Serial Data In DOUT Serial Data Out CS/SHDN Chip Select/Shutdown Input VREF Reference Voltage Input

© 2007 Microchip Technology Inc. 4.2 Reference Input For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. EQUATION When using an external voltage reference device, the system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- ity in the operation of the reference device will have a direct effect on the operation of the A/D converter. FIGURE 4-1: Analog Input Model. FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a

0.1 LSB deviation in INL from nominal

conditions. LSB Size VREF 1024 Digital Output Code 1024 VIN VREF VIN = analog input voltage VREF = reference voltage CPIN VA RSS CHx 7 pF VT = 0.6V VT = 0.6V ILEAKAGE Sampling Switch SS RS = 1 kΩ CSAMPLE = DAC capacitance VSS VDD = 20 pF ±1 nA Legend VA = Signal Source ILEAKAGE = Leakage Current At The Pin Due To Various Junctions RSS = Source Impedance SS = sampling switch CHx = Input Channel Pad RS = sampling switch resistor CPIN = Input Pin Capacitance CSAMPLE = sample/hold capacitance VT = Threshold Voltage 100 1000 10000 Input Resistance (Ohms) Clock Frequency (Mhz) VDD = VREF = 5 V fSAMPLE = 200 ksps VDD = VREF = 2.7 V fSAMPLE = 75 ksps

© 2007 Microchip Technology Inc. DS21295C-page 15 MCP3004/3008 5.0 SERIAL COMMUNICATION Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3004 and MCP3008, respectively. The device will begin to sample the ana- log input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as is shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1, “Using the MCP3004/3008 with Microcon- troller (MCU) SPI Ports”, for more details on using the MCP3004/3008 devices with hardware SPI ports. TABLE 5-1: CONFIGURE BITS FOR THE MCP3004 TABLE 5-2: CONFIGURE BITS FOR THE MCP3008 Control Bit Selections Input Configuration Channel Selection Single/ Diff D2* X single-ended CH0 X single-ended CH1 X single-ended CH2 X single-ended CH3 X differential CH0 = IN+ CH1 = IN- X differential CH0 = IN- CH1 = IN+ X differential CH2 = IN+ CH3 = IN- X differential CH2 = IN- CH3 = IN+ * D2 is “don’t care” for MCP3004 Control Bit Selections Input Configuration Channel Selection Single /Diff single-ended CH0 single-ended CH1 single-ended CH2 single-ended CH3 single-ended CH4 single-ended CH5 single-ended CH6 single-ended CH7 differential CH0 = IN+ CH1 = IN- differential CH0 = IN- CH1 = IN+ differential CH2 = IN+ CH3 = IN- differential CH2 = IN- CH3 = IN+ differential CH4 = IN+ CH5 = IN- differential CH4 = IN- CH5 = IN+ differential CH6 = IN+ CH7 = IN- differential CH6 = IN- CH7 = IN+

© 2007 Microchip Technology Inc. 6.5 Utilizing the Digital and Analog Ground Pins The MCP3004/3008 devices provide both digital and analog ground connections to provide additional means of noise reduction. As is shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10Ω. If no ground plane is utilized, both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. FIGURE 6-5: Separation of Analog and Digital Ground Pins. MCP3004/08 Analog Ground Plane DGND AGND VDD 0.1 µF Substrate 5 - 10Ω Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator

© 2007 Microchip Technology Inc. DS21295C-page 21 MCP3004/3008 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e 14-Lead PDIP (300 mil) Example: 14-Lead SOIC (150 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXX YYWWNNN MCP3004-I/P 0712027 XXXXXXXXXXX MCP3004ISL 0712027 XXXXXXXXXXX XXXXXXXX NNN YYWW 14-Lead TSSOP (4.4mm) * Example: 3004 027 0712 e e e

© 2007 Microchip Technology Inc. Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3308) Example: 16-Lead SOIC (150 mil) (MCP3308) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX YYWWNNN MCP3008-I/P 0712030 XXXXXXXXXXXXX MCP3008-I/SL 0712030 XXXXXXXXXX e e

© 2007 Microchip Technology Inc. DS21295C-page 23 MCP3004/3008 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N Pitch e .100 BSC Top to Seating Plane A .210 Molded Package Thickness .115 .130 .195 Base to Seating Plane .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB .430 N D NOTE 1 E c eB L A b e Microchip Technology Drawing C04-005B

© 2007 Microchip Technology Inc. 14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

1.27 BSC

A 1.75 Molded Package Thickness 1.25 Standoff § 0.10 0.25 Overall Width E

6.00 BSC

3.90 BSC

D

8.65 BSC

Chamfer (optional) h 0.25 0.50 Foot Length L 0.40 1.27 Footprint

1.04 REF

φ Lead Thickness c 0.17 0.25 Lead Width b 0.31 0.51 Mold Draft Angle Top α 15° Mold Draft Angle Bottom β 15° NOTE 1 N D E b e A L c h h α β φ Microchip Technology Drawing C04-065B

© 2007 Microchip Technology Inc. DS21295C-page 25 MCP3004/3008 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e

0.65 BSC

A 1.20 Molded Package Thickness 0.80 1.00 1.05 Standoff 0.05 0.15 Overall Width E

6.40 BSC

4.30 4.40 4.50 Molded Package Length D 4.90 5.00 5.10 Foot Length L 0.45 0.60 0.75 Footprint

1.00 REF

φ Lead Thickness c 0.09 0.20 Lead Width b 0.19 0.30 NOTE 1 D N E e b c A L φ Microchip Technology Drawing C04-087B

© 2007 Microchip Technology Inc. 16-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N Pitch e .100 BSC Top to Seating Plane A .210 Molded Package Thickness .115 .130 .195 Base to Seating Plane .015 Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width .240 .250 .280 Overall Length D .735 .755 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB .430 N NOTE 1 D A b e L E eB c Microchip Technology Drawing C04-017B

© 2007 Microchip Technology Inc. DS21295C-page 27 MCP3004/3008 16-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLMETERS Dimension Limits MIN NOM MAX Number of Pins N Pitch e A 1.75 Molded Package Thickness 1.25 Standoff § 0.10 0.25 Overall Width E D

9.90 BSC

Chamfer (optional) h 0.25 0.50 Foot Length L 0.40 1.27 Footprint φ Lead Thickness c 0.17 0.25 Lead Width b 0.31 0.51 Mold Draft Angle Top α 15° Mold Draft Angle Bottom β 15° D E N NOTE 1 b e h h c L A β φ α Microchip Technology Drawing C04-108B

© 2007 Microchip Technology Inc. NOTES:

© 2007 Microchip Technology Inc. DS21295C-page 29 MCP3004/3008 APPENDIX A:

REVISION HISTORY

Revision C (January 2007) This revision includes updates to the packaging diagrams.

© 2007 Microchip Technology Inc. NOTES:

© 2007 Microchip Technology Inc. DS21295C-page31 MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: MCP3004: 4-Channel 10-Bit Serial A/D Converter MCP3004T: 4-Channel 10-Bit Serial A/D Converter (Tape and Reel) MCP3008: 8-Channel 10-Bit Serial A/D Converter MCP3008T: 8-Channel 10-Bit Serial A/D Converter (Tape and Reel) Temperature Range: I = -40°C to +85°C Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Examples: MCP3004-I/P: Industrial Temperature, PDIP package. MCP3004-I/SL: Industrial Temperature, SOIC package. MCP3004-I/ST: Industrial Temperature, TSSOP package. MCP3004T-I/ST: Industrial Temperature, TSSOP package, Tape and Reel. MCP3008-I/P: Industrial Temperature, PDIP package. MCP3008-I/SL: Industrial Temperature, SOIC package. PART NO. X /XX Package Temperature Range Device

© 2007 Microchip Technology Inc. NOTES:

© 2007 Microchip Technology Inc. DS21295C-page 33 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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