Interface

MCP3

Microchip Technology

2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface 2008

Manufacturer: Microchip Technology

Document: 40 Pages / 777Kb

Request Quote Download Datasheet Read online HTML view

More from Microchip Technology Browse M parts

Online Datasheet

Read MCP3 online.

MCP3004_08 MICROCHIP | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 40

Technical content

Features

10-bit resolution
± 1 LSB max DNL
± 1 LSB max INL
4 (MCP3004) or 8 (MCP3008) input channels
Analog inputs programmable as single-ended or pseudo-differential pairs
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
200 ksps max. sampling rate at V DD =5 V
75 ksps max. sampling rate at V DD =2 . 7 V
Low power CMOS technology
5 nA typical standby current, 2 µA max.
500 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
Available in PDIP, SOIC and TSSOP packages

Applications

Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems Functional Block Diagram

Description

The Microchip Technology Inc. MCP3004/3008 devices are successive approximation 10-bit Analog- to-Digital (A/D) converters with on-board sample and hold circuitry. The MCP3004 is programmable to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 is programmable to provide four pseudo-differential input pairs or eight single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are specified at ±1 LSB. Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 200 ksps. The MCP3004/3008 devices operate over a broad voltage range (2.7V - 5.5V). Low-current design permits operation with typical standby currents of only 5 nA and typical active currents of 320 µA. The MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages, while the MCP3008 is offered in 16- pin PDIP and SOIC packages. Package Types Comparator Sample and Hold 10-Bit SAR DAC Control Logic CS/SHDN VREF VSSVDD CLK DOUT Shift Register CH0 Channel Max InputCH1 CH7* * Note: Channels 4-7 are available on MCP3008 Only DIN VDD CLK DOUT MCP3004 VREF DIN CH0 CH1 CH2 CH3 CS /SHDNDGND AGND NC VDD CLK DOUT MCP3008 VREF DIN CS/SHDN DGND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 NC AGND PDIP, SOIC, TSSOP PDIP, SOIC 2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

1.0 ELECTRICAL

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25°C. Parameter Sym Min Typ Max Units Conditions Conversion Rate Conversion Time t CONV — — 10 clock cycles Analog Input Sample Time t SAMPLE 1.5 clock cycles Throughput Rate f SAMPLE —— 2 0 0 ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V DC Accuracy Resolution 10 bits Integral Nonlinearity INL — ±0.5 ±1 LSB Differential Nonlinearity DNL — ±0.25 ±1 LSB No missing codes over temperature Offset Error — — ±1.5 LSB Gain Error — — ±1.0 LSB Dynamic Performance Total Harmonic Distortion — -76 dB V IN = 0.1V to 4.9V@1 kHz Signal-to-Noise and Distortion (SINAD) —6 1 d B V IN = 0.1V to 4.9V@1 kHz Spurious Free Dynamic Range — 78 dB V IN = 0.1V to 4.9V@1 kHz Reference Input Voltage Range 0.25 — V DD VN o t e 2 Current Drain — 100 0.001 150 µA µA CS = VDD = 5V Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode VSS —V REF V Input Voltage Range for IN+ in pseudo-differential mode IN- — V REF+IN- Input Voltage Range for IN- in pseudo-differential mode VSS-100 — V SS+100 mV Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information.

DS21295D-page 4 © 2008 Microchip Technology Inc. Leakage Current — 0.001 ±1 µA Switch Resistance — 1000 — Ω See Figure 4-1 Sample Capacitor — 20 — pF See Figure 4-1 Digital Input/Output Data Coding Format Straight Binary High Level Input Voltage V IH 0.7 VDD ——V Low Level Input Voltage V IL — 0.3 V DD V High Level Output Voltage V OH 4.1 — — V I OH = -1 mA, VDD = 4.5V Low Level Output Voltage V OL ——0 . 4V I OL = 1 mA, VDD = 4.5V Input Leakage Current I LI -10 — 10 µA V IN = VSS or VDD Output Leakage Current I LO -10 — 10 µA V OUT = VSS or VDD Pin Capacitance (All Inputs/Outputs) CIN, COUT —— 1 0p F V DD = 5.0V (Note 1) TA = 25°C, f = 1 MHz Timing Parameters Clock Frequency f CLK ——3 . 6 1.35 MHz MHz VDD = 5V (Note 3) VDD = 2.7V (Note 3) Clock High Time t HI 125 — — ns Clock Low Time t LO 125 — — ns CS Fall To First Rising CLK Edge t SUCS 100 — — ns CS Fall To Falling CLK Edge t CSD —— 0 n s Data Input Setup Time t SU 50 — — ns Data Input Hold Time t HD 50 — — ns CLK Fall To Output Data Valid t DO —— 1 2 5 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CLK Fall To Output Enable t EN —— 1 2 5 200 ns ns VDD = 5V, See Figure 1-2 VDD = 2.7V, See Figure 1-2 CS Rise To Output Disable t DIS — — 100 ns See Test Circuits, Figure 1-2 CS Disable Time t CSH 270 — — ns DOUT Rise Time t R — — 100 ns See Test Circuits, Figure 1-2 (Note 1) DOUT Fall Time t F — — 100 ns See Test Circuits, Figure 1-2 (Note 1) ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25°C. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information.

© 2008 Microchip Technology Inc. DS21295D-page 5 MCP3004/3008 TEMPERATURE CHARACTERISTICS FIGURE 1-1: Serial Interface Timing. Power Requirements Operating Voltage V DD 2.7 — 5.5 V Operating Current I DD —4 2 5 225 550 µA V DD = VREF = 5V, DOUT unloaded VDD = VREF = 2.7V, DOUT unloaded Standby Current I DDS —0 . 0 0 5 2 µ A C S = VDD = 5.0V Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS =G N D . Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T A -40 — +85 °C Operating Temperature Range T A -40 — +85 °C Storage Temperature Range T A -65 — +150 °C Thermal Package Resistances Thermal Resistance, 14L-PDIP θJA —7 0 — ° C / W Thermal Resistance, 14L-SOIC θJA —1 0 8 — ° C / W Thermal Resistance, 14L-TSSOP θJA —1 0 0 — ° C / W Thermal Resistance, 16L-PDIP θJA —7 0 — ° C / W Thermal Resistance, 16L-SOIC θJA —9 0 — ° C / W ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for VDD = 5V, TA = +25°C. Parameter Sym Min Typ Max Units Conditions Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for more information. CS CLK DIN MSB IN TSU THD TSUCS TCSH THI TLO DOUT TEN TDO TR TF LSBMSB OUT TDIS NULL BIT

2.0 TYPICAL PERFORMA NCE CHARACTERISTICS

Note: Unless otherwise indicated, V DD = VREF = 5V, fCLK = 18* fSAMPLE, TA = +25°C. FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate. FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 175 200 225 250 Sample Rate (ksps) INL (LSB) Positive INL Negative INL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0123456 VREF (V) INL(LSB) Positive INL Negative INL -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1024 Digital Code INL (LSB) VDD = VREF = 5 V fSAMPLE = 200 ksps -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 02 5 5 0 7 5 1 0 0 Sample Rate (ksps) INL (LSB) Positive INL Negative INL VDD = VREF = 2.7 V -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 VREF (V) INL(LSB) Positive INL Negative INL VDD = VREF = 2.7 V fSAMPLE = 75 ksps -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 128 256 384 512 640 768 896 1024 Digital Code INL (LSB) VDD = VREF = 2.7 V fSAMPLE = 75 ksps

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE

3.1 Digital Ground (DGND)

Digital ground connection to internal digital circuitry.

3.2 Analog Ground (AGND)

Analog ground connection to internal analog circuitry.

3.3 Analog inputs (CH0 - CH7)

Analog inputs for channels 0 - 7, respectively, for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN. See Section 4.1 “Analog Inputs” , “Analog Inputs”, and Section 5.0 “Serial Communication” , “Serial Communication”, for information on programming the channel configuration.

3.4 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2 “Maintaining Minimum Clock Speed”, “Maintaining Minimum Clock Speed”, for constraints on clock speed.

3.5 Serial Data Input (D IN)

The SPI port serial data input pin is used to load channel configuration data into the device.

3.6 Serial Data Output (D OUT)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.

3.7 Chip Select/Shutdown (CS /SHDN)

The CS /SHDN pin is used to initiate communication with the device when pulled low. When pulled high, it will end a conversion and put the device in low-power standby. The CS /SHDN pin must be pulled high between conversions. MCP3004 MCP3008 Symbol DescriptionPDIP , SOIC, TSSOP PDIP, SOIC 1 1 CH0 Analog Input 2 2 CH1 Analog Input 3 3 CH2 Analog Input 4 4 CH3 Analog Input – 5 CH4 Analog Input – 6 CH5 Analog Input – 7 CH6 Analog Input – 8 CH7 Analog Input 7 9 DGND Digital Ground 81 0 C S /SHDN Chip Select/Shutdown Input 91 1 D IN Serial Data In 10 12 D OUT Serial Data Out 11 13 CLK Serial Clock 12 14 AGND Analog Ground 13 15 V REF Reference Voltage Input 14 16 V DD +2.7V to 5.5V Power Supply 5,6 – NC No Connection

4.0 DEVICE OPERATION

The MCP3004/3008 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the first rising edge of the serial clock once CS has been pulled low. Following this sample time, the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3004/3008. See Section 6.2 “Maintaining Mini- mum Clock Speed” , “Maintaining Minimum Clock Speed”, for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3004/3008 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3004 can be configured to provide two pseudo-differential input pairs or four single-ended inputs. The MCP3008 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo- differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) are programmed as the IN+ and IN- inputs as part of the command string transmit- ted to the device. The IN+ input can range from IN- to REF + IN-). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise, which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[V REF + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below V SS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, the 3FFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (C SAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. This diagram illustrates that the source impedance (R adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (C SAMPLE). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2).

4.2 Reference Input

For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION 4-1: LSB SIZE CALCULATION The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. EQUATION 4-2: DIGITAL OUTPUT CODE CALCULATION When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter. LSB Size VREF Digital Output Code 1024 V IN× VREF Where: VIN = analog input voltage VREF = analog input voltage

0.1 LSB deviation in INL from nominal

conditions. CPINVA RSS CHx 7p F VT = 0.6V VT = 0.6V ILEAKAGE Sampling Switch SS RS = 1 kΩ CSAMPLE = DAC capacitance VSS VDD = 20 pF±1 nA Legend VA = Signal Source ILEAKAGE = Leakage Current At The Pin Due To Various Junctions RSS = Source Impedance SS = sampling switch CHx = Input Channel Pad RS = sampling switch resistor CPIN = Input Pin Capacitance CSAMPLE = sample/hold capacitance VT = Threshold Voltage 100 1000 10000 Input Resistance (Ohms) Clock Frequency (Mhz) VDD = VREF = 5 V fSAMPLE = 200 ksps VDD = VREF = 2.7 V fSAMPLE = 75 ksps

5.0 SERIAL COMMUNICATION

Communication with the MCP3004/3008 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and D IN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3004 and MCP3008, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 10 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as is shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 “Using the MCP3004/3008 with Micro- controller (MCU) SPI Ports” , “Using the MCP3004/ 3008 with Microcontroller (MCU) SPI Ports”, for more details on using the MCP3004/3008 devices with hardware SPI ports. TABLE 5-1: CONFIGURE BITS FOR THE MCP3004 TABLE 5-2: CONFIGURE BITS FOR THE MCP3008 Control Bit Selections Input Configuration Channel SelectionSingle/ Diff D2* D1 D0

1 X 0 0 single-ended CH0

1 X 0 1 single-ended CH1

1 X 1 0 single-ended CH2

1 X 1 1 single-ended CH3

0 X 0 0 differential CH0 = IN+

CH1 = IN-

0 X 0 1 differential CH0 = IN-

CH1 = IN+

0 X 1 0 differential CH2 = IN+

CH3 = IN-

0 X 1 1 differential CH2 = IN-

CH3 = IN+ * D2 is “don’t care” for MCP3004 Control Bit Selections Input Configuration Channel SelectionSingle /Diff D2 D1 D0 1 0 0 0 single-ended CH0 1 0 0 1 single-ended CH1 1 0 1 0 single-ended CH2 1 0 1 1 single-ended CH3 1 1 0 0 single-ended CH4 1 1 0 1 single-ended CH5 1 1 1 0 single-ended CH6 1 1 1 1 single-ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3004/3008 with

Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3004/3008 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure 6-1 and Figure 6-2 shows how the MCP3004/ 3008 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the sim- ilar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains seven leading zeros before the start bit. Arranging the leading zeros this way induces the 10 data bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 14. Once the second eight clocks have been sent to the device, the MCU receive buffer will contain five unknown bits (the output is at high-impedance for the first two clocks), the null bit and the highest order 2 bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D c onverter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock. FIGURE 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low). 12345678 9 10 11 12 13 14 15 16 CS SCLK DIN X = “Don’t Care” Bits 17 18 19 20 21 22 23 24 DOUT NULL BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z MCU latches data from A/D Data is clocked out of A/D converter on falling edges converter on rising edges of SCLK Don’t CareSGL/ DIFF D1D2Start 00000 1 XXX XDO XXXXXXXX D1D2SGL/ DIFF Start Bit (Null) MCU Transmitted Data (Aligned with falling edge of clock) Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits DO MCU Received Data (Aligned with rising edge of clock)

6.2 Maintaining Minimum Clock Speed

When the MCP3004/3008 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is rece ived. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 10 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.

6.3 Buffering/Filtering the Analog

If the signal source for the A/D converter is not a low- impedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 4- 2). It is also recommende d that a filter be used to eliminate any signals that may be aliased back in to the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive, filter and gain the analog input of the MCP3004/3008. Th is amplifier provides a low-impedance source for the converter input, plus a low-pass filter, which eliminates unwanted high- frequency noise. Low-pass (anti-aliasing) filt ers can be designed using Microchip’s free interactive FilterLab ® software. FilterLab will calculate capacitor and resistors values, as well as determine the number of poles that are required for the application. For more information on fil- tering signals, see AN699, “Anti-Aliasing Analog Filters for Data Acquisition Systems”. FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3004. 1234567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 16 CS SCLK DIN X = “Don’t Care” Bits 17 18 19 20 21 22 23 24 DOUT DO Don’t Care NULL BIT B9 B8 B6 B5 B4 B3 B2 B1 B0HI-Z 00000 1 XXX XDO SGL/ DIFF XXXXXXXX MCU latches data from A/D converter on rising edges of SCLK Data is clocked out of A/D converter on falling edges D1D2SGL/ DIFF Start Bit (Null) D1D2Start MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits MCP3004 VDD 10 µF IN- IN+ +VIN VREF 4.096V Reference 1µ F 1µ F0.1 µF MCP601R1 MCP1541

6.4 Layout Considerations

When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or bypass capacitor. Extra precautions should be taken to keep traces with high- frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a “star” configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, “Layout Tips for 12-Bit A/D Converter Applications”. FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.

6.5 Utilizing the Digital and Analog

The MCP3004/3008 devices provide both digital and analog ground connections to provide additional means of noise reduction. As is shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10Ω. If no ground plane is utilized, both grounds must be connected to V SS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. FIGURE 6-5: Separation of Analog and Digital Ground Pins. VDD Connection Device 1 Device 2 Device 3 Device 4 MCP3004/08 Analog Ground Plane DGND AGND VDD 0.1 µF Substrate 5 - 10Ω Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 14-Lead PDIP (300 mil) Example: 14-Lead SOIC (150 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXX YYWWNNN MCP3004 0819256 XXXXXXXXXXX MCP3004 0819256 XXXXXXXXXXX XXXXXXXX NNN YYWW 14-Lead TSSOP (4.4mm) * Example: 3004 256 I819 I/P ISL ^^

DS21295D-page 26 © 2008 Microchip Technology Inc. Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3008)E x a m p l e : 16-Lead SOIC (150 mil) (MCP3008) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX YYWWNNN MCP3008-I/P 0819256 XXXXXXXXXXXXX MCP3008 0819256 XXXXXXXXXX 3eI/SL ^^

© 2008 Microchip Technology Inc. DS21295D-page 35 MCP3004/3008 APPENDIX A: REVISION HISTORY Revision D (December 2008) The following is the list of modifications: 1. Updates to Section 7.0 “Packaging Informa- tion”. Revision C (January 2007) The following is the list of modifications: 1. Updates to the packaging diagrams. Revision B (May 2002) The following is the list of modifications: 1. Undocumented changes. Revision A (February 2000)

Initial release of this document.

© 2008 Microchip Technology Inc. DS21295D-page 37 MCP3004/3008 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTemperature Range Device Device MCP3004: 4-Channel 10-Bit Serial A/D Converter MCP3004T: 4-Channel 10-Bit Serial A/D Converter (Tape and Reel) MCP3008: 8-Channel 10-Bit Serial A/D Converter MCP3008T: 8-Channel 10-Bit Serial A/D Converter (Tape and Reel) Temperature Range I = -40°C to +85°C (Industrial) Package P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Examples: a) MCP3004-I/P: Industrial Temperature, PDIP package. b) MCP3004-I/SL: Industrial Temperature, SOIC package. c) MCP3004-I/ST: Industrial Temperature, TSSOP package. d) MCP3004T-I/ST: Industrial Temperature, TSSOP package, Tape and Reel. a) MCP3008-I/P: Industrial Temperature, PDIP package. b) MCP3008-I/SL: Industrial Temperature, SOIC package.

© 2008 Microchip Technology Inc. DS21295D-page 39 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS21295D-page 40 © 2008 Microchip Technology Inc. AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 WORLDWIDE SALES AND SERVICE 01/02/08

Product Information

MCP3 specifications and overview.

Summary

2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface 2008

Description

2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface 2008

Source title MCP3 Datasheet(PDF) - Microchip Technology

Related Parts

More parts from the same family.

Browse manufacturer