Power Management

MCP2021-500E/SN

Microchip Technology

LIN Transceiver with Voltage Regulator 2009

Manufacturer: Microchip Technology

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Technical content

Features

The MCP2021 and MCP2022 are compliant with LIN Bus Specifications 1.3, 2.0, and 2.1 and are compliant to SAE J2602
Support Baud Rates up to 20 Kbaud with LIN-compatible output driver
43V load dump protected
Very low EMI meets stringent OEM requirements
Wide supply voltage, 6.0V - 18.0V continuous: - Maximum input voltage of 30V
Extended Temperature Range: -40 to +125°C
Interface to PIC EUSART and standard USARTs
Local Interconnect Network (LIN) bus pin: - Internal pull-up resistor and diode - Protected against ground shorts - Protected against loss of ground - High current drive
Automatic thermal shutdown
On-Board Voltage Regulator: - Output voltage of 5.0V with tolerances of ±3% overtemperature range - Available with alternate output voltage of 3.3V with tolerances of ±3% overtemperature range - Maximum continuous input voltage of 30V - Internal thermal overload protection - Internal short circuit current limit - External components limited to filter capacitor only and load capacitor
Two low-power modes: - Receiver on, Transmitter off, voltage regulator on ( ≅ 85 µA) - Receiver monitoring bus, Transmitter off, voltage regulator off (≅ 16 µA)

Description

The MCP2021/2 provides a bidirectional, half-duplex communication physical interface to automotive, and industrial LIN systems to meet the LIN bus specification Revision 2.0. The device incorporates a voltage regulator with 5V @ 50 mA or 3.3V @ 50 mA regulated power supply output. The regulator is short circuit protected, and is protected by an internal thermal shut- down circuit. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections, +43V load dump transients, and double-battery jumps. The device has been designed to meet the stringent quiescent current requirements of the automotive industry. MCP2021/2 family members:

8-pin PDIP, DFN and SOIC packages: - MCP2021-330, LIN-compatible driver, 8-pin, 3.3V regulator - MCP2021-500, LIN-compatible driver, 8-pin, 5.0V regulator
14-lead PDIP , TSSOP and SOIC packages with RESET output: - MCP2022-330, LIN-compatible driver, 14-pin, 3.3V regulator - MCP2022-500, LIN-compatible driver, 14-pin, 5.0V regulator Package Types MCP2021 DFN-8, PDIP-8, SOIC-8 MCP2022 PDIP-14, SOIC-14, TSSOP-14 RXD CS/LWAKE VREG TXD FAULT/TXE VBB LBUS VSS RXD CS/LWAKE VREG TXD RESET NC NC FAULT/TXE VBB LBUS VSS NC NC NC LIN Transceiver with Voltage Regulator

DS22018E-page 2 © 2009 Microchip Technology Inc. Block Diagram Voltage Regulator Ratiometric Reference OC Thermal Protection Internal CircuitsVREG FAULT/TXE RXD TXD VBB LBUS VSS ~30 kΩ CS/LWAKE Wake-Up Logic and Power Control RESETShort Circuit Protection Short Circuit Protection Thermal Protection

1.0 DEVICE OVERVIEW

The MCP2021/2 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. The MCP2021/2 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN level logic, and vice versa. The LIN specification 2.0 requires that the transceiver of all nodes in the system be connected via the LIN pin, referenced to ground and with a maximum external termination resistance of 510Ω from LIN bus to battery supply. The 510 Ω corresponds to 1 Master and 16 Slave nodes. The MCP2021-500 provides a +5V 50 mA regulated power output. The regulator uses a LDO design, is short-circuit-protected and will turn the regulator output off if it falls below 3.5V. The MCP2021/2 also includes thermal shutdown protection. The regulator has been specifically designed to operate in the automotive environment and will surviv e reverse battery connec- tions, +43V load dump transients and double-battery jumps. The other members of the MCP2021-330 family output +3.3V at 50 mA with a turn-off voltage of 2.5V. (see Section 1.6 “Internal Voltage Regulator”).

1.1 Optional External Protection

1.1.1 REVERSE BATTE RY PROTECTION

An external reverse-battery-blocking diode should be used to provide polarity protection (see Example 1-1).

1.1.2 TRANSIENT VOLTAGE

PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between V BB and ground, with a 50 Ω transient protection resistor (R TP) in series with the battery supply and the VBB pin serve to protect the device from power transients (see Example 1-1) and ESD events. While this protection is optional, it should be considered as good engineering practice. EQUATION 1-1:

1.2 Internal Protection

1.2.1 ESD PROTECTION

For component-level ESD ratings, please refer to the maximum operation specifications.

1.2.2 GROUND LO SS PROTECTION

The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a hi-impedance level.

1.2.3 THERMAL PROTECTION

The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions.

Voltage regulator overload
LIN bus output overload
Increase in die temperature due to increase in environment temperature Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low). FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAMS RTP <= (VBBmin - 5.5) / 250 mA. 5.5V = VUVLO + 1.0V , 250 mA is the peak current at power-on when VBB = 5.5V Operation Mode Transmitter Shutdown LIN bus Voltage Shutdown Regulator Output Temp < SHUTDOWNTEMP shorted to VBBOverload Temp < SHUTDOWNTEMP

1.3 Modes of Operation

For an overview of all operational modes, please refer to Table 1-1.

1.3.1 POWER-ON-RESET MODE

Upon application of VBB, the device enters Power-On- Reset mode (POR). During this mode, the part maintains the digital section in a reset mode and waits until the voltage on pin V BB rises above the “ON” threshold (Typ. 5.75V) to enter to the Ready mode. If during the operation, the voltage on pin VBB falls below the “OFF” threshold (Typ. 4.25V), the part comes back to the Power-On-Reset mode.

1.3.2 POWER-DOWN MODE

In the Power-down mode, the transmitter and the voltage regulator are both off. Only the receiver section, and the CS/LWAKE pin wake-up circuits are in operation. This is the lowest power mode. If any bus activity (e.g. a BREAK character) or CS/ LWAKE going to a high level should occur during Power-down mode, the device will immediately enter the Ready mode, enable the voltage regulator, and once the output has stabilized (approximately 0.3 ms to 1.2 ms), go to the Operation mode. The part will also enter the Ready mode, followed by the Operation mode, if the CS/LWAKE pin should become active true (‘1’). The part may only enter the Power-down mode after going through an Operation mode step.

1.3.3 READY MODE

Upon entering the Ready mode, the voltage regulator and receiver threshold detect circuit are powered up. The transmitter remains in power down mode. The device is ready to receive data but not to transmit. If a microcontroller is being driven by the voltage regulator output, it will go through a Power-on Reset and initial- ization sequence. The LIN pin is in the recessive state. The device will stay in the Ready mode until the output of the voltage regulator has stabilized and CS/LWAKE pin is true (‘1’). After V REG is OK and CS/LWAKE pin is true, the transmitter is enabled and the part enters the Operation mode. On Power-on of the VBB supply pin, the component will stay in the Ready mode if CS/LWAKE is low. If CS/ LWAKE is high, the device wi ll immediately enter the Operation mode.

1.3.4 OPERATION MODE

In this mode, all internal modules are operational. The MCP2021/2 will go into the Power-down mode on the falling edge of CS/LWAKE.

1.3.5 TRANSMITTER OFF MODE

Whenever the FAULT/TXE signal is low and the L BUS transmitter is off. The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, either by removing the internal fault condition or the CPU returning the FAULT/ TXE high. The transmitter will not be enabled if the FAULT/TXE pin is brought high when the internal fault is still present. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation.

1.3.5.1 Wake-up

The Wake-up sub module observes the L BUS in order to detect bus activity. Bus activity is detected when the voltage on the L BUS stays below a threshold of approximately 3V for at least a typical duration of 10 µs. Such a condition causes the device to leave the Power- down mode. FIGURE 1-2: OPE RATIONAL MODES STATE DIAGRAMS Note: The above time interval < 1.2 ms assumes 12V VBB input and no thermal shutdown event. Note: While the MCP2021/2 is in shutdown, TXD should not be actively driven high or it may power internal logic through the ESD diodes and may damage the device. Operation Mode Power-down Mode Ready Mode Bus Activity VREGOK = true POR CS/LWAKE VBBOK = true Start Transmitter Mode Off FAULT/TXE = true = false FAULT/TXE = false CS/LWAKE = false OR CS/LWAKE = true AND CS/LWAKE = true

1.4 Typical Applications

EXAMPLE 1-1: TYPICAL MCP2021 APPLICATION State Transmitter Receiver Voltage Regulator Operation Comments POR OFF OFF OFF Read CS/LWAKE, if LOW, then READY , if HIGH, Operational mode READY OFF Activity Detect ON If CS/LWAKE high leve l, then Operation mode Bus Off state OPERATION ON ON ON If CS/LWAKE low level, then Power down If FAULT/TXE low level, then Transmitter- Off mode Normal Operation mode POWER DOWN OFF Activity Detect OFF On LIN bus falling, go to READY mode. On CS/LWAKE high level, go to Operational mode Low Power mode TRANSMITTER- OFF OFF ON ON If CS/LWAKE low level, then Power down If FAULT /TXE high, then Operation mode LIN Bus 27V (4) VBB LBUS VREG TXD RXD VSS VDD TXD RXD +12 CF CG CS/LWAKEI/O FAULT/TXEI/O 43V(5) 1k Ω +12 Master Node Only +12 220 kΩ WAKE-UP Note 1: See Figure 2-3 for correct capacity and ESR for stable operation.. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V.. (3) RTP(5) 100nF

DS22018E-page 6 © 2009 Microchip Technology Inc. EXAMPLE 1-2: TYPICAL MCP2022 APPLICATION LIN Bus 27V (4) VBB LBUS VREG TXD RXD VSS VDD TXD RXD +12 CF CG CS/LWAKEI/O FAULT/TXEI/O 43V(5) 1k Ω +12 Master Node Only +12 220 kΩ WAKE-UP Note 1: See Figure 2-3 for correct capacity and ESR for stable operation. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V. 6: Required if CPU does not have internal pullup. (3) RTP(5) 100 nF INT RESET VDD (6)

© 2009 Microchip Technology Inc. DS22018E-page 7 MCP2021/2 EXAMPLE 1-3: TYPICAL MCP2022 APPLICATION FIGURE 1-3: TYPICAL LI N NETWORK CONFIGURATION LIN Bus 27V (4) VBB LBUS VREG TXD RXD VSS VDD TXD RXD +12 CF CG CS/LWAKEI/O FAULT/TXEI/O 43V(5) 1k Ω +12 Master Node Only +12 220 kΩ WAKE-UP Note 1: See Figure 2-3 for correct capacity and ESR for stable operation. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 43V. 5: These components are required for additional load dump protection above 43V. (3) RTP(5) 100 nF RESETMCLR 1k Ω LIN bus MCP202X Master µC 1k Ω VBB Slave 1 µC Slave 2 µC Slave n <16 µC 40m + Return LIN bus LIN bus MCP202X LIN bus MCP202X LIN bus MCP202X

1.5 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTIONS

1.5.1 POWER OUTPUT (V REG)

Positive Supply Voltage Regulator Output pin.

1.5.2 GROUND (V SS)

Ground pin.

1.5.3 BATTERY (V BB)

Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator.

1.5.4 TRANSMIT DATA INPUT (TXD)

The Transmit Data Input pin has an internal pull-up to V REG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. For extra bus security, TXD is internally forced to ‘ 1’ when VREG is less than 1.8V (typ.). In case the thermal protection detects an over-temper- ature condition while the signal TXD is low, the transmitter is shutdown. The recovery from the thermal shutdown is equal to adequate cooling time.

1.5.5 RECEIVE DATA OUTPUT (RXD)

The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin.

1.5.6 LIN BUS

The bidirectional LIN bus Interface pin is the driver unit for the LIN pin and is controlled by the signal TXD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled. To further reduce radiated emissions, the L BUS pin has corner-rounding control for both falling and rising edges. The internal LIN Receiver observes the activities on LIN bus, and generates t he output signal RXD that follows the state of the LBUS. A 1st degree 1 MHz, low- pass input filter is placed to maintain EMI immunity.

1.5.7 CS/LWAKE

Chip Select Input pin. A internal pull-down resistor will keep the CS/LWAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. The pin must see a high level to activate the transmitter. If CS/LWAKE= ‘0’ when the V BB supply is turned on, the device stays in Ready mode (Low-power mode). In Ready mode, both the receiver and the voltage regulator are on and the LIN transmitter driver is off. If CS/LWAKE = ‘1’ when the VBB supply is turned on, the device will proceed to the Operation mode as soon as the VREG output has stabilised. This pin may also be used as a local wake-up input (See Example 1-1). In this implementation, the micro- controller will set the I/O pin that controls the CS/ LWAKE as an high-impedance input. The internal pull- down resistor will keep the input low. An external switch, or other source, can then wake-up both the transceiver and the microcontroller. Pin Name Devices Pin Type Function 8-Pin DFN, PDIP, SOIC 14-Pin PDIP, SOIC, TSSOP Normal Operation V REG 3 3 O Power Output VSS 5 11 P Ground VBB 7 13 P Battery Supply TXD 4 4 I Transmit Data Input (TTL) RXD 1 1 O Receive Data Output (CMOS) LBUS 6 12 I/O LIN bus (bidirectional) CS/LWAKE 2 2 TTL Chip Select (TTL) FAULT/TXE 8 14 OD Fault Detect Output, Transmitter Enable (OD) RESET — 5 OD RESET signal Output (OD) Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open-Drain output, P = Power, O = Output, I = Input Note: CS/LWAKE should not be tied directly to VREG as this could force the MCP202x into Operation Mode before the microcontroller is initialized.

1.5.8 F AULT/TXE

Fault Detect output and Transmitter Enable input bidirectional pin. This pin is an open-drain output. Its state is defined as shown in Table 1-2. The transmitter driver is disabled whenever this pin is low (‘ 0’), either from an internal fault condition or by external drive. This allows the transmitter to be placed in an off state and still allow the voltage regulator to operate. Refer to Table 1-1. The FAULT/TXE also signals a mismatch between the TXD input and the L BUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. This pin has an internal pull-up resistor of approximately 750 kΩ. The FAULT/TXE pin sampled at a rate faster than every 10 µs. TABLE 1-2: FAULT/ TXE TRUTH TABLE

1.5.9 RESET

RESET is an open-drain output pin. This pin tracks an internal signal that tracks the internal system voltage has reached a valid, stable level. As long as the internal voltage is valid, this pin will remain high (‘1’). When the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the RESET output to (‘0’). When connected to a micro-controller input, this can provide a warning that the voltage regulator is shutting down (see Example 1- 2). Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Example 1-3). In addition to monitoring the internal voltage, RESET is asserted immediately upon entering the Powerdown mode. Note 1: The FAULT/TXE pin is true ( 0) whenever the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. 2: FAULT/TXE is true (0) when VREG not OK and has disabled the LBUS output driver. TXD In RXD Out LINBUS I/O Thermal Override FAULT/TXE DefinitionExternal Input Driven Output LHV BB OFF H L FAULT, TXD driven low, LINBUS shorted to VBB (Note 1) HHV BB OFF H H OK LL G N D O F F H H OK HL G N D O F F H H OK, data is being received from the LINBUS xxV BB ON H L FAULT, Tranceiver in thermal shutdown xxV BB xL x NO FAULT, the CPU is commanding the tranceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays.

1.6 Internal Voltage Regulator

1.6.1 5.0V REGULATOR The MCP2021 has a low-drop-out voltage, positive regulator capable of supplying 5.00 V DC ±3% at up to 50 mA of load current over the entire operating temperature range of -40°C to +125°C. With a load current of 50 mA, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 µA with a full 50 mA load current when the input to output voltage differential is greater than +3.00V. The regulator requires an external output bypass capacitor for stability. See Figure 2-3 for correct capac- ity and ESR for stable operation. Designed for automotive applications, the regulator will protect itself from double-battery jumps and up to +43V load dump transients. The voltage regulator has both short-circuit and thermal shutdown protection built-in. Regarding the correlation between V BB, VREG and IDD, please refer to Figure 1-5 through 1-7. When the input voltage (V BB) drops below the differential needed to provide stable regulation, the output Vreg will track the input down to approximately 3.5V, at which point the regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the Power-on Reset trip point. The MCP2021 will then monitor V BB and turn on the regulator when Vbb is 6.0V. When the input voltage (V BB) drops below the differential needed to provide stable regulation, the output V REG) will track the input down to approximately +4.25V. The regulator will turn off the output at this point. This will allow PIC ® microcontrollers, with internal POR circuits, to generate a clean arming of the Power-on Reset trip point. The regulator output will stay off until VBB is above +5.75 VDC. In the start phase, the device must see at least 6.0V to initiate operation during power up. In the Power-down mode, the VBB monitor will be turned off. The regulator has a thermal shutdown. If the thermal protection circuit detects an over temperature condition, and the signals T XD and RXD are LOW, or TXD is HIGH, the regulator will shut down. The recovery from the thermal shutdown is equal to adequate cooling time. FIGURE 1-4: VOLTAGE RE GULATOR BLOCK DIAGRAM Note: The regulator has an overload current limiting of approximately 100 mA. During a short circuit, the V REG is monitored. If VREG is lower than 3.5V, the VREG will turn off. After a recovery time of about three milliseconds, the V REG will be checked again. If there is no short circuit, (V REG > 3.5V) then the VREG will be switched back on. Pass Element Sampling Network Buffer VREG VBB VSS Fast Transient Loop VREF

© 2009 Microchip Technology Inc. DS22018E-page 11 MCP2021/2 1.6.2 3.3V REGULATOR A metal option provides for a alternate 3.30 V DC ±3% at up to 50 mA of load current over the entire operating temperature range of -40°C to +125°C. All specifications given above for the 5.0V operation apply except for any difference noted here. The same input tracking of 4.25V applies the 3.3V regulator. FIGURE 1-5: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET Note: The regulator has an overload current limiting of approximately 100 mA. If V REG is lower than 2.5V, the VREG will turn off. Note 1: Start-up, VBB < 5.75V, regulator off. 2: VBB > 5.75V, regulator on. 3: VBB ≤ 5.5V, regulator tracks VBB 4: VBB < 4.25V, regulator will turn off 5.0 3.5 (1) (2) (3) t 0 t VBB V VREG V

DS22018E-page 12 © 2009 Microchip Technology Inc. FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON POWER DIP Note 1: Voltage regulator on. 2: VBB ≤ 5.5V, regulator tracks VBB until VBB < 4.25V. 3: VREG < 3.5V, regulator is off. 4: VBB > 5.75V, regulator on. 3.5 (1) (2) (3) t 0 t 3.5 (4) VBB V VREG V

1.7 ICSP™ Considerations

The following should be considered when the MCP2021/2 is connected to pins supporting in-circuit programming:

Power used for programming the microcontroller can be supplied from the programmer, or from the MCP2021/2.
The voltage on V REG should not exceed the maximum output voltage of VREG. Note 1: IREG less than 50 mA, regulator on. 2: After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached. 5.0 3.5 (1) (2) t 0 t IREG mA VREG V

2.0 ELECTRICAL CHARACTERISTICS

2.1 Absolute Maximum Ratings†

Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

2.2 DC Specifications

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10 µF Parameter Sym Min. Typ. Max. Units Conditions Power VBB Quiescent Operating Current IBBQ 115 210 µA I OUT = 0 mA, LBUS recessive — 120 215 µA V OUT = 3.3V VBB Transmitter-off Current IBBTO — 90 190 µA With V REG on, transmitter off, receiver on, FAULT/ TXE = VIL, CS = VIH — 95 210 µA V OUT = 3.3V VBB Power-down Current I BBPD —1 6 2 6 µ A W i t h V REG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) VBB Current with VSS Floating IBBNOGND -1 — 1m A V BB = 12V, GND to VBB, VLIN = 0-18V Microcontroller Interface High Level Input Voltage (TXD, FAULT /TXE) VIH 2.0 or (0.25VREG +0.8) — VREG +0.3 V Low Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 — 0.15 VREG V High Level Input Current (TXD, FAULT/TXE) IIH -2.5 — — µA Input voltage = 0.8*V REG Low Level Input Current (TXD, FAULT/TXE) IIL -10 — — µA Input voltage = 0.2*V REG Pull-up Current on Input (TXD) IPUTXD -3.0 — — µA ~800 k Ω internal pull-up to VREG @ VIH = 0.7*VREG High Level Input Voltage (CS/LWAKE) VIH 0.7VREG — VBB V Through a current-limiting resistor Low Level Input Voltage (CS/LWAKE) VIL -0.3 — 0.3VREG V High Level Input Current (CS/LWAKE) IIH — — 7.0 µA Input voltage = 0.8*V REG Low Level Input Current (CS/LWAKE) IIL — — 3.0 µA Input voltage = 0.2*V REG Pull-down Current on Input (CS/LWAKE) IPDCS — — 6.0 µA ~1.3M Ω internal pull-down to VSS @ VIH = 3.5V Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition.

© 2009 Microchip Technology Inc. DS22018E-page 17 MCP2021/2 Bus Interface High Level Input Voltage V IH(LBUS) 0.6 V BB — 18 V Recessive state Low Level Input Voltage V IL(LBUS)- 8 — 0.4 VBB V Dominant state Input Hysteresis V HYS —— 0.175 VBB VV IH(LBUS) - VIL(LBUS) Low Level Output Current I OL(LBUS)4 0 — 200 mA Output voltage = 0.1 V BB, VBB = 12V Pull-up Current on Input I PU(LBUS)5 — 180 µA ~30 k Ω internal pull-up @ VIH (LBUS) = 0.7 VBB Short Circuit Current Limit ISC 50 — 200 mA (Note 1) High Level Output Voltage VOH(LBUS) 0.8 V BB — VBB VV OH(LBUS) must be at least

0.8 VBB

Low Level Output Voltage V OLLO (LBUS) — — 0.2 VBB V Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 — —m A D r i v e r o f f , VBUS = 0V, VBAT = 12V Leakage Current (disconnected from ground) IBUS_NO_GND -1 — +1 mA GND DEVICE = VBAT, 0V < VBUS < 18V, VBAT = 12V Leakage Current (disconnected from VBAT) IBUS — — 10 µA V BAT = GND, 0 < VBUS < 18V, TA = -40°C to +85°C (Note 3) 50 µA T A = +85°C to +125°C Receiver Center Voltage V BUS_CNT 0.475 VBB 0.5 VBB

0.525 VBB VV BUS_CNT = (VIL (LBUS) +

VIH (LBUS))/2 Slave Termination Rslave 20 30 47 k Ω

2.2 DC Specifications (Continued)

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V BB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10 µF Parameter Sym Min. Typ. Max. Units Conditions Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition.

2.2 DC Specification (Continued)

FIGURE 2-1: MCP2021-500 SAFE OPERATING RANGE DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V BB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10 µF Parameter Sym Min. Typ. Max. Units Conditions Voltage Regulator - 5.0V Output Voltage V OUT 4.85 5.00 5.15 V 0 mA < I OUT < 50 mA, Load Regulation ΔVOUT2 — 10 50 mV 5 mA < I OUT < 50 mA refer to Section 1.6 “Internal Voltage Regulator” Quiescent Current I VRQ — — 25 µA I OUT = 0 mA, (Note 2) Power Supply Ripple Reject PSRR — — 50 dB 1 V PP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Output Noise Voltage eN — — 100 µV RMS 10 Hz – 40 MHz CFILTER = 10 µf, CBP = 0.1 µf, CLOAD 10 µf, ILOAD = 50 mA Shutdown Voltage V SD 3.5 — 4.0 V See Figure 1-5 Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. -40 -34 -28 -22 -16 -10 104 110 116 122 Temperature (°C) Voltage Regulator Load (mA) 18V DFN 18V SOIC 12V SOIC 12V DFN

© 2009 Microchip Technology Inc. DS22018E-page 19 MCP2021/2 FIGURE 2-2: MCP2021-330 SAFE OPERATING RANGE DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V BB = 6.0V to 18.0V TA = -40°C to +125°C CLOADREG = 10 µF Parameter Sym Min. Typ. Max. Units Conditions Voltage Regulator - 3.3V Output Voltage V OUT 3.20 3.30 3.40 V 0 mA < I OUT < 50 mA Line Regulation ΔVOUT1 — 10 50 mV I OUT = 1 mA, 6.0V < VBB < 18V Load Regulation ΔVOUT2 — 10 50 mV 5 mA < I OUT < 50 mA Refer to Section 1.6 “Internal Voltage Regulator” Quiescent Current I VRQ — — 25 µA I OUT = 0 mA, (Note 2) Power Supply Ripple Reject PSRR — — 50 dB 1 V PP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Output Noise Voltage eN — — 100 µV RMS /√Hz

10 Hz – 40 MHz

CFILTER = 10 µf, CBP = 0.1 µf CLOAD = 10 µf, ILOAD = 50 mA Shutdown Voltage V SD 2.5 — 2.7 V See Figure 1-5 Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). 2: For design guidance only, not tested. 3: Node has to sustain the current that can flow under this condition; bus must be operational under this condition. -40 -34 -28 -22 -16 -10 104 110 116 122 Temperature (°C) Voltage Regulator Load (mA) 18V DFN 18V SOIC 12V SOIC 12V DFN

DS22018E-page 20 © 2009 Microchip Technology Inc. FIGURE 2-3: ESR CURVES FOR LOAD CAPACITOR SELECTION Load Capacitor [uF] ESR Curves ESR [ohm] 0.1 0.01 0.001 10 100 100010.1 Instable Instable Instable Stable only with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap.

2.3 AC Specification

AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions Bus Interface - Constant Slope Time Parameters Slope rising and falling edges tSLOPE 3.5 — 22.5 µs 7.3V <= V BB <= 18V Propagation Delay of Transmitter tTRANSPD —— 4 . 0 µ s t TRANSPD = max (tTRANSPDR or tTRANSPDF) Propagation Delay of Receiver tRECPD —— 6 . 0 µ s t RECPD = max (tRECPDR or tRECPDF) Symmetry of Propagation Delay of Receiver rising edge w.r.t. falling edge t RECSYM -2.0 — 2.0 µs t RECSYM = max (tRECPDF - tRECPDR) Symmetry of Propagation Delay of Transmitter rising edge w.r.t. falling edge t TRANSSYM -2.0 — 2.0 µs t TRANSSYM = max (tTRANSPDF - tTRANSPDR) Time to sample of FAULT/ TXE for bus conflict reporting tFAULT — — 32.5 µs t FAULT = max (tTRANSPD + tSLOPE + tRECPD) Duty Cycle 1 @20.0 kbit/sec 39.6 — — %t BIT CBUS;RBUS conditions: 1n F ; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50 µs. D1 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 2 @20.0 kbit/sec — — 58.1 %t BIT CBUS;RBUS conditions: 1n F ; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50 µs. D2 = tBUS_REC(MAX) / 2 x tBIT) Duty Cycle 3 @10.4 kbit/sec 41.7 — — %t BIT CBUS;RBUS conditions: 1n F ; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96 µs. D3 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 4 @10.4 kbit/sec — — 59.0 %t BIT CBUS;RBUS conditions: 1n F ; 1kΩ | 6.8 nF; 660Ω | 10 nF; 500Ω THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96 µs. D4 = tBUS_REC(MAX) / 2 x tBIT)

2.4 Thermal Specifications

Bus Activity Debounce time t BDB 5 10 20 µs Bus debounce time Bus Activity to Voltage Regulator Enabled tBACTVE 100 250 500 µs After Bus debounce time Voltage Regulator Enabled to Ready tVEVR — — 1200 µs (Note 1) Chip Select to Operation Ready tCSOR —— 5 0 0 µ s (Note 1) Chip Select to Power-down t CSPD — — 80 µs Short circuit to shut-down t SHUTDOWN 20 — 100 µs RESET Timing VREG OK detect to RESET inactive tRPU — — 10.0 µs VREG OK detect to RESET active tRPD — — 10.0 µs Note 1: Time depends on external capacitance and load. THERMAL CHARACTERISTICS Parameter Symbol Typ Max Units Test Conditions Recovery Temperature θRECOVERY +140 — °C Shutdown Temperature θSHUTDOWN +150 — °C Short Circuit Recovery Time t THERM 1.5 5.0 ms Thermal Package Resistances Thermal Resistance, 8L-DFN θJA 35.7 — °C/W Thermal Resistance, 8L-PDIP θJA 89.3 — °C/W Thermal Resistance, 8L-SOIC θJA 149.5 — °C/W Thermal Resistance, 14L-PDIP θJA 70 — °C/W Thermal Resistance, 14L-SOIC θJA 95.3 — °C/W Thermal Resistance, 14L-TSSOP θJA 100 — °C/W Note 1: The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the MCP2021 will go into thermal shutdown.

2.3 AC Specification (Continued)

AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions

2.5 Timing Diagrams and Specifications

FIGURE 2-4: BUS TIMING DIAGRAM FIGURE 2-5: REGULATOR CS/LWAKE TIMING DIAGRAM .95VLBUS TTRANSPDR TRECPDR TTRANSPDF TRECPDF TXD LBUS RXD Internal TXD/RXD Compare FAULT Sampling TFAULT TFAULT FAULT/TXE Output Stable StableStable Match MatchMatch Match Match Hold Value Hold Value 50%50% .50VBB 50%50% 0.0V TCSPD TCSOR CS/LWAKE VOUT VREG

3.0 PACKAGING INFORMATION

3.1 Package Marking Information

8-Lead PDIP (300 mil) Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN E/P^^256 0729 2021500E SN^^0729 256 2021500 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead DFN-S (6x5) Example: XXXXXXX XXYYWW NNN XXXXXXX 2021500 0733 256 E/MF^^3e 8-Lead DFN (4x4) Example: XXXXXXX XXYYWW NNN XXXXXXX 202150 0733 256 E/MD^^3e

3.1 Package Marking Information (Continued)

Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 14-Lead PDIP (300 mil) (MCP2022) Example: 14-Lead SOIC (150 mil) (MCP2022) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXX YYWWNNN MCP2022-500 0729256 XXXXXXXXXX MCP2022-500 0729256 E/SL^^ E/P^^3e 14-Lead TSSOP (MCP2022) XXXXXXXX YYWW NNN Example 2022500E 0729 256

© 2009 Microchip Technology Inc. DS22018E-page 29 MCP2021/2 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.80 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 4.00 BSC Exposed Pad Width E2 0.00 2.20 2.80 Overall Width E 4.00 BSC Exposed Pad Length D2 0.00 3.00 3.60 Contact Width b 0.25 0.30 0.35 Contact Length L 0.30 0.55 0.65 Contact-to-Exposed Pad K 0.20 – – D N E NOTE 1 1 2 A NOTE 2 NOTE 1 L N e b K EXPOSED PAD TOP VIEW BOTTOM VIEW Microchip Technology Drawing C04-131C

© 2009 Microchip Technology Inc. DS22018E-page 31 MCP2021/2 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A 0.80 0.85 1.00 Standoff A1 0.00 0.01 0.05 Contact Thickness A3 0.20 REF Overall Length D 5.00 BSC Overall Width E 6.00 BSC Exposed Pad Length D2 3.90 4.00 4.10 Exposed Pad Width E2 2.20 2.30 2.40 Contact Width b 0.35 0.40 0.48 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – NOTE 2 A NOTE 1 12 E N D EXPOSED PAD NOTE 12 1 L N e b K BOTTOM VIEWTOP VIEW Microchip Technology Drawing C04-122B

© 2009 Microchip Technology Inc. DS22018E-page 33 MCP2021/2 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 N NOTE 1 D 12 3 A L b e E eB c Microchip Technology Drawing C04-018B

DS22018E-page 34 © 2009 Microchip Technology Inc. 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° D N e E NOTE 1 123 b A L c h h φ β α Microchip Technology Drawing C04-057B

DS22018E-page 36 © 2009 Microchip Technology Inc. 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .045 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 N D NOTE 1 12 3 E c eB L A be Microchip Technology Drawing C04-005B

© 2009 Microchip Technology Inc. DS22018E-page 37 MCP2021/2 14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 8.65 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° NOTE 1 N D E 1 23 b e A L c h h α β φ Microchip Technology Drawing C04-065B

© 2009 Microchip Technology Inc. DS22018E-page 39 MCP2021/2 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 14 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 4.90 5.00 5.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 NOTE 1 D N E 1 2 e b c A L1 L φ Microchip Technology Drawing C04-087B

© 2009 Microchip Technology Inc. DS22018E-page 41 MCP2021/2 APPENDIX A: REVISION HISTORY Revision E (February 2009) The following is the list of modifications. 1. Added Example 1-2 and Example 1-3. 2. Updated Section 1.5.9 “RESET”. 3. Updated Section 1.7 “ICSP™ Consider- ations”. 4. Updated Section 2.1 “Absolute Maximum Ratings†”. 5. Updated Section 2.2 “DC Specifications” and Section 2.3 “AC Specification”. 6. Added FIGURE 2-3: “ESR Curves For Load Capacitor Selection”. 7. Updated the Product Identification System section. Revision D (July 2008) The following is the list of modifications. 1. Updated ESD specs under ‘Absolute DC’. 2. Updated notes in Example 1-1. 3. Updated Package Outline Drawings. Revision C (April 2008) The following is the list of modifications. 1. Added LIN2.1 and J2602 compliance statement to Features section. 2. Added recommended RC network for CS/ LWAKE in Example 1-1. 3. Updated 2.1 Absolute Maximum Ratings to reflect current test results. 4. Updated 2.2 DC Specifications and 2.3 AC Specifications to refl ect current production device. 5. Added 8-Lead SOIC Landing Pattern Outline drawing. Revision B (August 2007) The following is the list of modifications: 1. Modified Block Diagram on page 2. 2. Section 1.3.5 “Transmitter OFF Mode” : Deleted text in 1st paragraph. 3. Example 1-1: Removed +5V notation. 4. Section 1.5 “Pin Descriptions”: Removed 10- pin DFN, MSOP column from table. 5. Section 1.5.8 “Fault/TXE”: Deleted text from 2nd paragraph. 6. Section 3.0 “Packaging Information”: Added 8-lead 4x4 and 6x5 DFN and 14-lead TSSOP packages. Updated package outline drawings and added drawings for 8-lead DFN and 14-lead TSSOP drawings. Revision A (November 2005)

Original Release of this Document.

© 2009 Microchip Technology Inc. DS22018E-page 43 MCP2021/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: MCP2021: LIN Transceiver with Voltage Regulator MCP2021T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only) MCP2022: LIN Transceiver with Voltage Regulator MCP2022T: LIN Transceiver with Voltage Regulator (Tape and Reel) (SOIC only) Temperature Range: E = -40°C to +125°C Package: MD = Plastic Micro Small Outline (4x4), 8-lead MF = Plastic Micro Small Outline (6x5), 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead SL = Plastic SOIC, (150 mil Body), 14-lead ST = Plastic Thin Shrink Small Outline, 14-lead PART NO. –X /XX PackageTemperature Range Device Examples: a) MCP2021-330E/SN: 3.3V, 8L-SOIC pkg. b) MCP2021-330E/P: 3.3V, 8L-PDIP pkg. c) MCP2021-500E/MF: 5.0V, 8L-DFN-S pkg. d) MCP2021-500E/SN: 5.0V, 8L-SOIC pkg. e) MCP2021-500E/MD: 5.0V, 8L-DFN pkg. f) MCP2021-330E/P: 5.0V, 8L-PDIP pkg. g) MCP2021T-330E/SN: Tape and Reel, 3.3V, 8L-SOIC pkg. h) MCP2021T-500E/MD: Tape and Reel, 5.0V, 8L-DFN pkg. i) MCP2021T-500E/SN: Tape and Reel, 5.0V, 8L-SOIC pkg. a) MCP2022-330E/SL: 3.3V, 14L-SOIC pkg. b) MCP2022-330E/P: 3.3V, 14L-PDIP pkg. c) MCP2022-500E/SL: 5.0V, 14L-SOIC pkg. d) MCP2022-500E/P: 5.0V, 14L-PDIP pkg. e) MCP2022T-330E/SL: Tape and Reel, 3.3V, 14L-SOIC pkg. f) MCP2022T-500E/SL: Tape and Reel, 5.0V, 14L-SOIC pkg. g) MCP2022T-500E/ST: Tape and Reel, 5.0V, 14L-TSSOP pkg.

© 2009 Microchip Technology Inc. DS22018E-page 45 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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Product Information

MCP2021-500E/SN specifications and overview.

Summary

LIN Transceiver with Voltage Regulator 2009

Description

LIN Transceiver with Voltage Regulator 2009

Source title MCP2021-500E/SN Datasheet(PDF) - Microchip Technology

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