MCP2003

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Document overview

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Technical content

Features

• The MCP2003 and MCP2004 are compliant with LIN Bus Specifications 1.3, 2.0 and 2.1 and are compliant to SAE J2602
• Support Baud Rates up to 20 Kbaud with LIN-compatible output driver
• 43V load dump protected
• Very low EMI meets stringent OEM requirements
• Very high ESD immunity: - >20kV on VBB (IEC 61000-4-2) - >14kV on LBUS (IEC 61000-4-2)
• Very high immunity to RF disturbances meets stringent OEM requirements
• Wide supply voltage, 6.0V-27.0V continuous
• Extended Temperature Range: -40 to +125°C
• Interface to PIC ® MCU EUSART and standard USARTs
• Local Interconnect Network (LIN) bus pin: - Internal pull-up resistor and diode - Protected against battery shorts - Protected against loss of ground - High current drive
• Automatic thermal shutdown
• Low-power mode: - Receiver monitoring bus and transmitter off,  5µ A )

Description

This device provides a bidirectional, half-duplex communication physical interface to automotive and industrial LIN systems to meet the LIN bus specification Revision 2.1 and SAE J2602. The device is short circuit and overtemperature protected by internal circuitry. The device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. MCP200X family members:

• 8-pin PDIP , DFN and SOIC packages: - MCP2003, LIN-compatible driver, with WAKE pins - MCP2004, LIN-compatible driver, with FAULT/TXE pins Package Types MCP2004 PDIP, SOIC FAULT/TXE CS TXD VBB LBUS

5 VSS

PDIP , SOIC WAKE CS TXD VBB LBUS 4x4 DFN* WAKE CS TXD VBB LBUS 4x4 DFN* FAULT/TXE CS TXD VBB LBUS

• Includes Exposed Thermal Pad (EP); see Table 1-1. LIN J2602 Transceiver

DS22230A-page 2  2010 Microchip Technology Inc. MCP2003 Block Diagram MCP2004 Block Diagram Ratiometric Reference OC Thermal Protection VREN WAKE RXD TXD VBB LBUS VSS ~30 k CS Wake-Up Logic and Power Control Short Circuit Protection Ratiometric Reference OC Thermal Protection VREN FAULT/TXE RXD TXD VBB LBUS VSS ~30 k CS Wake-Up Logic and Power Control Short Circuit Protection

 2010 Microchip Technology Inc. DS22230A-page 3 MCP2003/4

1.0 DEVICE OVERVIEW

The MCP2003/4 provides a physical interface between a microcontroller and a LIN bus. This device will translate the CMOS/TTL logic levels to LIN logic level, and vice versa. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. LIN specification 2.1 requires that the transceiver of all nodes in the system is connected via the LIN pin, refer- enced to ground and with a maximum external termination resistance of 510 from LIN bus to battery supply. The 510  corresponds to 1 master and 15 slave nodes. The V REN pin can be used to drive the logic input of an external voltage regulator. This pin is high in all modes except for Power Down mode.

1.1 External Protection

1.1.1 REVERSE BATTERY PROTECTION

An external reverse-battery-blocking diode should be used to provide polarity protection (see Example 1-1).

1.1.2 TRANSIENT VOLTAGE

PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between V BB and ground, with a 50  transient protection resistor (R TP) in series with the battery supply and the VBB pin serve to protect the device from power transients (see Example 1-1) and ESD events. While this protection is optional, it is considered good engineering practice.

1.2 Internal Protection

1.2.1 ESD PROTECTION

For component-level ESD ratings, please refer to the maximum operation specifications.

1.2.2 GROUND LOSS PROTECTION

The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a high-impedance level.

1.2.3 THERMAL PROTECTION

The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter. There are two causes for a thermal overload. A thermal shut down can be triggered by either, or both, of the following thermal overload conditions.

• LIN bus output overload
• Increase in die temperature due to increase in environment temperature Driving the T XD and checking the RXD pin makes it pos- sible to determine whether there is a bus contention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low). After a thermal overload event, the device will automatically recover once the die tem- perature has fallen below the recovery temperature threshold. See Figure 1-1. FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAM Operation Mode Transmitter Shutdown LIN bus Shorted to VBB Temp < SHUTDOWNTEMP

DS22230A-page 4  2010 Microchip Technology Inc.

1.3 Modes of Operation

For an overview of all operational modes, refer to Table 1-1.

1.3.1 POWER-DOWN MODE

In Power Down mode, the transmitter and V REN are both off. Only the receiver section and the wake-up circuits are operational. This is the lowest power mode. On bus activity (e.g. a BREAK character), CS going to a high level, or on a falling edge on WAKE, the device will immediately enter Ready mode. If CS is held high as the device transitions from Power Down to Ready mode, the device will transition to Operation mode as soon as internal voltages stabilize.

1.3.2 READY MODE

Upon entering the Ready mode, V REN is enabled and the receiver detect circuit is powered up. The transmit- ter remains disabled and the device is ready to receive data but not to transmit. Upon VBB supply pin power-on, the device will remain in Ready mode as long as CS is low. If CS transitions high, the device will enter Operation mode. However, if the T XD pin is held low when CS goes high, the device will transition to Transmitter Off mode instead of Operation mode.

1.3.3 OPERATION MODE

In this mode, all internal modules are operational. The MCP2003/4 will go into the Power Down mode on the falling edge of CS. The MCP2003/4 will enter Transmitter Off mode in the event of a Fault condition. These include: thermal overload, bus contention and T XD timer expiration. The MCP2004 device can also enter Transmitter Off mode if the FAULT/TXE pin is pulled low

1.3.4 TRANSMITTER OFF MODE

Transmitter Off mode is reached whenever the transmitter is disabled either due to a Fault condition or pulling the nFAULT/TXE pin low on the MCP2004. The fault conditions include: thermal overload, bus contention or TXD timer expiration. The MCP2003/4 will go into Power Down mode on falling edge of CS, or return to Operation mode if all faults are resolved and the FAULT /TXE pin on the MCP2004 is high. FIGURE 1-2: OPERATIONAL MOD ES STATE DIAGRAM – MCP2003 Note: Bus activity is defined as LBUS dropping below V IL(LBUS) for longer than the Bus Activity Debounce time (tBDB). Operation Mode VREN ON RX ON TX ON Ready Mode VREN ON RX ON TX OFF TOFF Mode VREN ON RX ON TX OFF Sleep Mode VREN OFF RX OFF TX OFF VBB > 5.5V CS = 1 and TXD = 0 CS=0 CS = 1 and TXD = 1 CS=0 Falling edge on LIN or CS = 1 CS = 1 and TXD = 1 and No Fault Fault (Thermal or Timer ) POR VREN OFF RX OFF TX OFF

 2010 Microchip Technology Inc. DS22230A-page 5 MCP2003/4 FIGURE 1-3: OPERATIONAL MOD ES STATE DIAGRAM – MCP2004 TABLE 1-1: OVERVIEW OF OPERATIONAL MODES Note: While the MCP2003/4 is in thermal shutdown, T XD should not be actively driven high or it may power internal logic through the ESD diodes and may damage the device. State Transmitter Receiver Vren Operation Comments POR OFF OFF OFF Read CS, if low, then Ready; if high, Operational mode Ready OFF ON ON If CS high level, then Operation mode Bus Off state Operation ON ON ON If CS low level, then Power Down; If FAULT/TXE low level, then Transmitter Off mode Normal Operation mode Power Down OFF Activity Detect OFF On LIN bus falling, go to Ready mode. On CS high level, go to Operation mode Low Power mode Transmitter Off OFF ON ON If CS low level, then Power Down; If FAULT/TXE and TXD high, then Operation mode FAULT/TXE only available on MCP2004 Operation Mode VREN ON RX ON TX ON Ready Mode VREN ON RX ON TX OFF TOFF Mode VREN ON RX ON TX OFF Sleep Mode VREN OFF RX OFF TX OFF VBB > 5.5V CS = 0 CS = 0 Falling edge on LIN or CS = 1 POR VREN OFF RX OFF TX OFF CS = 1and TXE = 1 and TXD = 1 and No Fault Fault (Thermal or Timer) or TXE=0 CS = 1 and (TXE = 0 or TXD = 0 ) CS = 1 and TXD = 1 and TXE = 1

DS22230A-page 6  2010 Microchip Technology Inc.

1.4 Typical Applications

EXAMPLE 1-1: TYPICAL MCP2003 APPLICATION EXAMPLE 1-2: TYPICAL MCP2004 APPLICATION LIN Bus 27V VBB LBUS VREN TXD RXD VSS VDD TXD RXD +12 1.0 µF CSI/O WAKE 50 43V 1K  +12 Master Node Only +12 220 K Wake-up VOLTAGE REG 100 nF (See Note) Note: For applications with current requirements of less than 20 mA, the connection to +12V can be deleted, and voltage to the regulator supplied directly from the VREN pin. LIN Bus 27V VBB LBUS VREN TXD RXD VSS VDD TXD RXD +12 1.0 µF CSI/O FAULT/TXEI/O 50 43V 1K  +12 Master Node Only +12 220 K Wake-up VOLTAGE REG 100 nF

 2010 Microchip Technology Inc. DS22230A-page 7 MCP2003/4 EXAMPLE 1-3: TYPICAL LI N NETWORK CONFIGURATION Master µC 1k  VBB Slave 1 µC Slave 2 µC Slave n <23 µC 40m + Return LIN bus LIN bus MCP200X LIN bus MCP200X LIN bus MCP200X LIN bus MCP200X

DS22230A-page 8  2010 Microchip Technology Inc.

1.5 Pin Descriptions

TABLE 1-1: PINOUT DESCRIPTIONS

1.5.1 RECEIVE DATA OUTPUT (R XD)

The Receive Data Output pin is a open drain (OD) output and follows the state of the LIN pin.

1.5.2 CS (CHIP SELECT)

Chip Select Input pin. An internal pull-down resistor will keep the CS pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and an I/O initialization sequence. The pin must detect a high level to activate the transmitter. If CS = 0 when the V BB supply is turned on, the device stays in Ready mode. In Ready mode, the receiver is on and the LIN transmitter driver is off. If CS = 1 when the VBB supply is turned on, the device will proceed to the Operation mode as soon as internal voltages stabilize. This pin may also be used as a local wake-up input (Refer to Example 1-1). In this implementation, the microcontroller I/O controlling the CS should be converted to a high-impedance input allowing the internal pull-down resistor will keep CS low. An external switch, or other source, can then wake-up both the transceiver and the microcontroller (if powered).

1.5.3 WAKE UP INPUT (WAKE)

This pin is only available on the MCP2003. The WAKE pin has an internal 800K pull up to V BB. A falling edge on the WAKE pin causes the device to wake from Power Down mode. Upon waking, the MCP2003 will enter Ready mode

1.5.4 FAULT /TXE

This pin is only available on the MCP2004. This pin is bidirectional and allows disabling of the transmitter, as well as fault reporting related to disabling the transmitter. This pin is an open-drain output with states as defined in Table 1-2. The transmitter is disabled whenever this pin is low (‘ 0’), either from an internal Fault condition or by an external drive. While the transmitter is disabled, the internal 30 k  pull-up resistor on the L BUS pin is also disconnected to reduce current. Pin Name 8-Pin PDIP , SOIC 8-Pin DFN MCP2003 MCP2004 Normal Operation Normal Operation RXD 1 1 Receive Data Output (OD) Receive Data Output (OD) CS 2 2 Chip Select (TTL) Chip Select/Local WAKE (TTL) WAKE (MCP2003 only) FAULT/TXE (MCP2004 only) 3 3 Wake up, HV tolerant Fault Detect Output (OD) Transmitter Enable (TTL) TXD 4 4 Transmit Data Input (TTL) Transmit Data Input (TTL) VSS 5 5 Ground Ground LBUS 6 6 LIN bus (bidirectional) LIN bus (bidirectional) VBB 7 7 Battery positive Battery positive VREN 8 8 Voltage Regulator Enable Output Voltage Regulator Enable Output EP — 9 Exposed Thermal Pad. Do not electrically connect or connect to Vss Exposed Thermal Pad. Do not electrically connect or connect to Vss Legend: TTL = TTL Input Buffer; OD = Open-Drain Output Note: It is not recommended to tie CS high as this can result the MCP2003/4 entering Operation mode before the microcon- troller is initialized and may result in unintentional LIN traffic. Note: The FAULT/TXE pin is true (‘0’) whenever the internal circuits have detected a short or thermal excursion and have disabled the L BUS output driver.

 2010 Microchip Technology Inc. DS22230A-page 9 MCP2003/4 TABLE 1-2: FAULT/ TXE TRUTH TABLE

1.5.5 TRANSMIT DATA INPUT (T XD)

The Transmit Data Input pin has an internal pull-up. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. For extra bus security, T XD is internally forced to ‘ 1’ whenever the transmitter is disabled regardless of external T XD voltage.

1.5.5.1 T XD Dominant Timeout

If TXD is driven low longer than approximately 10 ms, the LBUS pin is switched to Recessive mode and the part enters TOFF mode. This is to prevent the LIN node from permanently driving the LIN Bus dominant. The transmitter is re-enabled on the T XD rising edge.

1.5.6 GROUND (V SS)

This is the Ground pin.

1.5.7 LIN BUS (L BUS)

The bidirectional LIN Bus pin (LBUS) is controlled by the TXD input. L BUS has a current limited open collector output. To reduce EMI, the edges during the signal changes are slope controlled and include corner rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus, and matches the output signal R XD to follow the state of the LBUS pin.

1.5.7.1 Bus Dominant Timer

The Bus Dominant Timer is an internal timer that deac- tivates the L BUS transmitter after approximately 25 milliseconds of dominant state on the LBUS pin. The timer is reset on any recessive LBUS state. The LIN bus transmitter will be re-enabled after a recessive state on the LBUS pin as long as CS is high. Disabling can be caused by the LIN bus being exter- nally held dominant, or by TXD being driven low. Addi- tionally, on the MCP2004, the FAULT pin will be driven low to indicate the Transmitter Off state.

1.5.8 BATTERY (V BB)

This is the Battery Positive Supply Voltage pin.

1.5.9 VOLTAGE REGULATOR ENABLE

OUTPUT (VREN) This is the External Voltage Regulator Enable pin. Open source output is pulled high to VBB in all modes, except Power Down.

1.5.10 EXPOSED THERMAL PAD (EP)

Do not electrically connect, or connect to Vss. TXD In RXD Out LINBUS I/O Thermal Override FAULT/TXE DefinitionExternal Input Driven Output LHV BB OFF H L FAULT, T XD driven low, LINBUS shorted to VBB (Note 1) HHV BB OFF H H OK L L GND OFF H H OK H L GND OFF H H OK, data is being received from the LIN BUS xxV BB ON H L FAULT, Transceiver in thermal shutdown xxV BB x L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays.

DS22230A-page 10  2010 Microchip Technology Inc. NOTES:

 2010 Microchip Technology Inc. DS22230A-page 11 MCP2003/4

2.0 ELECTRICAL CHARACTERISTICS

2.1 Absolute Maximum Ratings†

Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to IEC 61000-4-2, 330 ohm, 150 pF and Tranceiver EMC Test Specifications [2] to [4]. 3: According to AEC-Q100-002/JESD22-A114. 4: According to AEC-Q100-011B. 5: According to AEC-Q100-003/JESD22-A115. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DS22230A-page 12  2010 Microchip Technology Inc.

2.2 DC Specifications

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V BB = 6.0V to 27.0V TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Conditions Power VBB Quiescent Operating Current IBBQ 90 150 µA Operating Mode, bus recessive (Note 1) VBB Transmitter-off Current I BBTO — 75 120 µA Transmitter off, bus recessive (Note 1) VBB Power Down Current I BBPD — 5 15 µA Transmitter off, bus recessive (Note 1) VBB Current with VSS Floating IBBNOGND -1 — 1 mA V BB = 12V, GND to VBB, VLIN =0 - 1 8 V Microcontroller Interface High Level Input Voltage XD, FAULT/TXE) VIH 2.0 — 5.3 V Low Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 — 0.8 V High Level Input Current (TXD, FAULT/TXE) IIH -2.5 — — µA Input voltage = 4.0V Low Level Input Current (TXD, FAULT/TXE) IIL -10 — — µA Input voltage = 0.5V High Level Voltage (VREN) VHVREN -0.3 — V BB+0.3 High Level Output Current (VREN) IHVREN -20 — -10 mA Output voltage = V BB- 0.5V High Level Input Voltage (CS) VIH 2.0 — V BB V Through a current limiting resistor Low Level Input Voltage (CS) VIL -0.3 — 0.8 V High Level Input Current (CS) IIH -10.0 — 10.0 µA Input voltage = 4.0V Low Level Input Current (CS) IIL -5.0 — 5.0 µA Input voltage = 0.5V Low Level Input Voltage (WAKE) VIL VBB – 4.0V — — V Low Level Output Voltage (RXD) VOL ——0 . 4 V I IN = 2 mA High Level Output Current (RXD) IOH -1 — -1 µA V LIN - VBB, VRXD = 5.5V Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). 2: Node has to sustain the current that can flow under this condition; bus must be operational under this condition.

 2010 Microchip Technology Inc. DS22230A-page 13 MCP2003/4 Bus Interface High Level Input Voltage V IH(LBUS) 0.6 V BB — 18 V Recessive state Low Level Input Voltage V IL(LBUS)- 8 — 0 . 4 V BB V Dominant state Input Hysteresis V HYS — — 0.175 V BB VV IH(LBUS) – VIL(LBUS) Low Level Output Current I OL(LBUS) 40 — 200 mA Output voltage = 0.1 V BB, VBB = 12V Pull-up Current on Input I PU(LBUS)5 — 1 8 0 µ A ~ 3 0 k  internal pull-up @ VIH (LBUS) = 0.7 VBB Short Circuit Current Limit I SC 50 — 200 mA (Note 1) High Level Output Voltage V OH(LBUS) 0.9 V BB —V BB V Driver Dominant Voltage V_ LOSUP ——1 . 2 V V BB = 7V, RLOAD = 500 Driver Dominant Voltage V_ HISUP ——2 . 0 V V BB = 18V, RLOAD = 500 Driver Dominant Voltage V_ LOSUP-1K 0.6 — — V V BB = 7V, RLOAD = 1 k Driver Dominant Voltage V_ HISUP-1K 0.8 — — V V BB = 18V, RLOAD = 1 k Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 -0.4 — mA Driver off, VBUS = 0V, VBB = 12V Input Leakage Current (at the receiver during recessive bus level) IBUS_PAS_REC — 12 20 µA Driver off, 8V < VBB < 18V 8V < VBUs < 18V VBUS  VBB Leakage Current (disconnected from ground) IBUS_NO_GND -10 1.0 +10 µA GND DEVICE = VBB, 0V < VBUS < 18V, VBB = 12V Leakage Current (disconnected from VBB) IBUS —— 1 0 µ A V BB = GND, 0 < VBUS < 18V, TA = -40°C to +85°C (Note 2) Receiver Center Voltage V BUS_CNT 0.475 VBB 0.5 VBB

0.525 VBB VV BUS_CNT = (VIL (LBUS) +

VIH (LBUS))/2 Slave Termination R SLAVE 20 30 47 k 

2.2 DC Specifications (Continued)

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 27.0V TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Conditions Note 1: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB). 2: Node has to sustain the current that can flow under this condition; bus must be operational under this condition.

DS22230A-page 14  2010 Microchip Technology Inc.

2.3 AC Specifications

AC CHARACTERISTICS VBB = 6.0V to 27.0V; TA = -40°C to +125°C Parameter Sym Min. Typ. Max. Units Test Conditions Bus Interface – Constant Slope Time Parameters Slope rising and falling edges tslope 3.5 — 22.5 µs 7.3V <= V BB <= 18V Propagation Delay of Transmitter ttranspd — — 4.0 µs ttranspd = max (ttranspdr or ttranspdf) Propagation Delay of Receiver trecpd — — 6.0 µs trecpd = max (trecpdr or trecpdf) Symmetry of Propagation Delay of Receiver rising edge w.r.t. falling edge trecsym -2.0 — 2.0 µs trecsym = max (trecpdf – trecpdr) Symmetry of Propagation Delay of Transmitter rising edge w.r.t. falling edge ttrans- sym -2.0 — 2.0 µs ttranssym = max (ttranspdf - ttranspdr) Time to sample of FAULT/ TXE for bus conflict reporting tfault — — 32.5 µs tfault = max (ttranspd + tslope + trecpd) Duty Cycle 1 @20.0 kbit/sec 39.6 — — %tbit Cbus;Rbus conditions: 1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W THrec(max) = 0.744 x V BB, THdom(max) = 0.581 x VBB, VBB =7.0V-18V; tbit = 50 µs D1 = tbus_rec(min) / 2 x tbit) Duty Cycle 2 @20.0 kbit/sec — — 58.1 %tbit Cbus;Rbus conditions: 1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W THrec(max) = 0.284 x VBB, THdom(max) = 0.422 x VBB, VBB =7.6V-18V; tbit = 50 µs D2 = tbus_rec(max) / 2 x tbit) Duty Cycle 3 @10.4 kbit/sec 41.7 — — %tbit Cbus;Rbus conditions: 1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W THrec(max) = 0.778 x VBB, THdom(max) = 0.616 x VBB, VBB =7.0V-18V; tbit = 96 µs D3 = tbus_rec(min) / 2 x tbit) Duty Cycle 4 @10.4 kbit/sec — — 59.0 %tbit Cbus;Rbus conditions: 1 nF; 1 kW | 6.8 nF; 660W | 10 nF; 500W THrec(max) = 0.251 x VBB, THdom(max) = 0.389 x VBB, VBB =7.6V-18V; tbit = 96 µs D4 = tbus_rec(max) / 2 x tbit) Wake-up Timing Bus Activity Debounce time tBDB 5 20 µs Bus debounce time, 10 µs typical Bus Activity to Vren on tBACTVE 35 150 µs After Bus debounce time, 52 µs typical WAKE to Vren on tWAKE 150 µs Chip Select to Vren on tCSOR — 150 µs Vren floating Chip Select to Vren off tCSPD — 80 µs Vren floating

 2010 Microchip Technology Inc. DS22230A-page 15 MCP2003/4

2.4 Thermal Specifications

Parameter Symbol Typ Max Units Test Conditions Recovery Temperature RECOVERY +140 — C Shutdown Temperature SHUTDOWN +150 — C Short Circuit Recovery Time t THERM 1.5 5.0 ms Thermal Package Resistances Thermal Resistance, 8L-DFN  JA 35.7 — C/W Thermal Resistance, 8L-PDIP JA 89.3 — C/W Thermal Resistance, 8L-SOIC JA 149.5 — C/W Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2003/4 will go into thermal shutdown.

DS22230A-page 16  2010 Microchip Technology Inc.

2.5 Typical Performance Curves

Note: Unless otherwise indicated, VBB = 6.0V to 18.0V, TA = -40°C to +125°C. FIGURE 2-1: TYPICAL IBBQ FIGURE 2-2: TYPICAL IBBPD FIGURE 2-3: TYPICAL IBBTO Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.02 0.04 0.06 0.08 0.1 0.12 0.14 6 7.3 12 14.4 18 VBB (V) Current (mA) -40C 25C 85C 125C 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 6 7.3 12 14.4 18 VBB (V) Current (mA) -40C 25C 85C 125C 0.02 0.04 0.06 0.08 0.1 0.12 6V 7.3V 12V 14.4V 18V VBB (V) Current (mA) -40C 25C 85C 125C

 2010 Microchip Technology Inc. DS22230A-page 17 MCP2003/4

2.6 Timing Diagrams and Specifications

FIGURE 2-4: BUS TIMING DIAGRAM FIGURE 2-5: CS TO V REN TIMING DIAGRAM FIGURE 2-6: BUS TO V REN WAKE TIMING DIAGRAM .95VLBUS 0.5VLBUS TTRANSPDR TRECPDR TTRANSPDF TRECPDF TXD LBUS RXD Internal TXD/RXD Compare FAULT Sampling TFAULT TFAULT FAULT/TXE Output Stable StableStable Match MatchMatch Match Match Hold Value Hold Value 50%50% .50VBB 50%50% 0.0V TCSPD TCSOR CS VREN VBB OFF VREN LBUS .4VBB VBB TBDB + TBACTVE

DS22230A-page 18  2010 Microchip Technology Inc. NOTES:

 2010 Microchip Technology Inc. DS22230A-page 19 MCP2003/4

3.0 PACKAGING INFORMATION

3.1 Package Marking Information

8-Lead PDIP (300 mil) Example: 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN E/P^^256 0948 MCP2003E SN^^0948 256 MCP2003 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 8-Lead DFN (4x4) Example: XXXXXX YYWW NNN XXXXXX 2004 0948 256 E/MD^^3e

DS22230A-page 20  2010 Microchip Technology Inc. 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2

 2010 Microchip Technology Inc. DS22230A-page 21 MCP2003/4 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2

DS22230A-page 22  2010 Microchip Technology Inc. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

 2010 Microchip Technology Inc. DS22230A-page 23 MCP2003/4 /g49/g82/g87/g72/g86/##58Hb981034091b194e41ef5193e7127dfd3 /g56/g81/g76/g87/g86 /g44/g49/g38/g43/g40/g54 /g49/g88/g80/g69/g72/g85/;#23#23#23/g82/g73/;#23#23#23/g51/g76/g81/g86 /g49 /##52H929f5141f4575eca8d5e4ef21356227f /g50/g89/g72/g85/g68/g79/g79/;#23#23#23/g47/g72/g81/g74/g87/g75 /g39 /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##43Hd27e308598cf1f8bcf9e336036f3f448/##46H7a539460a8268e5915c0973dbb05dce1/##52H929f5141f4575eca8d5e4ef21356227f /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##43Hd27e308598cf1f8bcf9e336036f3f448/##4CH2eb0c8ba15de4cce8fa3c169622f8e93/##49H7d5c40f4f2638829db6b707b7e9400a3 /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##46H7a539460a8268e5915c0973dbb05dce1/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23 N NOTE 1 D 12 3 A L b e E eB c

DS22230A-page 24  2010 Microchip Technology Inc. /g49/g82/g87/g72/g86/##58Hb981034091b194e41ef5193e7127dfd3 /g56/g81/g76/g87/g86 /g48/g44/g47/g47/g44/g48/g40/g55/g40/g53/g54 /g49/g88/g80/g69/g72/g85/;#23#23#23/g82/g73/;#23#23#23/g51/g76/g81/g86 /g49 /##52H929f5141f4575eca8d5e4ef21356227f /g50/g89/g72/g85/g68/g79/g79/;#23#23#23/g43/g72/g76/g74/g75/g87 /g36 /g177 /g177 /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##4FHabe68123f3cb4e14e0d59c97044fedf7/##49H7d5c40f4f2638829db6b707b7e9400a3 /g48/g82/g79/g71/g72/g71/;#23#23#23/g51/g68/g70/g78/g68/g74/g72/;#23#23#23/g55/g75/g76/g70/g78/g81/g72/g86/g86 /g36/##40He56442409eb2e77ad61dd1c271fabe6c /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##40He56442409eb2e77ad61dd1c271fabe6c/##49H7d5c40f4f2638829db6b707b7e9400a3 /g177 /g177 /g48/g82/g79/g71/;#23#23#23/g39/g85/g68/g73/g87/;#23#23#23/g36/g81/g74/g79/g72/;#23#23#23/g55/g82/g83/g68 /##49H7d5c40f4f2638829db6b707b7e9400a3/g131 /g177 /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##49H7d5c40f4f2638829db6b707b7e9400a3/g131 /g48/g82/g79/g71/;#23#23#23/g39/g85/g68/g73/g87/;#23#23#23/g36/g81/g74/g79/g72/;#23#23#23/g37/g82/g87/g87/g82/g80/g69 /##49H7d5c40f4f2638829db6b707b7e9400a3/g131 /g177 /;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##49H7d5c40f4f2638829db6b707b7e9400a3/g131 D N e E NOTE 1 12 3 b A L c h h φ β α /g48/g76/g70/g85/g82/g70/g75/g76/g83 /g55/g72/g70/g75/g81/g82/g79/g82/g74/g92 /g39/g85/g68/g90/g76/g81/g74 /g38/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##46H7a539460a8268e5915c0973dbb05dce1/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/;#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23#23/##49H7d5c40f4f2638829db6b707b7e9400a3/##4FHabe68123f3cb4e14e0d59c97044fedf7/g37

 2010 Microchip Technology Inc. DS22230A-page 25 MCP2003/4

DS22230A-page 26  2010 Microchip Technology Inc. NOTES:

 2010 Microchip Technology Inc. DS22230A-page 27 MCP2003/4 APPENDIX A: REVISION HISTORY Revision A (March 2010)

• Original Release of this Document.

DS22230A-page 28  2010 Microchip Technology Inc. NOTES:

 2010 Microchip Technology Inc. DS22230A-page 29 MCP2003/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . PART NO. X /XX PackageTemperature Range Device Device: MCP2003: LIN Transceiver with Voltage Regulator MCP2003T: LIN Transceiver with Voltage Regulator (Tape and Reel) (DFN and SOIC) MCP2004: LIN Transceiver with Voltage Regulator MCP2004T: LIN Transceiver with Voltage Regulator (Tape and Reel) (DFN and SOIC) Temperature Range: E = -40°C to +125°C Package: MD = Plastic Micro Small Outline (4x4), 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC, (150 mil Body), 8-lead Examples: a) MCP2003-E/MD: Extended Temperature, 8L-DFN pkg. b) MCP2003-E/P: Extended Temperature, 8L-PDIP pkg. c) MCP2003-E/SN: Extended Temperature, 8L-SOIC pkg. d) MCP2003T-E/MD: Tape and Reel, Extended Temperature, 8L-DFN pkg. e) MCP2003T-E/SN: Tape and Reel, Extended Temperature, 8L-SOIC pkg. a) MCP2004-E/MD: Extended Temperature, 8L-DFN pkg. b) MCP2004-E/P: Extended Temperature, 8L-PDIP pkg. c) MCP2004-E/SN: Extended Temperature, 8L-SOIC pkg. d) MCP2004T-E/MD: Tape and Reel, Extended Temperature, 8L-DFN pkg. e) MCP2004T-E/SN: Tape and Reel, Extended Temperature, 8L-SOIC pkg.

DS22230A-page 30  2010 Microchip Technology Inc. NOTES:

 2010 Microchip Technology Inc. DS22230A-page 31 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-080-5 Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improvin g the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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