MCM8A10 MOTOROLA | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
The MCM8A10 is an 8M bit static random access memory module organized as 1,048,576 words of 8 bits. The module is offered in a 72–lead single in–line memory module (SIMM). Eight MCM6227B fast static RAMs, packaged in 28–lead SOJ packages are mounted on a printed circuit board along with eight decoupling capacitors. The MCM6227B is organized as 1,048,576 words of 1 bit. Static design elimi- nates the need for external clocks or timing strobes, while CMOS circuitry re- duces power consumption and provides for greater reliability. The MCM8A10 is equipped with a chip enable (E) and eight separate write enable (W0 – W7) inputs, allowing for greater system flexibility.
- Single 5 V ± 5% Power Supply
- Fast Access Times: 15 ns
- Three–State Outputs
- Fully TTL Compatible
- High Board Density SIMM Package
- Bit Operation: Eight Separate Write Enables, One for Each Bit
- High Quality Six–Layer FR4 PWB with Separate Internal Power and Ground Planes For proper operation of the device, VSS must be connected to ground. PIN NAMES This document contains information on a new product. Specifications and information herein are subject to change without notice. Order this document by MCM8A10/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA MCM8A10 PIN ASSIGNMENT TOP VIEW 72-LEAD SIMM – CASE TBD VCC VSS A11 VCC DAISY VSS VCC VSS VCC A10 VSS DAISY VCC PD1 38 VCC A21 A19 VCC A17 A15 VSS A13 VCC PD0 PD2 VSS VSS A20 VSS A18 A16 A14 VCC A12 VSS VCC E VSS 10/30/96 Motorola, Inc. 1996
A0 – A19 E W E A0 – A19 1M x 1 FUNCTIONAL BLOCK DIAGRAM 1M x 8 MEMORY MODULE D Q A0 – A19 E WW4 1M x 1 D Q A0 – A19 E WW5 1M x 1 D Q A0 – A19 E WW6 1M x 1 D Q A0 – A19 E WW7 1M x 1 D Q A0 – A19 E WW1 1M x 1 D Q A0 – A19 E WW2 1M x 1 D Q A0 – A19 E WW3 1M x 1 D Q PD0 — Open PD1 — V SS PD2 — Open
E W Mode I/O Pin Cycle Current H X Not Selected High–Z — ISB1 , ISB2 L H Read D out Read ICCA L L Write High–Z Write ICCA NOTE: H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit Power Supply Voltage Relative to VSS VCC – 0.5 to 7.0 V Voltage Relative to VSS for Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 8.8 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Storage Temperature Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.75 5.25 V Input High Voltage VIH 2.2 VCC +0.3** V Input Low Voltage VIL – 0.5* 0.8 V *VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — ± 1 µA Output Leakage Current (E = VIH, Vout = 0 to VCC ) Ilkg(O) — ± 1 µA AC Active Supply Current (Iout = 0 mA, VCC = max) ICCA — 920 mA AC Standby Current (VCC = max, E = VIH, f ≤ fmax ) ISB1 — 320 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 40 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Symbol Typ Max Unit Input Capacitance Address Inputs E W C in 42 pF Input and Output Capacitance D, Q C in, Cout 10 13 pF This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to these high–impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
- W is high for read cycle.
- Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
- All timings are referenced from the last valid address to the first transitioning address.
- Addresses valid prior to or coincident with E
- At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device.
- Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
- This parameter is sampled and not 100% tested.
- Device is continuously selected (E ≤ VIL).
provides data later than that time. Figure 1. AC Test Loads
A (ADDRESS) Q (DATA OUT) tAVAV tAXQX tAVQV DATA VALIDPREVIOUS DATA VALID READ CYCLE 1 (See Notes 1, 2, and 8) tAVAV tELQV tELQX tEHQZ tAVQV tELICCH tEHICCL ISB Q (DATA OUT) A (ADDRESS) E (CHIP ENABLE) SUPPLY CURRENT ICC HIGH–Z DATA VALID READ CYCLE 2 (See Note 4)
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) P Sb l MCM8A10–15 Ui NParameter Symbol Min Max Unit Notes Write Cycle Time tAVAV 15 — ns 3 Address Setup Time tAVWL 0 — ns Address Valid to End of Write tAVWH 12 — ns Write Pulse Width tWLWH, tWLEH 12 — ns Data Valid to End of Write tDVWH 7 — ns Data Hold TIme tWHDX 0 — ns Write Low to Data High–Z tWLQZ 0 6 ns 4, 5, 6 Write High to Output Active tWHQX 5 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. tAVWH tWLQZ tWHAX tDVWH A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) DATA VALID HIGH–Z HIGH–Z tAVAV tAVWL tWLEH tWLWH tWHDX tWHQX WRITE CYCLE 1 (W Controlled See Notes 1 and 2)
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) P Sb l MCM8A10–15 Ui NParameter Symbol Min Max Unit Notes Write Cycle Time tAVAV 15 — ns 3 Address Setup Time tAVEL 0 — ns Address Valid to End of Write tAVEH 12 — ns Enable to End of Write tELEH, tELWH 10 — ns 4, 5 Write Pulse Width tWLEH 12 — ns Data Valid to End of Write tDVEH 7 — ns Data Hold Time tEHDX 0 — ns Write Recovery Time tEHAX 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. tEHDX tDVEH tEHAXtELWHtAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tELEH tWLEH WRITE CYCLE 2 (E Controlled See Notes 1 and 2)
ORDERING INFORMATION
(Order by Full Part Number) MCM 8A10 XX XX Full Part Number — MCM8A10SG15 Package (SG = Gold Pad SIMM) Speed (15 = 15 ns)Motorola Memory Prefix Part Number
72–LEAD SIMM CASE TBD Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P.O. Box 5405; Denver, Colorado 80217. 1–800–441–2447 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 INTERNET : http://Design–NET.com 51 Ting Kok R oad, Tai Po, N.T., Hong Kong. 852–26629298 MCM8A10/D /C0042/C0077/C0067/C0077/C0056/C0065/C0049/C0048/C0047/C0068/C0042