MCM72F6 MOTOROLA | Alldatasheet

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MCM72F6 •MCM72F7 MOTOROLA FAST SRAM 512KB and 1MB Synchronous Fast Static RAM Module The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7 (1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual– in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit flow–through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable ) are clock (K) controlled through positive–edge–triggered noninverting reg- isters. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (W ) allows writes to either individual bytes or to both bytes.

  • Single 3.3 V + 10%, – 5% Power Supply
  • Plug and Pin Compatibility with 2MB and 4MB
  • Multiple Clock Pins for Reduced Loading
  • All Inputs and Outputs are LVTTL Compatible
  • Byte Write Capability
  • Fast SRAM Access Times: 9/10/12 ns
  • Decoupling Capacitors for Each Fast Static RAM
  • High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
  • Amp Connector, Part Number: 390064–4
  • 168–Pin DIMM Module Order this document by MCM72F6/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA MCM72F6 MCM72F7 168–LEAD DIMM CASE 1115J–01 TOP VIEW REV 3 11/24/97  Motorola, Inc. 1997

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM 64K x 18 ADSC SBa G ADSP SE1 A0 – A15 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW VDD VSS DQ0 – DQ7 DQ8 – DQ15 DP1 DP0 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ16 – DQ23 DQ24 – DQ31 DP3 DP2 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ32 – DQ39 DQ40 – DQ47 DP5 DP4 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ48 – DQ55 DQ56 – DQ63 DP7 DP6 MCM72F6 BLOCK DIAGRAM

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM 64K x 18 ADSC SBa G ADSP SE1 A0 – A15 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW VDD VSS DQ0 – DQ7 DQ8 – DQ15 DP1 DP0 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQa0 – DQa7 SE2 DQb0 – DQb7 SE3 DQb8 DQa8 SW VDD VSS 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ16 – DQ23 DQ24 – DQ31 DP3 DP2 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ32 – DQ39 DQ40 – DQ47 DP5 DP4 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW 64K x 18 ADSC SBa G SE1 A0 – A15 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ48 – DQ55 DQ56 – DQ63 DP7 DP6 MCM72F7 BLOCK DIAGRAM

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM PIN ASSIGNMENT 168–LEAD DIMM TOP VIEW 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQ18 VSS DQ16 DQ15 VSS DQ13 DQ11 VSS DQ9 DP0 VDD DQ6 DQ4 VSS DQ2 DQ0 VSS NC NC VSS A15 A13 VDD A11 VSS VSS ADSP VSS VSS VSS VDD VSS DQ19 VSS DQ17 DP1 VDD DQ14 DQ12 VSS DQ10 DQ8 VSS DQ7 DQ5 VSS DQ3 DQ1 VDD NC NC VSS NC A14 VSS A12 A10 VSS VDD VSS VSS VSS VSS VSS 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 VSS DP7 DQ61 VSS DQ59 DQ57 VSS DP6 DQ54 VDD DQ52 DQ50 VSS DQ48 DQ47 VSS DQ45 DQ43 VSS DQ41 DP4 VDD DQ38 DQ36 VSS DQ34 DQ32 VSS VSS DQ31 DQ29 VSS DQ27 DQ25 VSS DP2 DQ22 VDD DQ20 VSS DQ63 DQ62 VDD DQ60 DQ58 VSS DQ56 DQ55 VSS DQ53 DQ51 VSS DQ49 DP5 VDD DQ46 DQ44 VSS DQ42 DQ40 VSS DQ39 DQ37 VSS DQ35 DQ33 VSS VSS DP3 DQ30 VDD DQ28 DQ26 VSS DQ24 DQ23 VSS DQ21

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type Description 72, 145, 146, 148, 149, 151, 152, 154, 155 A0 – A15 Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times.

156 ADSP Input Synchronous Addresss Status Controller: Initiates read, write, or chip

deselect cycle. 15, 31, 44, 86, 92, 105, 121, 134 DP0 – DP7 Synchronous Parity Data Inputs/Outputs. 101, 102, 104, 107, 108, 110, 111, 115, 116, 118, 119, 122, 124, 125, 127, 128, 130, 131, 133, 136, 137, 139, 140 DQ0 – DQ63 I/O Synchronous Data Inputs/Outputs. 167, 83 E0, E1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. E1 is only used on 1MB module. 166, 82 G0 , G1 Input Asynchronous Output Enable Input: Low — enables output buffer. High — DQx pins are high impedance. G1 is only used on 1MB module. 29, 74, 113, 158 K0 – K3 Input Clock: This signal registers the address, data in, and all control signals except G and LBO. 76, 77, 79, 80, 160, 161, 163, 164 W0 – W7 Input Synchronous Byte Write Inputs: x refers to the byte being written (byte a, b). SGW overrides SBx. 106, 123, 135, 147, 165 VDD Supply Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules. 88, 91, 97, 100, 103, 109, 112, 114, 117, 120, 126, 129, 132, 138, 141, 144, 150, 153, 157, 159, 162, 168 VSS Supply Ground. 58, 59, 61, 142, 143 NC No Connection: There is no connection to the chip. DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3 and 4) Next Cycle Address Used E ADSP G DQx WRITE Deselect None 1 0 X High–Z X Begin Read External Address 0 0 0 DQ Read Read Current X 1 1 High–Z Read Read Current X 1 0 DQ Read Begin Write External 0 0 X High–Z Write Write Current X 1 X High–Z Write NOTES: 1. X = don’t care, 1 = logic high, 0 = logic low. 2. Write is defined as any Wx low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX ) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VDD – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout – 0.5 to VDD + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation MCM72F6 MCM72F7 PD 4.6 9.2 W Ambient Temperature TA 0 to 70 °C Die Temperature TJ 110 °C Temperature Under Bias Tbias – 10 to + 85 °C Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VDD 3.135 3.6 V Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5* 0.8 V *V IL ≥ – 2.0 V for t ≤ tKHKH /2. DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (0 V ≤ Vin ≤ VDD ) Ilkg(I) — ± 1.0 µA Output Leakage Current (0 V ≤ Vin ≤ VDD ) Ilkg(O) — ± 1.0 µA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V POWER SUPPLY CURRENTS Parameter Symbol Min Max Unit AC Supply Current (Device Selected, All Outputs Open, MCM72F6DG9 Cycle Time ≥ tKHKH min) MCM72F6DG10 MCM72F6DG12 MCM72F7DG9 MCM72F7DG10 MCM72F7DG12 IDDA — 900 860 840 1800 1720 1680 mA CMOS Standby Supply Current (Deselected, MCM72F6DG9 Clock (K) Cycle Time ≥ tKHKH , All Inputs Toggling at MCM72F6DG10 CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) MCM72F6DG12 MCM72F7DG9 MCM72F7DG10 MCM72F7DG912 ISB1 — 440 400 380 880 800 760 mA Clock Running Supply Current (Deselected, MCM72F6DG9 Clock (K) Cycle Time ≥ tKHKH , All Other Inputs MCM72F6DG10/12 Held to Static CMOS Levels Vin ≤ VSS + 0.2 V MCM72F7DG9 or ≥ VDD – 0.2 V) MCM72F7DG10/12 ISB2 — 160 140 320 280 mA MCM72F6 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance W , K Other Inputs C in — pF I/O Capacitance C I/O — 19 pF This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated volt- ages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up.

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM MCM72F7 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance W , K E, G Other Inputs C in — pF I/O Capacitance C I/O — 28 pF MASS (Periodically Sampled Rather Than 100% Tested) Parameter Max Unit MCM72F6 16 g MCM72F7 20 g AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3 and 4) P Sb l MCM72F6–9 MCM72F7–9 MCM72F6–10 MCM72F7–10 MCM72F6–12 MCM72F7–12 Ui NParameter Symbol Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 12 — 15 — 16.6 — ns Clock Access Time tKHQV — 9 — 10 — 12 ns Output Enable to Output Valid tGLQV — 5 — 5 — 6 ns Clock High to Output Active tKHQX1 0 — 0 — 0 — ns 5 Clock High to Output Change tKHQX2 3 — 3 — 3 — ns 5 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 5 Output Disable to Q–High–Z tGHQZ — 5 — 5 — 6 ns 5, 6 Clock High to Q–High–Z tKHQZ 3 5 3 5 3 6 ns 5, 6 Clock High Pulse Width tKHKL 4 — 5 — 6 — ns Clock Low Pulse Width tKLKH 4 — 5 — 6 — ns Setup Times Address ADSP Data In Write Chip Enable tAVKH tADKH tDVKH tWVKH tEVKH Hold Times: Address ADSP , ADSC, ADV Data In Write Chip Enable tKHAX tKHADX tKHDX tKHWX tKHEX NOTES: 1. In setup and hold times, write refers to either any SBx and SW or SGW is low. 2. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 3. All read and write cycle timings are referenced from K or G. 4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle. 5. This parameter is sampled and not 100% tested. 6. Measured at ± 200 mV from steady state.

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM OUTPUT Z0 = 50 Ω 50 Ω VL = 1.5 V TIMING LIMITS The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load

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MCM72F6 •MCM72F7 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 168–LEAD DIMM CASE 1115J–01 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉ É É ÉÉ ÉÉ É É ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ É É É É É É É É É É ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ É É É É É É ÉÉ ÉÉ CL M0.016 (0.4) A FRONT VIEW VIEW C VIEW D D6 VIEW B (DATUM PLANE C) VIEW D ÉÉ ÉÉ É É É É É É b168X L168X L1168X 162X e M0.004 (0.1) CA B 11 40 4110 NOTE 5 NOTE 4 E1 NOTE 6 E SIDE VIEW R K VIEW B 16885 COMPONENT AREA A B M0.004 (0.1) CA B C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALLIZATION. 4. DIMENSIONS E AND A1 DEFINE A DOUBLE–SIDED MODULE. 5. DIMENSION E2 DEFINES OPTIONAL SINGLE–SIDED MODULE 6. STRAIGHTNESS CALLOUT APPLIES TO TAB AREA ONLY. 7. D5 DIMENSION DEFINES SLOT END AND EDGE OF COMPONENT AREA. R VIEW C 2X 2X 2X P 2X A4 M0.004 (0.1) CA B M0.004 (0.1) CA B 94 95 D4D4 VIEW C R K VIEW A M0.004 (0.1) CA B M0.15 (0.006) CA B DIM MIN MAX MIN MAX MILLIMETERSINCHES A 1.095 1.105 27.81 28.07 A2 0.118 BSC 3.00 BSC A3 0.700 BSC 17.78 BSC A4 0.154 0.161 3.90 4.10 A5 0.118 0.128 3.00 3.25 b 0.037 0.041 0.95 1.05 D1 5.245 5.255 133.22 133.48 D2 5.014 BSC 127.35 BSC D3 1.700 BSC 43.18 BSC D4 0.250 BSC 6.35 BSC D6 0.125 BSC 3.175 BSC e 0.050 BSC 1.27 BSC E1 0.046 0.054 1.17 1.37 K 0.075 0.083 1.90 2.10 P 0.114 0.122 2.90 3.10 BACK VIEW COMPONENT AREA

MCM72F6 •MCM72F7 MOTOROLA FAST SRAM Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, P .O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Motorola Fax Back System – US & C anada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com/mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM72F6/D◊