MCM6229AWJ45

MCM6229A MOTOROLA | Alldatasheet

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SEMICONDUCTOR TECHNICAL DATA ae MCM6229A 256K x 4 Bit Static Random Access Memory The MCM6229A Is a 1,048,576 bit static random access memory organized LEY as 262,144 words of 4 bits, fabricated using high-performance silicon-gate WJ PACKAGE CMOS technology. Static design eliminates the need for external clocks or timing 400 MIL SOU strobes, while CMOS circuitry reduces power consumption and provides for CASE 810-03 greater reliability. The MCM6229A is equipped with both chip enable (E) and output enable @) pins, allowing for greater system flexibility and eliminating bus contention prob- . lems. PIN ASSIGNMENT The MCM6229A Is available in 400 mil, 28-lead surface-mount SOJ pack- - ages. 5 aofjie 28{] Yoo Single 5 V + 10% Power Supply : 9 Ai[]2 a7{} Ai7 « Fast Access Times: 20, 25, 35, and 45 ns < no[}3 26[} ate « Equal Address and Chip Enable Access Times we oy ror ast] ats « All inputs and Outputs are TTL Compatible < f + Three-State Outputs NN Cs mls af) A «Low Power Operation: 170/150/140/130 mA Maxi ads oj} ase 2a{] ats ce) € ot a6 (]7 zai} ate G 9) ae ar(] 8 ai] att BLOCK Q *) a asf] 9 20[] NC ss > a Ae 49 [|10 191] bas | ‘ hi aw ato G11 181] paz M ee ( l <— | 6 oy EQ 17{] pat ar maa ‘ 3 alls 160) 020 As i> Vgg {}14 1s) Ww K+ 1 now MEMORY MATRIX AS 1244 vECODER 512 ROWS x KS | 2048 COLUMNS Ato > »—st [ewnawes | a AS e+] W eee eeeeeeseeeeeee es Write Enable M = G oeeeecceeesereeeee Output Enable

4 EB voecccccesseeeeeeeeess Chip Enable

=| NC oo... esse eeeeeees No Connection pa Le = Vog «sss. ss++.5V Power Supply DATA ee CONTROL vo tel AAAAAAAAA ii< AQ AIS AI2 Alt AIG AO AI7 AIS AI4 — fd 6 1_) Cy

LE [6 | w [ Wode [ vorin T cyete [Curent | [ef [rood oa] Feat | con] [ex P| wie [on we [toca] H = High, L = Low, X = Don't Care ABSOLUTE MAXIMUM RATINGS (See Note) inputs against damage due to high static volt- Power Supply Voltage Relative to Vgg, ages or electric fields; however, it is advised ~ " 7 that norma! precautions be taken to avoid ‘erage eave 10 Vgs for Any Pin 06 10 Voc +05 application of any voltage higher than maxi- mum rated voltages to these high-impedance This CMOS memory circuit has been de- - 7 y shown in the tables, after thermal equilibrium Temperature Under Bias has been established, The circult is in a test Operating Temperature socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for ‘extended periods of time could affect device reliability, DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS fo arareter Smet iin [Mae | Oni | *ViL (min) =~ 0.5 V de; Vj_ (min) = - 2.0 V ac (pulse width < 20 ns). "VI (max) = Veg + 0.3 V de; Vjy (max) = Voc + 2 V ac (pulse width < 20 ns), DC CHARACTERISTICS AND SUPPLY CURRENTS ee input Leakage Current (All Inputs, Vin = 0 to Voc) katt) [- [= [# [oe | AC Active Supply Current {lout = 0 mA, Voc = max) loca MCM6229A-20: tayay = 20 ns 140 | 170 MCM6229A-25: tavay = 25 ns 120 | 150 MCM6229A-35: tayay = 35 ns 110 | 140 MCM6229A--45: tavay = 45 ns 100 130 CMOS Standby Current (E = Voc - 0.2 V, Vin Vgg + 0.2V Igp2 15 | mA or 2 Voc - 0.2 V, Voc = max, f= 0 MHz) Output Low Voitage (Io = + 8.0 mA) [| vo | - | — [oa [vy | “Typical measurements are taken at 25°C, Voc = 5 V.

CAPACITANCE (f= 1,0 MHz, dV = 3.0 V, Ta = 25°C, Periodically ‘Sampled Rather Than 100% Tested) re es ee Input Capacitance All Inputs Except Clocks andDQ| — Cin pF E.G, and W Cok inpuvOvtput Capactance =) AC OPERATING CONDITIONS AND CHARACTERISTICS (Vcc = 5.0 V+ 10%, Ta = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE TIMING (See Notes 1 and 2) | cum | sat Tee [ee ef [ [a ant | ne symbot_['win [ mex [win [ wax win [ wax | win | Max | Road Oyele Time [ww [= — fe [— le] Ts] | fs | wa f-|*|-[s{[-[s[-[;se[=] | Supaodteonaten cane | wax [@f-{s|-]fs[—-[*|-[= | | Dapatntietwnoaparcme | vax fof —1et- >|[— e|— |= | | cairn ouanone [eae fot» fe] ofo[ ele | | [sar Cupaeraverieneounarinz | tenoz | o |e |e | [> | 2 [o | 6 | we | sor | uo |? [—- [fe [-fef[-Je[-[=T | enon |— | [-[s[-]s][-Ts ts [ | NOTES: 1. Wis high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low. 5. Atany given voltage and temperature, tEHQz maxis less than teL@x min, and tqHQz max is less than tgLQx min, both for a given device and from device to device. 6. Transition is measured + 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100%. tested. 8. Device is continuously selected (E < ViL, G < VIL). AC TEST LOADS TIMING LIMITS The table of timing values shows elther a +5V minimum or a maximum limit for each param- ater, input requirements are specified from OUTPUT- 4802 the extemal system point of view. Thus, ad- OUTPUT. dress setup time is shown as a minimum + %= 02 Ry = 500 258.0 since the systam must supply at least that

5 PF much time (even though most dovices do not

VL=15V require it). On the other hand, responses from ae the memory are specified from the device - point of view. Thus, the access time is shown . as a maximum since the device never pro- Figure 1A Figure 1B vides data later than that time.

READ CYCLE 1 (See Notes 1, 2, and 8) taVAV A (ADDRESS) taxax: Q (DATA OUT) PREVIOUS DATA VALID DATA VALID READ CYCLE 2 (See Note 8) ——— tavay teLav E (CHIP ENABLE) teHaz & (OUTPUT ENABLE} So f a comain f= XXX) wane tavav L 'ELICCH tEHICCL- SUPPLY CURRENT Isa

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) | emma | ayo | im = ea om | ae | Write Pulse Width tWLWH, = 17 ns tWLEH | ecovery Time awn |e f= fe {f-{fe[-~Tet-{t=J | NOTES: 1. Awrite occurs during the overlap of E tow and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power: ‘supplies as weil as minimization or elimination of bus conten- tion conditions during read and write cycles. 3. It G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured + 500 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, twLqz max is less than twHaX min both for a given device and from device tc device. WRITE CYCLE 1 (W Controlled See Notes 1, 2, and 3) taVAV ‘WHAX E (CHIP ENABLE} W (WRITE ENABLE} KXXXKXOOK own RX D (DATA IN) OAAN AKAKAAAADAAAAS DATAVAUD KAKAKAA Le ‘wioz ‘WHDX O(DATACUT) HIGH-Z HIGH-Z

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3) Parameter [min [mex [ win [ox [win [tax | win [mor | Notes wav | 2 | — [a [=e [Te [- Te [| Address Setup Time | we | o [= [oo [=e t-Tel-TeT aes aiawoenservine [wer | © | — [wv [-}=}t-la[-[~« [| Enable to End of Write tELEH, 15 17 tELWH JwetePuowie [men [8 [Pw |e l[—-fey-[e | [paavenawendcrwie [oven | [= [wo [—-]*]-|=}-[@] | jpaerodTing | enox [oo fe [-fe[=fe|-fTel | [Write RecoveyTine | tewax [oo [foe [-[e}-l[ol-fel | NOTES: 1. Awrite occurs during the overlap of E low and W low. 2, Product sensitivities to noise require proper grounding and decoup ling of power supplies as wall as minimization or elimination of bus contan- tion conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. IE goes low coincident with or after W goes low, the output will remain in a high-impedance state. 6. If E goes high coincident with or before W goes high, the output will remain in a high-impedance state. WRITE CYCLE 2 (E Controlled See Notes 1, 2, and 3) tAVAV E (CHIP ENABLE) F | tAVEL tELWH HEHAX ‘WLEH W (WRITE ENABLE) 'DVEH pommen KXXXXXXXXXXXXXAKMKAK oA KXXXKK) LAD ALD D/SIVAALDAALDDAAALVA VAN AV AAV AN 'EHDX Q {DATA OUT) aL a

ORDERING INFORMATION

(Order by Full Part Number) ee Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns, 45 = 45 ns) Package (WJ = 400 mil SOJ) Full Part Numbers — MCM6229AWJ20 MCM6229AWJ20R2 MCM6229AWJ25 MCM6229AWJ25R2, MCM6229AWJ35 MCM6229AWJ35R2 MCM6229AWU45, MCM6229AWJ45R2