MCM6227B MOTOROLA | Alldatasheet
Document overview
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Technical content
The MCM6227B is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227B is each equipped with a chip enable (E ) pin. This feature pro- vides reduced system power requirements without degrading access time per- formance. The MCM6227B is available in 300 mil and 400 mil, 28–lead surface–mount SOJ packages.
- Single 5 V ± 10% Power Supply
- Fast Access Times: 15/17/20/25/35 ns
- Equal Address and Chip Enable Access Times
- Input and Output are TTL Compatible
- Three–State Output
- Low Power Operation: 115/110/105/100/95 mA Maximum, Active AC BLOCK DIAGRAM AA A A A A AA A AAA A A A A A A MEMORY MATRIX
512 ROWS x
A A E W Order this document by MCM6227B/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT MCM6227B WJ PACKAGE
400 MIL SOJ
CASE 810–03 A A A A A A NC A A A A Q W VSS VCC A A A A A NC* A A A A D A PIN NAMES E J PACKAGE
300 MIL SOJ
CASE 810B–03 *If not used for no connect, then do not ex- ceed voltages of – 0.5 to VCC + 0.5 V. This pin is used for manufacturing diag- nostics. REV 3 10/31/96 Motorola, Inc. 1994
E W Mode I/O Pin Cycle Current H X Not Selected High–Z — ISB1 , ISB2 L H Read D out Read ICCA L L Write High–Z Write ICCA H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit Power Supply Voltage Relative to VSS VCC – 0.5 to 7.0 V Voltage Relative to VSS for Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.1 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Storage Temperature Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC +0.3** V Input Low Voltage VIL – 0.5* 0.8 V *VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — ± 1 µA Output Leakage Current (E = VIH, Vout = 0 to VCC ) Ilkg(O) — ± 1 µA AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227B–15: tAVAV = 15 ns MCM6227B–17: tAVAV = 17 ns MCM6227B–20: tAVAV = 20 ns MCM6227B–25: tAVAV = 25 ns MCM6227B–35: tAVAV = 35 ns ICCA 115 110 105 100 mA AC Standby Current (VCC = max, E = VIH, f ≤ fmax ) MCM6227B–15: tAVAV = 15 ns MCM6227B–17: tAVAV = 17 ns MCM6227B–20: tAVAV = 20 ns MCM6227B–25: tAVAV = 25 ns MCM6227B–35: tAVAV = 35 ns ISB1 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 5 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to these high–impedance circuits. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
- W is high for read cycle.
- Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
- All timings are referenced from the last valid address to the first transitioning address.
- Addresses valid prior to or coincident with E
- At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device.
- Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
- This parameter is sampled and not 100% tested.
- Device is continuously selected (E
provides data later than that time. Figure 1. AC Test Loads
READ CYCLE 1 (See Notes 1, 2, and 8) A (ADDRESS) Q (DATA OUT) tAVAV tAXQX tAVQV DATA VALIDPREVIOUS DATA VALID READ CYCLE 2 (See Note 4) tAVAV tELQV tELQX tEHQZ tAVQV tELICCH tEHICCL ISB Q (DATA OUT) A (ADDRESS) E (CHIP ENABLE) SUPPLY CURRENT ICC HIGH–Z DATA VALID
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6227B–15 6227B–17 6227B–20 6227B–25 6227B–35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 15 — 17 — 20 — 25 — 35 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 14 — 15 — 17 — 20 — ns Write Pulse Width tWLWH, tWLEH 12 — 14 — 15 — 17 — 20 — ns Data Valid to End of Write tDVWH 7 — 8 — 8 — 10 — 11 — ns Data Hold TIme tWHDX 0 — 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 6 — 7 — 7 — 8 — 8 ns 4, 5, 6 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — 5 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1 and 2) tAVWH tWLQZ tWHAX tDVWH A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) DATA VALID HIGH–Z HIGH–Z tAVAV tAVWL tWLEH tWLWH tWHDX tWHQX
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6227B–15 6227B–17 6227B–20 6227B–25 6227B–35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 15 — 17 — 20 — 25 — 35 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 14 — 15 — 17 — 20 — ns Enable to End of Write tELEH, tELWH 10 — 11 — 12 — 15 — 20 — ns 4, 5 Write Pulse Width tWLEH 12 — 14 — 15 — 17 — 20 — ns Data Valid to End of Write tDVEH 7 — 8 — 8 — 10 — 11 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. WRITE CYCLE 2 (E Controlled See Notes 1 and 2) tEHDX tDVEH tEHAXtELWHtAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tELEH tWLEH
ORDERING INFORMATION
(Order by Full Part Number) Motorola Memory Prefix Part Number Package (J = 300 mil SOJ, WJ = 400 mil SOJ) Full Part Numbers — MCM6227BJ15 MCM6227BJ15R2 MCM6227BWJ15 MCM6227BWJ15R2 MCM6227BJ17 MCM6227BJ17R2 MCM6227BWJ17 MCM6227BWJ17R2 MCM6227BJ20 MCM6227BJ20R2 MCM6227BWJ20 MCM6227BWJ20R2 MCM6227BJ25 MCM6227BJ25R2 MCM6227BWJ25 MCM6227BWJ25R2 MCM6227BJ35 MCM6227BJ35R2 MCM6227BWJ35 MCM6227BWJ35R2 Shipping Method (R2 = Tape and Reel, Blank = Rails) MCM 6227B XX XX XX Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns)
28 LEAD
CASE 810–03 18.29 10.04 3.26 0.39 2.24 0.67 0.89 0.76 11.05 9.15 0.77 MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D E F G H K L M N P R S 0° 5° 0° 5°
1.27 BSC
0.64 BSC
0.050 BSC
0.025 BSC
18.54 10.28 3.75 0.50 2.48 0.81 0.50 1.14 1.14 11.30 9.65 1.01 0.720 0.395 0.128 0.015 0.088 0.026 0.035 0.030 0.435 0.360 0.030 0.730 0.405 0.148 0.020 0.098 0.032 0.020 0.045 0.045 0.445 0.380 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. PACKAGE DIMENSIONS CASE 810B–03 MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D E F G H K L M N P R S 0° 10° 0° 10° 18.29 7.50 3.26 0.39 2.24 0.67 0.89 0.76 8.38 6.60 0.77 18.54 7.74 3.75 0.50 2.48 0.81 0.50 1.14 1.14 8.64 6.86 1.01 0.720 0.295 0.128 0.015 0.088 0.026 0.035 0.030 0.330 0.260 0.030 0.730 0.305 0.148 0.020 0.098 0.032 0.020 0.045 0.045 0.340 0.270 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. L G M K DETAIL Z DETAIL Z S RAD F -B- -A- P R N 0.10 (0.004) SEATING PLANE-T- 0.25 (0.010) T SB 0.18 (0.007)M T SA 0.18 (0.007) T SBS S M CE D 24 PL H BRK
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