MCM6227AWJ20

MCM6227A MOTOROLA | Alldatasheet

Document overview

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Technical content

The MCM6227A is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low–power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ pack- ages.

• Single 5 V ± 10% Power Supply
• Fast Access Times: 20, 25, 35, and 45 ns
• Equal Address and Chip Enable Access Times
• Input and Output are TTL Compatible
• Three–State Output
• Low Power Operation: 160/140/130/120 mA Maximum, Active AC BLOCK DIAGRAM A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 MEMORY MATRIX

1024 ROWS x

1024 COLUMNS

E W QD SSV V CC Order this document by MCM6227A/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT MCM6227A WJ PACKAGE

400 MIL SOJ

CASE 810–03 NC Q W VSS VCC A19 A18 A17 A16 A14 NC A13 A12 A11 A10 D A15 PIN NAMES E REV 4  Motorola, Inc. 1994

E W Mode I/O Pin Cycle Current H X Not Selected High–Z — ISB1 , ISB2 L H Read D out Read ICCA L L Write High–Z Write ICCA H = High, L = Low, X = Don’t Care ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit Power Supply Voltage Relative to VSS VCC – 0.5 to 7.0 V Voltage Relative to VSS for Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ±/n63686172000000000000000020 mA Power Dissipation PD 1.1 W Temperature Under Bias Tbias – 10 to + 85 °C Operating T emperature TA 0 to + 70 °C Storage Temperature Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±/n63686172000000000000000010%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC + 0.3** V Input Low Voltage VIL – 0.5* 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns). ** VIH (max) = VCC = 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns). DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Symbol Min Typ* Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — — ± 1 µA Output Leakage Current (E = VIH, Vout = 0 to VCC ) Ilkg(O) — — ± 1 µA AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6227A–20: tAVAV = 20 ns MCM6227A–25: tAVAV = 25 ns MCM6227A–35: tAVAV = 35 ns MCM6227A–45: tAVAV = 45 ns ICCA 120 110 100 160 140 130 120 mA AC Standby Current (VCC = max, E = VIH, f = fmax ) ISB1 — 7 20 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz) ISB2 — 4 15 mA Output Low Voltage (IOL = + 8.0 mA) VOL — — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — — V * Typical values are measured at 25°C, VCC = 5 V. This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to these high–impedance circuits. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Symbol Typ Max Unit Input Capacitance All Inputs Except Clocks and D, Q E and W C in 4 pF Input and Output Capacitance D, Q C in, Cout 5 8 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±/n63686172000000000000000010%, TA = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE TIMING (See Notes 1 and 2) 6227A–20 6227A–25 6227A–35 6227A–45 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 20 — 25 — 35 — 45 — ns 2,3 Address Access Time tAVQV — 20 — 25 — 35 — 45 ns Enable Access Time tELQV — 20 — 25 — 35 — 45 ns 4 Output Hold from Address Change tAXQX 5 — 5 — 5 — 5 — ns Enable Low to Output Active tELQX 5 — 5 — 5 — 5 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ 0 9 0 10 0 12 — 18 ns 5, 6, 7 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 20 — 25 — 35 — 45 ns NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3.All timings are referenced from the last valid address to the first transitioning address. 4.Addresses valid prior to or coincident with E going low. 5.At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 7.This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL). AC TEST LOADS Figure 1A Figure 1B The table of timing values shows either a minimum or a maximum limit for each param- eter. Input requirements are specified from the external system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never pro- vides data later than that time. TIMING LIMITS OUTPUT Z0 = 50 Ω R L = 50 Ω VL = 1.5 V 5 pF + 5 V OUTPUT 255 Ω 480 Ω

READ CYCLE 1 (See Notes 1, 2, and 8) A (ADDRESS) Q (DATA OUT) tAVAV tAXQX tAVQV DATA VALIDPREVIOUS DATA VALID READ CYCLE 2 (See Note 4) tAVAV tELQV tELQX tEHQZ tAVQV tELICCH tEHICCL ISB Q (DATA OUT) A (ADDRESS) E (CHIP ENABLE) SUPPLY CURRENT ICC HIGH–Z DATA VALID

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6227A–20 6227A–25 6227A–35 6227A–45 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 20 — 25 — 35 — 45 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 15 — 17 — 20 — 25 — ns Write Pulse Width tWLWH, tWLEH 15 — 17 — 20 — 25 — ns Data Valid to End of Write tDVWH 10 — 10 — 15 — 20 — ns Data Hold TIme tWHDX 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 9 0 10 0 15 0 20 ns 4, 5, 6 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3.All timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 5.This parameter is sampled and not 100% tested. 6.At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1 and 2) tAVWH tWLQZ tWHAX tDVWH A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) DATA VALID HIGH–Z HIGH–Z tAVAV tAVWL tWLEH tWHDX tWLWH tWHDX

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6227A–20 6227A–25 6227A–35 6227A–45 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 20 — 25 — 35 — 45 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 15 — 17 — 20 — 25 — ns Enable to End of Write tELEH, tELWH 15 — 17 — 20 — 25 — ns 4, 5ELEH, tELWH Write Pulse Width tWLEH 15 — 17 — 20 — 25 — ns Data Valid to End of Write tDVEH 10 — 10 — 15 — 20 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3.All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state. WRITE CYCLE 2 (E Controlled See Notes 1 and 2) tEHDX tDVEH tEHAXtELWHtAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tELEH tWLEH

ORDERING INFORMATION

(Order by Full Part Number) Motorola Memory Prefix Part Number Package (WJ = 400 mil SOJ) Full Part Numbers — MCM6227AWJ20 MCM6227AWJ20R2 MCM6227AWJ25 MCM6227AWJ25R2 MCM6227AWJ35 MCM6227AWJ35R2 MCM6227AWJ45 MCM6227AWJ45R2 Shipping Method (R2 = T ape and Reel, Blank = Rails) Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns, 45 = 45 ns) MCM 6227A WJ XX XX

28 LEAD

CASE 810–03 18.29 10.04 3.26 0.39 2.24 0.67 0.89 0.76 11.05 9.15 0.77 MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D E F G H K L M N P R S 0° 5° 0° 5°

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

18.54 10.28 3.75 0.50 2.48 0.81 0.50 1.14 1.14 11.30 9.65 1.01 0.720 0.395 0.128 0.015 0.088 0.026 0.035 0.030 0.435 0.360 0.030 0.730 0.405 0.148 0.020 0.098 0.032 0.020 0.045 0.045 0.445 0.380 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. PACKAGE DIMENSIONS

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. MCM6227A/D /C0042/C0077/C0067/C0077/C0054/C0050/C0050/C0055/C0065/C0047/C0068/C0042 ◊ CODELINE TO BE PLACED HERE