MCM6206DJ25R2

MCM6206D MOTOROLA | Alldatasheet

Document overview

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Technical content

32K x 8 Bit Fast Static RAM The MCM6206D is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is avail- able in plastic dual–in–line and plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, and 25 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems
• Low Power Operation: 125 – 140 mA Maximum AC
• Fully TTL Compatible — Three State Output BLOCK DIAGRAM A0 A2 A5 A10 A12 A13 A14 A11 MEMORY MATRIX

256 ROWS x

E DQ0 DQ7 W G ... VCC VSS Order this document by MCM6206D/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT MCM6206D SS A12 V V A13 CC A11 DQ0 DQ6 A14 A10 DQ7 DQ4 DQ5 DQ1 DQ2 DQ3 G E W DQ0 – DQ7 Data Input/Data Output. . . P PACKAGE

300 MIL PLASTIC

CASE 710B–01 J PACKAGE

300 MIL SOJ

CASE 810B–03 PIN NAMES REV 1  Motorola, Inc. 1994

TRUTH TABLE (X = Don’t Care) E G W Mode VCC Current Output Cycle H X X Not Selected ISB1 , ISB2 High–Z – L H H Output Disabled ICCA High–Z – L L H Read ICCA D out Read Cycle L X L Write ICCA High–Z Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage VCC – 0.5 to + 7.0 V Voltage Relative to VSS For Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating T emperature TA 0 to + 70 °C Storage Temperature—Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for ex- tended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — ± 1 µA Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC ) Ilkg(O) — ± 1 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V POWER SUPPLY CURRENTS Parameter Symbol – 12 – 15 – 20 – 25 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax ) ICCA 140 135 130 125 mA AC Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 40 35 35 30 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥/n636861720000000000000000VCC – 0.2 V Vin ≤/n636861720000000000000000VSS + 0.2 V, or ≥/n636861720000000000000000VCC – 0.2 V) ISB2 20 20 20 20 mA CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested) Characteristic Symbol Max Unit Address Input Capacitance C in 6 pF Control Pin Input Capacitance (E, G, W) C in 8 pF I/O Capacitance C I/O 8 pF This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this high–impedance circuit. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE (See Note 1) – 12 – 15 – 20 – 25 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 2 Address Access Time tAVQV — 12 — 15 — 20 — 25 ns Enable Access Time tELQV — 12 — 15 — 20 — 25 ns 3 Output Enable Access Time tGLQV — 6 — 8 — 10 — 12 ns Output Hold from Address Change tAXQX 4 — 4 — 4 — 4 — ns 4,5,6 Enable Low to Output Active tELQX 4 — 4 — 4 — 4 — ns 4,5,6 Enable High to Output High–Z tEHQZ 0 7 0 8 0 9 0 10 ns 4,5,6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 4,5,6 Output Enable High to Output High–Z tGHQZ 0 6 0 7 0 8 0 10 ns 4,5,6 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 12 — 15 — 20 — 25 ns NOTES: 1. W is high for read cycle. 2.All timings are referenced from the last valid address to the first transitioning address. 3.Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device. 5. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B. 6.This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). AC TEST LOADS OUTPUT Z0 = 50 Ω 50 Ω VL = 1.5 V Figure 1A Figure 1B 5 pF +5 V OUTPUT 255 Ω 480 Ω TIMING LIMITS The table of timing values shows either a minimum or a maximum limit for each param- eter. Input requirements are specified from the external system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never pro- vides data later than that time.

READ CYCLE 1 (See Note 7) Q (DATA OUT) A (ADDRESS) DATA VALIDPREVIOUS DATA VALID tAVAV tAXQX tAVQV READ CYCLE 2 (See Note 3) ISB ICC tEHQZ tEHICCL DATA VALID tGHQZ tAVAV tELQX tELQV E (CHIP ENABLE) Q (DATA OUT) A (ADDRESS) tELICCH tAVQV tGLQX tGLQV G (OUTPUT ENABLE) VCC SUPPLY CURRENT HIGH–Z HIGH–Z

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) – 12 – 15 – 20 – 25 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — ns Write Pulse Width tWLWH , tWLEH 10 — 12 — 15 — 20 — ns Write Pulse Width, G High tWLWH , tWLEH 10 — 10 — 12 — 15 — ns 4 Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ 0 6 0 7 0 8 0 10 ns 5,6,7 Write High to Output Active tWHQX 4 — 4 — 4 — 4 — ns 5,6,7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3.All timings are referenced from the last valid address to the first transitioning address. 4. If G ≥ VIH, the output will remain in a high impedance state. 5.At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B. 7.This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) DATA VALID tDVWHtAVWL tAVWH tAVAV tWHAX tWLWH tWHDX tWLQZ tWHQX HIGH–Z HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tWLEH

WRITE CYCLE 2 (E Controlled, See Note 1) – 12 – 15 – 20 – 25 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — ns Enable to End of Write tELEH , tELWH 9 — 10 — 12 — 15 — ns 3,4 Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2.All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tWLEH tEHDXtDVEH tEHAXtELWH tELEHtAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN)

ORDERING INFORMATION

(Order by Full Part Number) Motorola Memory Prefix Part Number Package (P = 300 mil Plastic DIP , J = 300 mil SOJ) Shipping Method (R2 = T ape and Reel, Blank = Rails) Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns) MCM 6206D X XX XX Full Part Numbers — MCM6206DP12 MCM6206DJ12 MCM6206DJ12R2 MCM6206DP15 MCM6206DJ15 MCM6206DJ15R2 MCM6206DP20 MCM6206DJ20 MCM6206DJ20R2 MCM6206DP25 MCM6206DJ25 MCM6206DJ25R2

CASE 710B–01

300 MIL PDIP

28 LEAD

0.25 (0.010) T BM S0.25 (0.010) T AM S MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D E F G J K L M N 34.55 7.12 3.81 0.39 1.15 0.21 3.18 0.51 34.79 7.62 4.57 0.53 1.39 0.30 3.42 15° 1.01 1.360 0.280 0.150 0.015 0.045 0.008 0.125 0.020 1.370 0.300 0.180 0.021 0.055 0.012 0.135 15° 0.040

1.27 BSC

2.54 BSC

7.62 BSC

0.050 BSC

0.100 BSC

0.300 BSC

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). -B- -A- K L M C NE F D 28 PL G J 28 PL -T- SEATING PLANE CASE 810B–03 A B C D E F G H K L M N P R S 0° 10°

0.64 BSC

0.025 BSC

0° 10° 18.29 7.50 3.26 0.39 2.24 0.67 0.89 0.76 8.38 6.60 0.77 18.54 7.74 3.75 0.50 2.48 0.81 0.50 1.14 1.14 8.64 6.86 1.01 0.720 0.295 0.128 0.015 0.088 0.026 0.035 0.030 0.330 0.260 0.030 0.730 0.305 0.148 0.020 0.098 0.032 0.020 0.045 0.045 0.340 0.270 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. L G M K DETAIL Z DETAIL Z S RAD F -B- -A- P R N 0.10 (0.004) SEATING PLANE-T- 0.25 (0.010) T SB 0.18 (0.007)M T SA 0.18 (0.007) T SBS S M CE D 24 PL H BRK Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. MCM6206D/D /C0042/C0077/C0067/C0077/C0054/C0050/C0048/C0054/C0068/C0047/C0068/C0042 ◊ CODELINE TO BE PLACED HERE