MCM6206C MOTOROLA | Alldatasheet
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SEMICONDUCTOR TECHNICAL DATA 32K x 8 Bit Fast Static RAM The MCM6206C is fabricated using Motorola's high-performance silicon-gate CMOS technology. Static design eliminates the need forexternal clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliablity. This device meets JEDEC standards for functionality and pinout, and is avait P PACKAGE able in plastic dual-in-line and plastic small-outline Jleaded packages. 200 MIL PLASTIC * Single 5 V + 10% Power Supply CASE 7108-01 * Fully Static — No Clock or Timing Strobes Necessary * Fast Access Times: 15, 17, 20, 25 and 35 ns + Equal Address and Chip Enable Access Times J PACKAGE * Output Enable (G) Feature for Increased System Flexibility and to 300 MIL. SOJ Eliminate Bus Contention Problems CASE 8108-03 + Low Power Operation: 135 - 165 mA Maximum AC + Fully TTL Compatible — Three State Output cS) \\9) PIN ASSIGNMENT BLOCK DIAGRAM Ww AMO te Ul voc . (e\\ ave 2 afw At > SN L) ards 261) ass »—bo ONDE QOY “ate Ms 5 , Y ass 241) 19 = mle 230 an ~— BS pow uY C| asl? alls a Pej veconrg CN xe Q\\) raid 2tf] ao »—Ro (@) ai aofle ‘ 40] 0 191] par 49: — S pao ft 181] pos ai oar 12 1710 bos LT doe 8 ‘Hl bos J “ 5 =f es t= woth Hi ATA oo et i RRRRRARR . AO-A14.. Address input E. rT») AQ AZ AS AIO A12 AIZ Als DQ0- DQ7 ... Data input/Data Output ¥ = a - BS chip enable VSS ceeeccceeseeeeseees eee Grund MOTOROLA FAST SRAM Mcme208C o4e
TRUTH TABLE (x = Don't Care) [ETS [Ww] Mode | Vocurent | ouput | cycle | H |x |x | NotSelected | Igpy.lsp2 | Highz = tL | H | H | Output Disabled Ioca High-Z - cfula Read loca Dout _ | Read Cycle efxfe write loca High-Z__| Write Cycle ABSOLUTE MAXIMUM RATINGS [rare Simms [vou Tuer] onsen cing inputs against damage due to high static vot- Power Supply Voltage =08t0+7.0 ages or electric fields; however, itis advised = ry that normal precautions be taken to avoid in =08 +0: Votan elt 105s For Any OsteVoc+0s appication of any voltage higher than maxi- mum rated voltages to this high-impedance This CMOS memory circuit has been de- [PowerDissipaton TP 89 | | signed to meet th de and ac specications ‘Temperature Under Bias shown in the tables, after thermal equilibrium has been establshod. The circuit is in a test Operating Temperature socket or mounted on a printed creut board Sorage Temperature Plasto [tag | =88t0+ 125 | <0 | — and transverse alr lw of atleast 500 tnear NOTE: Permanent device damage may occur ABSOLUTE MAXIMUM RATINGS are —«*f@et Per minute is maintained. ‘exceeded, Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for ex- tended periods of time could affect device reliably. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS [Parameter OT yet Tie Tye Tex Tune ‘Supply Votage (Operating Voltage Range) [vec [4s [so [ss fv | [eeutonvenae | | of | *ViL (min) = —0.5 V do; Vi (min) = 2.0 V ac (pulse width = 20 ns) “Vin (max) = Voc + 0.3 V de; Viq (max) = Voc + 2.0 V ac (pulse width < 20 ns) DC CHARACTERISTICS ne cs ee ee Input Leakage Current (Alinputs, Vin = 019 Veo) a a Output Leakage Curent (E= Vin oF = Vins Vout= 010 VEO) wo) | = || Soha ae toot [von [ee [=v ‘Output Low Voltage (lou = 8.0 mA) [vo [= | oe Tv | POWER SUPPLY CURRENTS [Parmeter Symbot_[ = 18 | -17 | ~20 | ~25 | -25 T unt | Te Re Sy Carat eo wa YOO Wate) | toca | 18 | S| HO] [os | we | (AD Standby Current (= Vin. Voc = Max f= fax) | 'sex_[ so [ «| 4s | 40 [40 | ma | ‘CMOS Standby Current (Voc = Max, f= 0 MHz, E2Voo-02V Vin $Vgg +02 V, or 2VoG-0.2V) CAPACITANCE (f= 1 MHz, dV = 3 V, Ta = 25°C, Periodically sampled rather than 100% tested) PO eharectoiatc OT SymbotTax Tune | ‘Adress Input Capacitance a ee ae Conta nt apt EE oe a VO Capacitance [cv fe | oF | McM6206C MOTOROLA FAST SRAM 3-16 CC
AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE (See Note 1) : Co eee eee | win [wax [win [ax | win [wax [win [ex win [wax | [Peetcree tine OL twvav [a8 [= fo [= fm [Ps [Pos [oe [2 | [Aadiees Acceso Tine wow [= | 8 [= Pr [foo [Ys [= Pos [re [| [EnableAccessTine | exo [= [8 [= [v7 [= Too [Yas [= Pas [oe [| [ourtenabiorceestie [twxav [Ps [—[s [fo l—fel—-fsls | | [ouratheistomAdsess Change | wxox | [=| « [= fe [=f [Ts | [os [ase | a ee [enabietianioovpurin 2 [ena [0 |e [o fe To fe fo [io fo [i | ve | ase | [OumtEnabielowiocuraacte | cuax [0 [= [oe |= o [— fo |— [oo |= Te [ase | [ouptEranierionooumutrigh2 | tenor | o [7 [oe fe [oe fo [io fo |i |r [ase] [PoverveTine OO etconf 0 [= To [Po [-fe|-fTol-[ey | [PowerDownTine [emoo [= [8 [=P [=o [fs [=a t [| MTR ih or ad yt 2. All mings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. Atany given voltage and temperature, teG7 (max) Is less than teLQx (min), and tgHaz (max) is less than tgLaX (min), both fora given device and from device to device. ‘5. Transition is measured +500 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = Vi, G = Vip).
7 AC TEST LOADS TIMING LIMITS
‘The table of timing values shows either a : a ‘minimum or a maximum limitfor each param- ter. Input requirements are specified from X= 0 iC the extemal system point of view. Thus, ad- : Gress setup time is shown as a minimum Ourpur. since the system must supply at least that pee 20 Se ‘much time (even though most devices do not = + requireit).On the otherhand, responses from the memory are specified from the device W=1Sv L point of view. Thus, the access time is shown, as a maximum since the device never pro- Figure 1 Figure 18 vides data later than that time, i J i ee | MOTOROLA FAST SRAM MCM6206C ee
READ CYCLE 1 (See Note 7) wav. ‘AIADORESS) taxox Q(DATAOUT) PREVIOUS DATA VALID DATA VALID k—_—— wav READ CYCLE 2 (See Note 3) A(ADDRESS) wav ‘exov E (CHIP ENABLE) =a [| y = G (OUTPUT ENABLE) bo coman ae Pee evo ‘EHICCL Yoo 0° SUPPLY CURRENT, 'sB ee MCM6206C MOTOROLA FAST SRAM ee
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) Po pee See Symbot [ win [Max [ in [tax | win [Max [ win [wax | win [Mex | Unit | Notes [Wwite yee Tine wa fs | | fm [=e |— fa l— pel ss | [Adiess Seuptinwe ame fo [To [fo |-l;el|-fel-[ul | [Adtess vaidio Endofwite [tan [v2 | — [ve |= [is [=| |—-al|—-fe lf | ‘Write Pulse Width ‘WLWH: ‘WLEH ‘Write Pulse Width, ‘WLWH: ns GHigh tWLEH | [Petavaiswo enorme [towm 7 [—Te [=e [-[el-[el-[el | [DatatoisTine [two fo [fo [fo [=[o}-fol-[el | [WiteLowto Oumatrign-z Twmaz fo [7 [ote lots l[ololo|n|m |sar| [wate High to Outpatacive Twnox | [= | « [=| [=] [— [= | fe [aor] [wite RecovenyTimo wax 0 [—-fol=fo{—fe]-Jo|—-|m] | a wt cur rng he overlap of Elow and Wow. 2. 1G goes low coincident with or after W goes low, the output will remain in a high impedance state, 3. All timings are referenced from the last valid address to the first transitioning address. 4. 1G > Vix, the output will remain in a high impedance state. 5. Atany given voltage and temperature, twLaz (max) is less than twHax (min), both for a given device and from device to device. 6. Transition is measured +500 mV from steady-state voltage with load of Figure 1B. 7, This parameter le sampled and not 100% tsted WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) tava 'WHAX E (CHIP ENABLE) | WOWRITE ENABLE) TOOK KEE comm XK XXXXXXKXXK DATAVALO XXXXXXX ‘waz WHOX Q(DATAOUT) HIGH2, HGHZ eee | MOTOROLA FAST SRAM. MCM6206C el
WRITE CYCLE 2 (€ Controlled, See Note 1) SS SESE Symbol | win [Max | Min [wax | Win [Max | win [ ax | tin | Max | [Adaossseuptine S| wen | 0 || o[—-fel—fol~Jol[—-[m=] | [pcsessvaidiwenactwie | taven [| — [re |[—][s[—fa[=[as[— [ol | femererw Pe PEPE A Tt | tELWH [Datavaicwenaotwie | oven | 7 [-[*@ [—al—[o[-[uf- [mT | [witoRacweytme ———=s«d eta | © [— To [—fo[—[e[-[o[-T=] | Atte ocous dug the overlap of low and W tow 2. All timings are referenced from the last valid address to the first transitioning address. 3. ITE goos low coincident wth or ator W goes low, the ouput wil remain ina high impedance stat. 3 | 4. 1FE goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controtied, See Noto 1) ‘aay E (CHP ENABLE) =a wwe. her ‘eux ‘WLEH W(WRITEENABLE) ‘oven ‘eHox VVYVYV YY VY YY YY YY XXX YY YYYYVY voomany XXXXXXXKXXXAKAXXAKAMY XXXXXY
ORDERING INFORMATION
(Order by Full Part Number) Motorola Memory Prefix _ a Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number mT" _ Spood (15 = 15 ns, 17 = 17ns, 20 20s, 25 = 25 ns, 35 = 35 ns) Package (P = 300 mil Plastic DIP, J = 300 mil SOJ) Full Part Numbers — MCM6206CP15 MCM6206CJ15 MCM6206CJ15R2 MCM6206CP17 MCM6206CJ17 MCM6206CJ17R2 MCM6206CP20 MCM6206CJ20 MCM6206CJ20R2 MCM6206CP25 MCM6206CJ25 MCM6206CJ25R2 MCME206CP35 MCME2060J35. MGMBZ06GI9SR2 a mcmez06c MOTOROLA FAST SRAM eee