MCM6206BA MOTOROLA | Alldatasheet
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Technical content
32K x 8 Bit Fast Static RAM The MCM6206BA is a 262,144 bit static random access memory organized as 32,768 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is avail- able in plastic small–outline J–leaded packages.
- Single 5 V ± 10% Power Supply
- Fully Static — No Clock or Timing Strobes Necessary
- Fast Access Times: 12/15/20/25 ns
- Equal Address and Chip Enable Access Times
- Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems
- Low Power Operation: 125 – 140 mA Maximum AC
- Fully TTL Compatible — Three State Output BLOCK DIAGRAM AAAAAA A A A A A A A A MEMORY MATRIXROW DECODER INPUT DATA CONTROL COLUMN I/O COLUMN DECODER E DQ DQ W G VCC VSS A CIRCUIT CONTROL Order this document by MCM6206BA/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT MCM6206BA SS A A A A A A A A A V V A A A CC A DQ DQ A A DQ DQ DQ DQ DQ DQ G E W J PACKAGE
300 MIL SOJ
810B–03 PIN NAMES REV 1 10/9/96 Motorola, Inc. 1996
TRUTH TABLE (X = Don’t Care) E G W Mode VCC Current Output Cycle H X X Not Selected ISB1 , ISB2 High–Z – L H H Output Disabled ICCA High–Z – L L H Read ICCA D out Read Cycle L X L Write ICCA High–Z Write Cycle ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage VCC – 0.5 to + 7.0 V Voltage Relative to VSS For Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 20 mA Power Dissipation PD 1.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Storage Temperature—Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for ex- tended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V *VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — ± 1 µA Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC ) Ilkg(O) — ± 1 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = 8.0 mA) VOL — 0.4 V POWER SUPPLY CURRENTS Parameter Symbol –1 2 –1 5 –2 0 –2 5 Unit AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax ) ICCA 140 135 130 125 mA AC Standby Current (E = VIH, VCC = Max, f = fmax) ISB1 40 35 35 30 mA CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥ VCC – 0.2 V Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V) ISB2 10 10 10 10 mA CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested) Characteristic Symbol Max Unit Address Input Capacitance C in 6 pF Control Pin Input Capacitance (E, G, W) C in 8 pF I/O Capacitance C I/O 8 pF This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this high–impedance circuit. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
- W is high for read cycle.
- All timings are referenced from the last valid address to the first transitioning address.
- Addresses valid prior to or coincident with E
- At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given
device and from device to device.
- Transition is measured ±500 mV from steady–state voltage with load of Figure 1b.
- This parameter is sampled and not 100% tested.
- Device is continuously selected (E
provides data later than that time. Figure 1. AC Test Loads
READ CYCLE 1 (See Note 7) Q (DATA OUT) A (ADDRESS) DATA VALIDPREVIOUS DATA VALID tAVAV tAXQX tAVQV READ CYCLE 2 (See Note 3) ISB ICC tEHQZ tEHICCL DATA VALID tGHQZ tAVAV tELQX tELQV E (CHIP ENABLE) Q (DATA OUT) A (ADDRESS) tELICCH tAVQV tGLQX tGLQV G (OUTPUT ENABLE) VCC SUPPLY CURRENT HIGH Z HIGH Z
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) –1 2 –1 5 –2 0 –2 5 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 10 — 12 — 15 — 20 — ns Write Pulse Width tWLWH , tWLEH 10 — 12 — 15 — 20 — ns Write Pulse Width, G High tWLWH , tWLEH 10 — 10 — 12 — 15 — ns 4 Data Valid to End of Write tDVWH 6 — 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Output High–Z tWLQZ — 6 — 7 — 8 — 10 ns 5,6,7 Write High to Output Active tWHQX 2 — 2 — 2 — 2 — ns 5,6,7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. If G goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If G ≥ VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1b. 7. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) DATA VALID tDVWHtAVWL tAVWH tAVAV tWHAX tWLWH tWHDX tWLQZ tWHQX HIGH Z HIGH Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tWLEH
WRITE CYCLE 2 (E Controlled, See Note 1) –1 2 –1 5 –2 0 –2 5 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — ns Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 10 — 12 — 15 — 20 — ns Enable to End of Write tELEH , tELWH 9 — 10 — 12 — 15 — ns 3,4 Data Valid to End of Write tDVEH 6 — 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tWLEH tEHDXtDVEH tEHAXtELWH tELEHtAVEL tAVEH DATA VALID tAVAV HIGH Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN)
ORDERING INFORMATION
(Order by Full Part Number) Motorola Memory Prefix Part Number Package (J = 300 mil SOJ, E = Evolutionary Pinout) Shipping Method (R = Tape and Reel, Blank = Rails) Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns, 25 = 25 ns) MCM 6206BA EJ XX X Full Part Numbers — MCM6206BAEJ12 MCM6206BAEJ12R MCM6206BAEJ15 MCM6206BAEJ15R MCM6206BAEJ20 MCM6206BAEJ20R MCM6206BAEJ25 MCM6206BAEJ25R
CASE 810B–03
28 LEAD
0.25 (0.010) T BS S 0.18 (0.007) T BS S 0.18 (0.007) T AM S MIN MIN MAX MAX INCHES MILLIMETERS DIM A B C D E F G H K L M N P R S /C0048° 10°
1.27 BSC
0.64 BSC
0.050 BSC
0.025 BSC
/C0048° 10° 18.29 7.50 3.26 0.39 2.24 0.67 0.89 0.76 8.38 6.60 0.77 18.54 7.74 3.75 0.50 2.48 0.81 0.50 1.14 1.14 8.64 6.86 1.01 0.720 0.295 0.128 0.015 0.088 0.026 0.035 0.030 0.330 0.260 0.030 0.730 0.305 0.148 0.020 0.098 0.032 0.020 0.045 0.045 0.340 0.270 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. L G M K DETAIL Z DETAIL Z S RAD F -B- -A- P R N 0.10 (0.004) SEATING PLANE-T- M CE D 24 PL H BRK
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