MCM56824A MOTOROLA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

DSPRAM  8K x 24 Bit Fast Static RAM The MCM56824A is a 196,608 bit static random access memory organized as 8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple chip enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital Signal Processor and provide a very efficient means for imple- mentation of a reduced parts count system requiring no additional interface logic. The availability of multiple chip enable (E1 and E2) and output enable (G) in- puts provides for greater system flexibility when multiple devices are used. With either chip enable input unasserted, the device will enter standby mode, useful in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the highest order address input depending upon the state of the V/S control input. This feature allows one physical static RAM component to efficiently store pro- gram and vector or scalar operands by dynamically re–partitioning the RAM array. Typical applications will logically map vector operands into upper memory with scalar operands being stored in lower memory. By connecting DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control pin, such partitioning can occur with no additional components. This al- lows efficient utilization of the RAM resource irrespective of operand type. See application diagrams at the end of this document for addition- al information. Multiple power and ground pins have been utilized to minimize effects induced by output noise. The MCM56824A is available in a 52 pin plastic leaded chip–carrier (PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.

  • Single 5 V ± 10% Power Supply
  • Fast Access and Cycle Times: 20/25/35 ns Max
  • Fully Static Read and Write Operations
  • Equal Address and Chip Enable Access Times
  • Single Bit On–Chip Address Multiplexer
  • Active High and Active Low Chip Enable Inputs
  • Output Enable Controlled Three State Outputs
  • High Board Density PLCC Package
  • Low Power Standby Mode
  • Fully TTL Compatible DSPRAM is a trademark of Motorola, Inc. For proper operation of the device, all VSS pins must be connected to ground. PIN NAMES PIN ASSIGNMENTS DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ23 DQ22 DQ21 VSS DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 VSS DQ14 DQ13 DQ11 DQ12 NC W G CC SS V V 4748495051521234567 33323130292827262524232221 A10 A11 A12 CCV NC X/Y V/S PLCC D21 VSS VSS VCC NC X/Y A11 D23 V/S A12 A10 D22 D20D17D16 D15D14 D13 D12 VSS D7VSS D9D11 D10 W VCC G VSS A5 D18 D19 VSS 987 6 5 410 B C G A D E F H J Not to Scale 32 1 VIEW OF PBGA PACKAGE BOTTOM Order this document by MCM56824A/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA MCM56824A FN PACKAGE 52–LEAD PLCC CASE 778–02 9 x 10 GRID

86 BUMP PBGA

CASE 896A–01 REV 2  Motorola, Inc. 1995

(MSB) (LSB) V/S A9A6 DQ23 MEMORY ARRAY

512 ROWS x

384 COLUMNS

G W DQ0 A12

2 TO 1 MUX

  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • •• VSS TRUTH TABLE E1 E2 G W V/S Mode Supply Current I/O Status H X X X X Not Selected ISB High–Z X L X X X Not Selected ISB High–Z L H H H X Output Disable ICC High–Z L H L H H Read Using X/Y ICC Data Out L H L H L Read Using A12 ICC Data Out L H X L H Write Using X/Y ICC Data In L H X L L Write Using A12 ICC Data In NOTE: X=don’t care. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VCC – 0.5 to + 7.0 V Voltage Relative to VSS for Any Pin Except VCC Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.75 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid appli- cation of any voltage higher than maximum rated voltages to this high–impedance circuit. This CMOS memory circuit has been de- signed to meet the dc and ac specifications shown in the tables, after thermal equi- librium has been established. The circuit is assumed to be in a test socket or mounted on a printed circuit board with at least 300 LFPM of transverse air flow being maintained.

Figure 1. AC Test Loads

AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE TIMING (See Notes 1, 2, and 3) MCM56824A–20 MCM56824A–25 MCM56824A–35 Parameter Symbol Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 20 — 25 — 35 — ns Address Access Time tAVQV — 20 — 25 — 35 ns MUX Control Valid to Output Valid tVSVQV — 20 — 25 — 35 ns Chip Enable to Output Valid tE1LQV tE2HQV — 20 — 25 — 35 ns 4 Output Enable to Output Valid tGLQV — 8 — 10 — 15 ns Output Active from Chip Enable tE1LQX tE2HQX 2 — 2 — 0 — ns 4, 5 Output Active from Output Enable tGLQX 0 — 0 — 0 — ns 5 Output Hold from Address Change tAXQX 4 — 5 — 5 — ns Output Hold from MUX Control Change tVSXQX 4 — 5 — 5 — ns Chip Enable to Output High–Z tE1HQZ tE2LQZ 0 10 0 15 0 15 ns 4, 5 Output Enable High to Output High–Z tGHQZ 0 8 0 15 0 15 ns 5 NOTES: 1. A read cycle is defined by W high. 2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition. 3. Addresses valid prior to or coincident with E1 going low or E2 going high. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device. READ CYCLE tAVQV HIGH–ZHIGH–ZQ (DATA OUT) G (OUTPUT ENABLE) E1 (CHIP ENABLE) V/S (MUX CONTROL) A (ADDRESS) tVSXQX tGHQZ tE1HQZ DATA VALID tE1LQX tE1LQV tGLQV tVSVQV tAVAV tAXQX tGLQX

WRITE CYCLE TIMING (Write Enable Initiated, See Note 1) MCM56824A–20 MCM56824A–25 MCM56824A–35 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 20 — 25 — 35 — ns Address Setup Time tAVWL 0 — 0 — 0 — ns 2 MUX Control Setup Time tVSVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 15 — 20 — 30 — ns MUX Control Valid to End of Write tVSVWH 15 — 20 — 30 — ns Write Pulse Width tWLWH 15 — 15 — 20 — ns 3 Write Enable to Chip Enable Disable tWLE1H tWLE2L 15 — 15 — 20 — ns 3, 4 Chip Enable to End of Write tE1LWH tE2HWH 15 — 15 — 20 — ns 3, 4 Data Valid to End of Write tDVWH 8 — 10 — 15 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns 5 Write Recovery Time tWHAX 0 — 0 — 0 — ns 2 MUX Control Recovery Time tWHVSX 0 — 0 — 0 — ns Write High to Output Low–Z tWHQX 4 — 5 — 5 — ns 6 Write Low to Output High–Z tWLQZ 0 15 0 15 0 15 ns 6 NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. Write must be high for all address transitions. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state. 4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time. 6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than tGLQX min for a given device and from device to device. WE INITIATED WRITE CYCLE HIGH–Z HIGH–Z E1 (CHIP ENABLE) VALID DATA IND (DATA IN) W (WRITE ENABLE) V/S (MUX CONTROL) Q (DATA OUT) A (ADDRESS) tAVAV tWHQX tDVWH tWLQZ tWHAX tWHDX tWHVSX tAVWL tE1LWH tVSVWL tWLWH tVSVWH tAVWH tWLE1H

WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1) MCM56824A–20 MCM56824A–25 MCM56824A–35 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 20 — 25 — 35 — ns Address Setup Time tAVE1L tAVE2H 0 — 0 — 0 — ns 2 MUX Control Setup Time tVSVE1L tVSVE2H 0 — 0 — 0 — ns 2 Address Valid to End of Write tAVE1H tAVE2L 15 — 20 — 30 — ns 2 MUX Control Valid to End of Write tVSVE1H tVSVE2L 15 — 20 — 30 — ns 2 Chip Enable to End of Write tE1LE1H tE2HE2L 12 — 15 — 20 — ns 2, 3 Data Valid to End of Write tDVE1H tDVE2L 8 — 10 — 15 — ns 2 Data Hold Time tE1HDX tE2LDX 0 — 0 — 0 — ns 2, 4 Write Recovery Time tE1HAX tE2LAX 0 — 0 — 0 — ns 2 MUX Control Recovery Time tE1HVSX tE2LVSX 0 — 0 — 0 — ns 2 NOTES: 1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2 low. 2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high. 3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state. 4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time. E1 OR E2 INITIATED WRITE CYCLE D (DATA IN) W (WRITE ENABLE) E1 (CHIP ENABLE) V/S (MUX CONTROL) Q (DATA OUT) A (ADDRESS) tAVAV tAVE1H tE1HAX tVSVE1H tE1HVSX tE1LE1H tVSVE1L tDVE1H tE1HDX DATA VALID HIGH–Z tAVE1L

A0 – A11 A12 X/Y A0 – A11 8K x 24 “X” OPERANDS MCM56824ADSP56001 PROGRAM MEMORY 4K x 24 “X” OPERANDS PROGRAM MEMORY HIGH 4K x 24 “Y” OPERANDS PROGRAM MEMORY LOW V/S MUX DSPRAM Multiplexed Vector/Scalar Address Maps 8K x 24 DSPRAM Used in Typical Application X/Y A0 – A11 D0 – D23 A0 – A11 D0 – D23 WR A15 V/S W X/Y MEMORY MANAGEMENT PINS A12 A12 MCM56824ADSP56001

ORDERING INFORMATION

(Order by Full Part Number) MCM 56824A XX XX XX Motorola Memory Prefix Part Number Full Part Numbers — MCM56824AFN20 MCM56824AFN25 MCM56824AFN35 MCM56824AZP20 MCM56824AZP25 MCM56824AZP35 MCM56824AZP20R2 MCM56824AZP25R2 MCM56824AZP35R2 Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (FN = PLCC, ZP = PBGA) Shipping Method (R2 = Tape and Reel, Blank = rails)

CASE 896A–01 PACKAGE DIMENSIONS -T- -B- B -A- A R N L C G A B C D E F G H 1456897 3 2 D 86 PL G 0.637 0.697 0.053 0.028 0.073 0.544 0.602 0.644 0.703 0.068 0.031 0.096 0.559 0.617 16.36 17.88 1.73 0.81 2.44 14.20 15.69 0.060 BSC1.524 BSC 16.16 17.68 1.33 0.69 1.84 13.80 15.29 MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D G L N R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. J 0.20 (0.008) T0.50 (0.020) B AM S S

52–LEAD PLCC CASE 778–02 A B C E F G H J K R U V W X Y Z MIN MIN MAX MAX MILLIMETERS INCHES DIM 19.94 19.94 4.20 2.29 0.33 0.66 0.51 0.64 19.05 19.05 1.07 1.07 1.07 18.04 1.02 20.19 20.19 4.57 2.79 0.48 0.81 19.20 19.20 1.21 1.21 1.42 0.50 18.54 10° 0.785 0.785 0.165 0.090 0.013 0.026 0.020 0.025 0.750 0.750 0.042 0.042 0.042 0.710 0.040 0.795 0.795 0.180 0.110 0.019 0.032 0.756 0.756 0.048 0.048 0.056 0.020 0.730 10° 1.27 BSC 0.050 BSC NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. S T 0.25(0.010) S–MSL SS –PN G DETAIL S -N- -M--L- -P- C E J 0.10 (0.004) SEATING PLANE -T-G Z A R D W V Y BRK (NOTE 1) LEADS ACTUAL (NOTE 1) 52 B U NOTE 1 VIEW D–D H K DETAIL S F X SSS SM T 0.18(0.007) –PN– M L SSS SS T 0.25(0.010) –PN– M LSSS SS T 0.25(0.010) –ML– P N SSS SS T 0.25(0.010) –ML– P N SSS SM T 0.18(0.007) –PN– M L SSS SM T 0.18(0.007) –ML– P N SSS SM T 0.18(0.007) –PN– M L SSS S SSS SM T 0.18(0.007) –PN– M L M T 0.18(0.007) –ML– P N

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET : http://motorola.com/sps MCM56824A/D◊