MCM54410AN60

Motorola, Inc

1M x 4 CMOS Dynamic RAM Write Per Bit Mode

Manufacturer: Motorola, Inc

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MCM54410A MOTOROLA | Alldatasheet

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m@ SEMICONDUCTOR SE ue | Mcms44104_ | Aavance Information 1M x 4 CMOS Dynamic RAM N PACKAGE Write Per Bit Mode doom sou The MCM54410A is a 0.74 CMOS high-speed, dynamic random access memory. It is organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process ‘technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. ‘The MCM54410A requires only 10 address lines; row and column address inputs are ZPACKAGE multiplexed. The device is packaged in a standard 300-mil J-lead small outline package, “PLASTIC and a 100-mil zig-zag in-line package (ZIP). S" ZIG-ZAG IN-LINE © Three-State Data Output al CASE 836 ‘© Write Per Bit Mode ‘© Fast Page Capability © Test Mode © TTL-Compatible Inputs and Outputs RAS Only Refresh PIN ASSIGNMENT ¢ TAS Betore RAS Refresh 100-MiL ZIP © Hidden Refresh al? © 1024 Cycle Refresh: MCM54410A = 16 ms 300-MIL SOJ 32 ios © Fast Access Time (tac): — wop02 1 MCM54410A-60 = 60 ns (Max) s+ |wavas MCM54410A-70 = 70 ns (Max) wooae 1 % fl Vss Ves|=> MCM54410A-80 = 80 ns (Max) wroai (2 25 [) W303 > woos * Low Active Power Dissipation: ware d3 24 fh we00e wri0a1 s{— MCMS54410A-60 = 660 mW (Max) a — |g ** | WBWE MCMS54410A-70 = 550 mW (Max) RAS (14 23 CAS RRS) °- 4, MCMS54410A-80 = 468 mW (Max) 905 ape 1" “ © Low Standby Power Dissipation: id Da MCM54410A = 11 mW (Max, TTL Levels) | MCM54410A = 5.5 mW (Max, CMOS Levels) wots 18 fag lag ar O10 v7 Dar Voc 6 ‘i lat adn 16 DA asl | asi 5 Das wl 6 Voc 413 14 flag are ‘A0-A9 ‘Address input wor000-waD03 Write Seiect Data input Output Q Data Output Ww . Read/Write Enable RAS Row Address Strobe cs Chip Select Voc Power Supply (+ 5 V) vss Ground Ne No Connection “This document contains ilrmatonon a new roduc. Speciation an intrmaton heen ave subject o change wihout nice MOTOROLA MEMORY DATA 2154

wave w000-#9008 WeWe q onaN STAY rT aren fH TS. NO.2CLOGK DATA OUT = _ CAG: GENERATOR: BUFFER G preys ll COLUMN: no \\rrens.ia) [DECODER x BUFFERS (10) SS "REFRESH Ag aaax a one AS COUNTER 10) AB SENSE AMP Av ROW ADDRESS | VOGATING a8 BUFFERS "0) [> — As of eae) Fa vEMORY NO. 1 CLOCK ° ”] ARRAY aKS ceresnon HE Pe suastaate | <—y, BIAS ce ceneraton | — veg ABSOLUTE MAXIMUM RATING (See Note) [Power Suppiyvotage | Vc | 0047 | esa Gaage doe terilotawele Power Supply Vote aw? |v ‘ower Supply Vonage Veo inputs against damage due tohigh static volt Votiage Relative to Vgs for Any Pin Except Voc. ages or electri fields; however, itis advised [DataOucurent to | 50 [ma | Bhat normal precautions be taken to avoid |_7 mom ated valage otis gh ampere Power Dissipation Pp | 700 mum rated voltages to this high-impedance peaing Temperaiure Range Ta | a 70 rout ‘Storage Temperature Range | =150 NOTE: Permanentdevice damage may occur ABSOLUTE MAXIMUM RATINGS are ex ceeded. Functional operation should be restricted to RECOMMENDED OPERAT- ING CONDITIONS. Exposure to higher than recommended votages or extended periods of me could alec device reliability. WRITE-PER-BIT MODE masked for each write cycle. The truth table for the write-per- ‘The write-per-bit mode allows selective masking of a write _ dit function is shown in the following table: operation on a particular set of device DOs for a given cycle. The write-per-bit function is enabled by holding the WBWE Ti the Falling Edge of RAS signal “Low’ at the falling edge of RAS for the minimum hold 6 Ei time. Masked DOs aro selected by holding Data in(Di)-Low |_ CAS | Wewe | pai | Con the falling edge of RAS for the minimum hold time. Data is rn Write Enabiea then written into the device only on the unmasked DQs, which HOH t Wee Enabied occurs on the falling edge of either WB/WE (late write) or CAS H | L H WriteEnabled = | (early write). Any combination of DOs can be selectively Hop t u Write Maskeo MOTOROLA MEMORY DATA 2185

DC OPERATING CONDITIONS AND CHARACTERISTICS 2 (Voc = 5.0 V #10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS. [Parameter Symbot [win [tye | Max | unit [Notes | Supply Voltage (Operating Voltage Range) Hie fas foe fst | | [ vss [oo [oo | [Logic igh Votage, Alinpus Tw OT ee | = os Tv | | [Logictow Voltage. atineuts Ty 0 TP os Tv Tt | DC CHARACTERISTICS Voc Power Supply Current ‘ect mA MCMSé4108-60. tae = 110 ns 120 MCMSé4104.70. tag = 130 ns 100 MCM54410A-80, tac = 150 ns. 85 Voc Power Supply Current (Standby) (RAS-GAS-Viy) | tcce | — [20 [ma] | Voc Power Supply Current During RAS Only Retresh Cycles (CAS-Vin) ‘ccs 23 MCMS44104-60, tac = 110 ns 120 MCMBé810A-70. tao = 130 ns 00 MCMB48104-80. tg = 150 ns a Voc Power Supply Current During Fast Page Mode Cycle (RAS = Vi.) ‘ce MCME4104-60, tog = 45 ns 70 MCMB44108-70. tpg = 45 ns 70 MCMB44104-60. tog = 50 ns 60 Voc Power Supply Current (Standby) (RAS = CAS = Voc - 02 V) [cos [= [to [ma [| Voc Power Supply Current During CAS Betore RAS Retresh Cycle ‘cos mA MCMB44108-60. tac = 110 ns 120 MCMS4410A-70. tc = 130 ns 100 MCMB44108.80, tac = 150 ns as Input Leakage Current (0 V < Vin 6.5 V) [ing | 0 | io Towa || Output Leakage Current (CAS = Vin. OV < Vout $5.5 V) | tig) | =o [to [wa || Output High Votage (ign = - 5 mA) | vow [ 2s | — [Tv | | Output Low Voltage (Igy = 4.2 mA) [vo [ = [ o« [vy] CAPACITANCE (1.0 Miz. Ta ~ 25°C, Voc = 5 V. Periodically Sampled Rather Than 100% Tested) fo Parameter OT Symbot Max [unit [Notes | input Capadiance none] Cn VO Capacitance (CAS = Vjj4 to Disable Output) woac-waioa3[ Cy | 7 | of | 4 | NOTES. 1. Allvoltages referenced to Vg, 2 Currents @ function of cycle rate and output loading: maximum currents are spectied cycie time (minimum) with the output open 3. Column address can be changed once or less while RAS » Vj, and CAS = Vip, 4. Capacitance measured with a Boonton Meter or effective capacitance calculated trom the equation: C = IAVAV. MOTOROLA MEMORY DATA 2.186

AC OPERATING CONDITIONS AND CHARACTERISTICS (Veo = 30 10% Ta = 00 70°C, Uniese Otherwise Noted) READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2. 3, and 4) [ewan | apa ae ee fa ae] [Faron Readorwie CrioTing [werast [ino [we | — | wo | — [io] — [re] s | [resowiscysetine | reer [we [168 | — [es | — [as | — [re | 5 | [rstPae oes Greet [uricer | ee | = | | |— |= [- |e] | El Rall ada ad [acs Tnevon S| wera | wc | - | [| [= | Pe |e | [acess retonAS | crrav | exc | = | = [=| 2 [| [| so | [Acie Tino en Counnnaaee | twov [tea | — |» | — [5 | — [om [eo] [Swowuniwz | cox [az |e | — fo }— fo }— fel. | [owaceu anton chewy | teear [ore | 0 [= | o | @] 0 [a= || [tanstontneRsoweran [| 4 [3 | |s s,s [ots] | [raSrusewon | wevaen | mas | 0 | won [> [oe oo [of | | [Ras pase wor Fan PooeWoae) | weiner | ease | 00 | 200% | 7 | zon [oo | won| me | | [RiSteatme | ceunen | ass | | — | = | —- [a] — [=] | [easruseman ——iceucen [cas [a [vox | [oe | @ [iow [ ms | | [Ris woxSoeay tno weicer [co [a [© | [ss [a [ots] a] [Ris wcounwaatoss dome | eww [mo [= [| ss [pote | 2 | [GAB whASPresanetine | tenner | tore [5 | — | s | - | s|- [=] [exsPecageti Lene | gp 10 | = Pe | = [| = fe | J (continued) NOTES: 2. An initial pause of 200 us is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. range (0°C < Ta < 70°C) is ensured. 6. Measured with a current load equivalent to 2 TTL (200 A, + 4 mA) joads and 100 pF with the data output trip points set at Voy = 2.0V

2 Aeon 00 pce ras

torr (max) and/or tgz (max) detine the time at which the output achieves the open circuit condtion and is not referenced to output voltage 14. Operation within the tcp (max) limit ensures that tac (max) can be met. tcp (max) is specified as a reference point only: if RCD is greater than the specified tap (max) limit, then access time is controlled exclusively by tac. MOTOROLA MEMORY DATA 2-157

READ, WRITE, AND READ-WRITE CYCLES (Continued) 2 | nmominr | Te baer Ts in| {a au | se | Read Command Hold Time. 'REHWX 13 Reterenced to CAS. CAS Precharge to Write Delay Time | tcenwr | tcpwo | 7 | — | 70 75 ns TAS Setup Time for CAS Botore AAS | ‘rece, | tose) 5 | TAS Hold Time for CAS Betore FAS | tpercen | tona | 75 15 ‘GAS Precharge Time for CAS Betore | icencer | tcpr FAS Hold Time Relerercod'oG | tcinen | tnon | 10 | — a NOTES: MOTOROLA MEMORY DATA 2-158

‘orp + ' Reco» rs SoRP = ee ae aa wre OO te KEE OOOO) { t ba rr KERRY [TE | RRR - ‘ca K # it XXXXXXXKXKEXKENN | ARXKXXEXXEXXKRK ‘ | +—'oFF "rac po az EARLY WRITE CYCLE eI j tras =k ag “HO wore | | alee em wees" XM aw MO BES KKK RRA K KKK RKO ‘wes { aatves ‘wor | men XRF OX TEREN ®10 KORRRRXXRKKRXXKK KKK KKKXXXEERRER ‘os: toH wk KK aS XK XXX MOTOROLA MEMORY DATA 2-160

MCM54410A LED WRITE CYCLE ‘ae @contno tac . ‘or toot oe ; OT — tas am, Yin roo Tt “ = XXX FS ye \\\\ Tha XXXXXX ores NA = YLXX KKK - js XXXXXXX x a, alee sa Re TOKKKKKK XX Se) cy OOXXK Y eats XY “kx ——— s Z van vera va = | GUNES “WD (aK XOOKKXXXKK (S_X 2 KORRERR WOE KXXXXXKX) " LDOATANN KXXX ; - A = “QO ) READ-W ‘eve TesH ‘cas SH £_/ a eae VIM "Reo —~ XXXXXXX a i = \\\\ vom A ca an = =n KXXXXK we a OX es] ro ‘ovo “LK ‘as Rots XXX 0 — Yan XK asidtes wo ADORESSES T WEST tay — ‘ow tea KW t YY ~< KK |, eee “wey A OOOO CEE Tad ‘wou YOK ‘wos TSE KXXXXX foes \\ NGHZ IORY DATA

FAST PAGE MODE READ CYCLE : Re . + CAP —'bc ; ‘a cs crs Wi By - | "RAD \\ =e 1 tes ma ak ‘RAH t CAH j | Vid ae Es Vv — _ COLUMN XXX) ae KXXXXX roost ONE, ous KOO SEK asies KXXXXX ‘RCS RCH ~_ Pe de | - VY [fel | Rh | A ~ | YYVVY * OOOO | AKXEXN | AOC _| ARK Le = aoe : af az tez ‘oz tow _— eee XX atti) —~LM ot, DQ otdr_) FAST PAGE MODE EARLY WRITE CYCLE mV" SE a Vig — “cas | cas (7 ‘cs — 1 RAL * a at hse cA ‘iso be al woes REEL BE KOOL BE KON BS KD | foto om —a] ‘om —+ rion vg Pe tes ahh es _ Via Y mena VATATAN hen VAVATATAN een VAAYAVAVAA Wee NT AO T (XXXL 1 XXKXXXK - YYYYYY ae OOOO AX ANAK XXX KX AX KXXEKXAXK : 4 Woe tog ‘bd tog ‘oH tos: "oH wees XX skim XXX ses KOON SR KX MOTOROLA MEMORY DATA 2-162

FAST PAGE MODE READ-WRITE CYCLE vu = i 4 = ; =e toas et “cas | "ons os | PAN - . Wi tran + [RAL be ts Te | ! | “iH VY [- Y voweses YH NBER Ra) XOOOXIOXT B85 DOOOOOOX 8s OOOOOQOOOO0 inst al Fae y | i oe tn tacs t a ‘cewo + cPwo , ‘yea ‘owo bow tay =o Set he tow wane YH Df | | 1 ace we ] tweet oe ice le-twe * ir ca | | } pica 1 i piss | Sw N\\ Lk hed | | i ital | | Ka al ime stoked NL etic fier i) Qt HX woooo-| seb yz up | FO at | fT ate waa | yon DATAOUT | OATAOUT] DaTAQUT) | ~ VY Vv YVYV VAVATAVANA ee toi OOOOOL OOOO KOO KX MOTOROLA MEMORY DATA 2-163

(WBIWE and G are Don't Care) Vin mr ‘RP ‘RPC ~ we Yin Yu taAH ten r vores XX ae MX XKXKX KXAN CAS BEFORE RAS REFRESH CYCLE (G and A0-A9 are Don't Care) tae ars — ap —— Ven | "RPC -m ; ‘op osR toHR =x VO oS yt ‘wre el WR rave OY XXXXXAKXXKXXXXKXXKKAN OFF woods ee - OT GH 22. —$ A$ MOTOROLA MEMORY DATA 2164

MCM544 E (READ) . - SSH CYCLI HIDDEN REFRE: | - | tap - on) ——~ ton Vig Ri Vu - loRP | \\\\ | : | eer . ays EXE KR KXEKEEN

7 WAV XX

tasr 3 COONS ~ [ a _ KBD = =. ESSES. a XX x = ADDRE vie fs im = TS OO sr “ _ l ery won” OKRA EOE oe | 7 “a VALID DATA OUT a CYCLE (EARLY WRITE) . - “ - HIDDEN REFRESH = tac et e ne . - i ‘aco — RSH i tone “a = KKK cS WH trad’ toa TONY x asa as on OOK KA ae im Mey, OS - OOOO we: Oe : ‘ a ee — a 0 DATA IN “SEDO — same — OEE RROR - - MORY DATA MOTOROLA ME!

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE FS yy tesa | ‘ert ‘RH | a Van pte —>} Nas oS ! tase pmtcan | vooss i DOOOOOOODOOK coumacoess XX XXX tweP- | tan TRRH moe | ‘we 10S <0 ‘no Wawe Vem Yu fi j 80H ~ , ~ 4 1 Ic & n> KOON AXXXOXKX tow j } ea) a WRITE CYCLE symp rtm ‘nest 5S C at ‘em - A — two —> vee OOO AOOXXXXXKXXK a OOTP S OOOO OOOO OOOO TION tos t=} to | READ-WRITE CYCLE {AWD 4 he tay Wawe a | \\ Ling | | tea i | = Vi eH ‘60 | oat cur MOTOROLA MEMORY DATA 2-166

DEVICE INITIALIZATION time of tap to precharge the internal device circuitry for the (On power-up an intial pause of 200 microseconds is re- __Nextactive cycle. Qis valid, putnotiatched. as ong as the CAS quitedtor the internal substrate generator oestablsh the cor. "4 G clocks are active. When ether the CAS of Geka 2 rect bias voltage. This mustbe followed by aminimum of eight _Sitions toinactive, the output will switch to High Z (three-state) active cycies of the row address strobe (clock) to initialize all ‘OFF OF taz after the inactive transition. dynamic nodes within the RAM. During an extended inactive WRITE CYCLE state (greater than 16 milliseconds with the device powered ‘The user can write to the DRAM with any of four cycles: early up), awakeup sequence of eight active cycles is necessary to _write, late write, page mode early write, and page mode read- ‘ensure proper operation. write. Early and late write modes are discussed here, while page mode write operations are covered in another section. ADDRESSING THE RAM ‘Awrite cycle bepine ‘as described in ADDRESSING THE The ten address pins on the device are time multiplexed at RAM. Write modeis enabled by the transition of WE/WE to ac- the beginning of a memory cycle by two clocks, row address _tive (Vj,). Early and late write modes are distinguished by the strobe (RAS) and column address strobe (CAS), intotwosep- —_active transition of WB/WE, with respect to CAS. Minimum ac- arate 10-bit address fields. A total of twenty address bits, ten _tive time tag and tag, and precharge time tap apply to rows and ten columns, will decode one of the 1,048,576 bit lo- write mode, as in the read mode. cations in the device. RAS active transition is followed by CAS An early write cycle is characterized by WB/WE active tran- ‘active transition (active = ViL, tagp minimum) for all read or sition at minimum time tweg before CAS active transition. write cycles. The delay between RRs and CAS active transi- Data in (D) is referenced was in an early write cycle. RAS tions, reterredto as the multiplex window, givesa system de- and CAS clocks must stay active for trw1 and tcw. respec: signer flexibility in setting up the external addresses into the _ tively, after the start of the early write operation to complete the RAM. cycle. ‘The external CAS signal is ignored until an internal FAS sig- ‘Qremains in three-state condition throughout an early write nal is available, This “gate” feature on the external CAS clock cycle because WE/WE active transition precedes or coincides enables the internal CAS line as soon as the rowaddresshold —_with CAS active transition, keeping data-out butters and G dis- time (tray) Specttication is met (anddetines tcp minimum). abled. ‘The multiplex window can be used to absorb skew delays in Alate write cycle (referred to as G-controlled write) occurs switching the address bus from row to column addresses and when WB/WE active transition is made after CAS active transi- in generating the CAS clock. tion. WB/WE active transition could be delayed for almost 10 There are three other variations in addressing the 1Mx4 microseconds after CAS active transition, (tacp + tcwo + RAM: RAS only refresh cycle, CAS before RAS refresh taWL + 2tT) $ tras. if other timing minimums (tcp. 'RWL: cycle, and page mode. All three are discussed in separate and ty) are maintained. Dis reterenced to WEAVE active tran- sections that follow. ston ina ate wie cyte, Ouput bute are enabled by CAS active transition but outputs are switched off by G inactive tran- READ CYCLE sition, which is required to write to the device. Q may be inde- The DRAM may be read with four different cycles: “normal” _tarminate—see note 15 of ac operating conditions table. RAS: random read cycle, page mode read cycle, read-write cycle, and CAS must remain active for trw and tow. respectively, tnd page mode ead-urlecycle. The narmalreadeycleisout: ater WE/WE active vansiton to complete ine write cycle. G lined here, while the other cycles are discussed in separate must remain inactive for tgq{ afterWB/WE active transition to Sections. sad oyle be desctbedin ADDRESS. ZrmPlete the write cycle normal read cycle begins as described in ING THE RAM, wih RAS and CAS active ansitons latching READ-WRITE CYCLE ‘A read-write cycle performs a read and then a write at the the desired bit location. The write (WB/WE) input level must be high (ViH), tags (minimum) before the CAS active transition, Same address, during the same cycle, This cycles basically a oonatie reat Sede, late write cycle, as discussed in the WRITE CYCLE section, Both the RAS and CAS clocks iggera sequence of events $2090 WB/WE mustremain high fortcwp minimum after tne which are controlled by several delayed internal clocks. The CAS active transition, to guarantee valid Q before writing the internal clocks are linked in such a manner that the read ac- cess time of the device is independentofthe address multiplex PAGE MODE CYCLES window. Both CAS and output enable (G) control read access. Page mode allows fast successive data operations at all time: CAS must be active before or at ta¢p maximum and G 1024 column locations on a selected row of the 1M x 4 dynam- must be active tRac-tga (both minimum) after RAS active _ic RAM. Read access time in page mode (Ic.ac) Is typically transition to guarantee valid data out (Q) attrac (access time half the regular RAS clock access time, trac. Page mode op- from RAS active transition). If the tac¢p maximum is exceeded eration consists of keeping RAS active while toggling CAS be- andior G active transition does not occur in time, read access tween Vij and Vi. The row is latched by RAS active transi- time is determined by either the CAS or G clock active transi- tion, while each CAS active transition allows selection of anew tion (tgac or tea). column location on the row. ‘The RAS and CAS clocks must remain active for a minimum ‘A page mode cycle is initiated by a normal read, write, or time of tga and tcag respectively, to complete the read _read-wrte cycle, as described in prior sections. Once the cycle. WOME must remain high throughout the cycle, and for timing requirements for the first cycle are met, CAS transitions time taRH OF (RCH after RAS or CAS inactive transition, re- to inactive for minimum tcp, while RAS remains low (Vj). The spectively, to maintain the data at that bit location. Once RAS —_second CAS active transition while RAS is low initiates the first transitions to inactive, it must remain inactive for a minimum page mode cycle (Ipc or tpRWC). Either a read, write, or a MOTOROLA MEMORY DATA 2.167

2 (previously described). These operations cane intermixedin _transition to prevent switching the device into test mode. consecutive page mode cycles and performed in any order. ‘grade with time and temperature. Eachbit mustbe periodically mode cycle) as in CAS before RAS refresh. Anormal read, write, or read-write operationto the RAMwill cycle timing diagram. fore RAS refresh, and hidden refresh are available on this 1, Write “0"s into all memory cells with normal write mode. before RAS. This clock order activates an internal refresh cycle. Repeat this operation 1024 times. nal address lines are ignored during the automatic refresh mode. cycle. The output butter remains at the same state it was in 6. __ Repeat steps 1 to 5 using complement data. Figure 1. Hidden Refresh Cycle

TEST MODE See the following truth table and test mode block diagram. The internal organization of this device (512K x 8) allows it W, CAS before RAS timing puts the device in “Test Mode” 2 to be tested as if it were a 512K x 4 DRAM. Nineteen of the as shown inthe test mode timing diagram. ACAS before RAS: . ‘twenty addresses are used when operating the device in test or a RAS only refresh cycle puts the device back into normal mode. Column address AO is ignored by the device in test mode. Refresh is performed in test mode by using a W, CAS mode. A test mode cycle reads and/or writes data to a bit in _ before RAS etresh cycle which uses internalrefresh address, each of eight 512K blocks (BO-B7) in parallel. External data counter. outs determined by the internal test mode logic of the device. TEST MODE TRUTH TABLE [0 | eoer | 620s | ses | acer | a | 0 0 0 ° 0 1 1 1 1 1 1 1 - Any Other ° TEST MODE AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V +10%, Ta = 0 to 70°C, Unless Otherwise Noted) READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2,3, and 4) [__symooi__[ saatoaso [seatoa7o_ | seatoaso | | [sia [an [win [wax | win T wox | win | Notes [rardon Read wie owe Time | Tmeuagy Tomo [ns | — [es] — [oss — tm | s | Fast Page Mode Cycle Tine [cect | eo | so [ — | so | — | 7 — [ns [| [Access TinetromGaS | tcevav | tcac | — | 2 | - | 2 | — | es | ns | oe | [access Tine von PrechageoAS —| Tcenov [tema [=| |=] = | |= [= 1s | [RS Pusowan | were {mas | es [vox | m= [von | | ox | m= |_| [FaSHodTime | toeuren | tase | 28 | — [as [ — [os [fos [| [casHotime | aeucen | osu | es | — | 75 | — [es | — [ors | leasrasewan | txucen teas [25 [1 | es | ox | a [oe [me | | [counnadaosseR@iaoTae | wren | ma [se [= |] — fs t= ts] | NOTES: 1. Viqq min and Vj_ max are reference levels for measuring timing of input signals. Transition times are measured between Vis and Vit. 2. An initial pause of 200 us is required atter power-up followed by 8 RAS cycles before proper device operation is guarantees. 3. The transition time specification applies forall input signals, In addition to meeting the transition rate specication. all nput signals must transition between Viy and Vj_ (or between Vi__ and Vjy) in a monotonic manner. 4, AC measurements ty = 5.0 ns. 5. The specifications for tac (min) and tw (min) are used only to indicate cycle time at which proper operation over the full temperature range (0°C < Ta < 70°C) is ensured. 6. Measured with a current oad equivalent to 2 TTL (~ 200 uA, + 4 mA) loads and 100 pF with the data outout trip points set at VoH = 2.0V and Voy = 08. 7. Assumes that tgp < taco (max). 8. Assumes that tgp 2 tac (max). 9. Assumes that tap > (RAD (max) a MOTOROLA MEMORY DATA 2.169

WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY) (0 and AO-AS are Dont Care) ‘RC AS Vy — ns | = " wo ‘orn top ‘esr =O AXXXXMAXXKXKXXKKKAK . L ‘wis ‘wT i XXXXXN AXXXXXXKXXXXXXKKXXAK You = MOTOROLA MEMORY DATA 2.170

‘TEST MODE-READ CYCLE (astm) ts | ste mg “MO ‘En é Via ‘cas cone SIO BE HOOD Ins : ae _va- saan 0.000,0,050,0/4 M oe ‘ 1 tes —al ‘of CZ TEST MODE-EARLY WRITE CYCLE tae ~ tas ———- = lap 1 ‘i> j sq | ‘ | toge —ot ‘asa — | 4 ASC Sona | Ven woresis "OOK ais Salts XXOOOOOOOOOOOOOOO) t wes. ode | Van een, Neha CUCU ma aYe- BYE KXXMXX XXX XK MXKXXK MX AXK AKAN moor" OOK tiny KIO on XXX XXX MOTOROLA MEMORY DATA 2171

‘TEST MODE-FAST PAGE MODE READ CYCLE ~ Bi tcrp tec | ‘rep op _ asa _ ioe on tase JE 1d z om wness " SOCEXD BEE KOON SE KIO Be KID thes ‘acs "cH voume | | | omar VI wane OXXXXY | V \\/ sen po X be! ay tay - tan betonc Cisse ia aac torr tor "OFF “Opa: ‘ea! tas haz Vou — Ma vg QOX ottdir) UX ol QQ _ odie TEST MODE-FAST PAGE MODE EARLY WRITE CYCLE age,» Re wat -—— "we —4 FJ - ~ = al ‘Rep le teas op. ‘ons ‘ORE aN 7, mal ey — "RAK te ‘cal ase toa | worse)" ON sO Bs OOO as KX Ses KKK) wes) = ia ‘ou tw Eee Vu i ‘wes ‘wos : mes mores OX DOO OOO ONT TY XXXXX ial ‘wan | ‘wor ‘WoH ‘wor Va — Bn AXXKXXKXXXXXXAXXAMXARAAKKX ARAKI twos Yq ‘os ‘ow tog beet ton tos al ‘on 'WDH- | wear YOGaRADO oats XOXO ass KOON as KXXXXKD MOTOROLA MEMORY DATA 2-172

TEST MODE BLOCK DIAGRAM 2 | g*oc oc ° Yoo o ° ONORMAL ? sraxatock | A ; ot cE) ° 5 ios Ee Test 3 srexavoox | 3| TEST 81 TT) > Q Test ° @ NORMAL Shoo ghoc Age ° Voc 3 0 ONORMAL z stax took [Lo ° i) is & r=, Crest [oor Fo _horman, L ol {Loai_] 3 siexaroox | 5| TEST 8 TT y) > Test © NORMAL Shoo hoc oc ° Yoo s ° ONORMAL 7 sraK Block [LE ° =) ise * HL Sess [ee }— tun, [G4] ® srex ook TEST 85 TT J) > Q Test © NORMAL Shoo ehoc Age ° Yoo 3 o ONORMAL ’ ‘512K BLOCK |G, ° ie & [sl Srest [a] toon ([ F—— 2 srexatoox [a] TEST 7 My > ores © NORMAL Shoo MOTOROLA MEMORY DATA 24173

ORDERING INFORMATION

(Order by Full Part Number) MCM 54410A X XX XX Part Number ‘Speed (60 = 60 ns. 70 = 70 ns. 80 = 80 ns) Package (N = 300-mil SOJ, Z = 100-mi Plastic ZIP Full Part Numbers— MCMS4410ANEO MCMSs410AN6OR2 - MCMS54#10AZ60 MGMB4410AN70 MCMSé410AN70R2 - MCMB4810AZ70 MCMS4410AN80 MCMS#410ANB0R2 - MCMS4410AZBO MOTOROLA MEMORY DATA 2174

Product Information

MCM54410AN60 specifications and overview.

Summary

1M x 4 CMOS Dynamic RAM Write Per Bit Mode

Description

1M x 4 CMOS Dynamic RAM Write Per Bit Mode

Source title MCM54410AN60 Datasheet(PDF) - Motorola, Inc

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