MCM44G64

MCM4464 MOTOROLA | Alldatasheet

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Technical content

Fast Static RAM Module Set Four MCM4464 modules comprise a full 1 MB of secondary cache for the R4000 processor. Each module contains nine MCM6709J fast static RAMs for a cache data size of 64K x 36. The tag portion, dependent on word line size, contains either two MCM6709J or one MCM6706J fast static RAMs. All input sig- nals, except A0 and WE are buffered using 74FBT2827 drivers with series 25 Ω resistors. The MCM6709J and MCM6706J are fabricated using high–performance sili- con–gate BiCMOS technology. Static design eliminates the need for internal clocks or timing strobes. All 1MB R4000 supported secondary cache options are available.

• Single 5 V ±/n63686172000000000000000010% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Module Access Time: 12/15/17 ns
• Zero Wait–State Operation
• Unified or Split Seconday Cache Modules are Available (See Ordering Information for Details)
• Word Line Sizes of 4, 8, 16, and 32 are Available (See Ordering Information for Details)
• The Pin Compatible MCM44256 Series is also Available to Support a Full 4MB R4000 Secondary Cache.
• Decoupling Capacitors are Used for Each Fast Static RAM and Buffer, Along with Bulk Capacitance for Maximum Noise Immunity
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground Planes PIN NAMES TDQ0 – TDQ7 TAG Data Input / Output. . . For proper operation of the device, VSS must be connected to ground. Order this document by MCM4464/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT

80 LEAD SIMM — TOP VIEW

66* 68* VSS 80 79 V CC TDQ6 TDQ2 VSS DQ29 DQ30 DQ32 DQ1 TDQ3 TDQ5 TDQ7 VSS NOTE: Pin assignment is for unified cache. For split cache option, Pin 68 becomes Address MSB (A15) and Pin 66 is NC. REV 1  Motorola, Inc. 1994

DQ0 – DQ3 W MCM6709J E G A3 – A15A3 – A15 DQ0 – DQ35 TCS DCS OE WE TDQ0 – TDQ7 74FBT2827 DRIVER

4 WORD

TAG OPTIONS: MCM6709J MCM6706J MCM6706J MCM6706J W G DQ0 – DQ7 A2 – A14 E 64K x 8 TAG

8 WORD

(A0 NOT USED)

16 WORD

(A0, A1 NOT USED)

32 WORD

(A0, A1, A2 NOT USED) W G DQ0 – DQ7 A2 – A14 E W G DQ0 – DQ7 A2 – A14 E W G DQ0 – DQ7 A3 – A15 E

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VCC – 0.5 to 7.0 V Voltage Relative to VSS Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 10 W Temperature Under Bias Tbias – 10 to + 85 °C Operating T emperature TA 0 to + 70 °C Storage Temperature Tstg – 25 to +125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage (DQ0 – 35, TDQ0 – 7, WE, A0) (A1 – A15, OE, DCS, TCS) VIH 2.2 2.0 VCC + 0.3 V* VCC + 0.3 V* V Input Low Voltage VIL – 0.5** — 0.8 V * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns) ** VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Symbol Min Typ Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I)   ± 10 µA Output Leakage Current (G, xCS = VIH, Vout = 0 to VCC ) Ilkg(O)   ± 10 µA AC Supply Current (G, xCS = VIL, Iout = 0 mA) ICCA   1850 mA Output Low Voltage (IOL = + 8 mA) VOL   0.4 V OUtput High Voltage (IOH = – 4.0 mA) VOH 2.4   V Note: Good decoupling of the local power supply should always be used. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance (A0, WE ) (A1 – A15, OE, DCS, TCS) C in C in 110 pF pF Input/Output Capacitance C out  10 pF This devices on this module contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high–imped- ance circuits. These BiCMOS memory circuits have been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The module is in a test socket or mounted on a printed circuit board and transverse air flow of at leat 500 linear feet per minute is maintained.

AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE (See Notes 1 and 2) –12 –15 –17 Parameter Symbol Min Max Min Max Min Max Unit Notes Address Access Time tAVQV — 12 — 15 — 17 ns A0 Access Time tA0QV — 10 — 12 — 14 ns Data/Tag Enable Access Time tELQV — 12 — 15 — 17 ns Output Enable Access Time tGLQV — 9 — 10 — 11 ns Output Hold from Address Change tAXQX 4 — 4 — 4 — ns Output Hold from A0 Change tA0XQX 4 — 4 — 4 — ns Data/Tag Enable Low to Output Active tELQX 2 — 2 — 2 — ns 3, 4 Data/Tag Enable High to Output High–Z tEHQZ 1 9 1 10 1 11 ns 3, 4 Output Enable Low to Output Active tGLQX 1 — 1 — 1 — ns 3, 4 Output Enable High to Output High–Z tGHQZ 1 9 1 10 1 11 ns 3, 4 NOTES: 1. WE is high for read cycle. 2.Enable timings are the same for both DCS and TCS. 3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B. 4.This parameter is sampled and not 100% tested. OUTPUT Z0 = 50 Ω R L = 50 Ω VL = 1.5 V Figure 1A Figure 1B 5 pF +5 V OUTPUT 255 Ω 480 Ω AC TEST LOADS The table of timing values shows either a minimum or a maximum limit for each param- eter. Input requirements are specified from the external system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never pro- vides data later than that time. TIMING LIMITS

READ CYCLE 1 (See Note) Q (DATA OUT) A1 – A15 DATA VALIDPREVIOUS DATA VALID tAVQV tA0VQV tA0XQX tAXQX NOTE: Module is continuously selected (DCS or TCS = VIL, OE = VIL). READ CYCLE 2 (See Note) tEHQZ DATA VALID tGHQZ tELQX tELQV OE (OUTPUT ENABLE) Q (DATA OUT) A1 – A15 tGLQX tGLQV DCS /TCS (DATA/TAG ENABLE) tAVQV tA0VQV NOTE: Address valid prior to or coincident with DCS or TCS going low.

WRITE CYCLE 1 (WE Controlled, See Notes 1 and 2) –12 –15 –17 Parameter Symbol Min Max Min Max Min Max Unit Notes Address Setup Time tAVWL 5 — 5 — 5 — ns A0 Setup Time tA0VWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 15 — 17 — ns A0 Valid to End of Write tA0VWH 10 — 12 — 14 — ns Write Pulse Width tWLWH tWLEH 7 — 10 — 12 — ns Data Valid to End of Write tDVWH 6 — 7 — 8 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 4 0 5 0 6 ns 3, 4 Write High to Output Active tWHQX 3 — 3 — 3 — ns 3, 4 Write Recovery Time tWHAX 0 — 0 — 0 — ns Write Recovery Time – A0 tWHA0X 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of DCS or TCS low and WE low. 2.Enable timings are the same for both DCS and TCS. 3. Transition is measured 200 mV from steady–state voltage with load of Figure 1B. 4.This parameter is sampled and not 100% tested. WRITE CYCLE 1 tA0VWL DATA VALID tAVWH tWHDX tWLQZ tWHQX HIGH–Z A1 – A15 WE (WRITE ENABLE) DCS /TCS (DATA/TAG ENABLE) Q (DATA OUT) D (DATA IN) tWLEH tWHAX tAVWL tWLWH tDVWH tWHA0XtA0VWH HIGH–Z

WRITE CYCLE 2 (DCS or TCS Controlled, See Notes 1 and 2) –12 –15 –17 Parameter Symbol Min Max Min Max Min Max Unit Notes Address Setup Time tAVEL 0 — 0 — 0 — ns A0 Setup Time tA0VEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 15 — 17 — ns A0 Valid to End of Write tA0VEH 10 — 12 — 14 — ns Data/Tag Enable to End of Write tELEH, tELWH 12 — 15 — 17 — ns Data Valid to End of Write tDVEH 6 — 7 — 8 — ns Data Hold Time tEHDX 5 — 5 — 5 — ns Write Recovery Time tEHAX 5 — 5 — 5 — ns Write Recovery Time – A0 tEHA0X 5 — 5 — 5 — ns NOTES: 1. A write occurs during the overlap of DCS or TCS low and WE low. 2.Enable timings are the same for both DCS and TCS. WRITE CYCLE 2 tEHDXtDVEH tEHAX tELWH tELEH tAVEL DATA VALID HIGH–Z WE (WRITE ENABLE) DCS /TCS (DATA/TAG ENABLE) Q (DATA OUT) D (DATA IN) A1 – A15 tAVEH tEHA0X tA0VEL tA0VEH

ORDERING INFORMATION

(Order by Full Part Number) MCM 44X64 XX XX Motorola Memory Prefix Part Number Speed (12 = 12 ns, 15 = 15 ns, 17 = 17 ns) Package (SG = Gold Pad SIMM) Part Number Unified/Split Word Line Size TAG Depth MCM44A64 Unified 4 64K MCM44B64 Unified 8 32K MCM44C64 Unified 16 16K MCM44D64 Unified 32 8K MCM44E64 Split 4 64K MCM44F64 Split 8 32K MCM44G64 Spllit 16 16K MCM44H64 Split 32 8K Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. MCM4464/D /C0042/C0077/C0067/C0077/C0052/C0052/C0054/C0052/C0047/C0068/C0042 ◊ CODELINE TO BE PLACED HERE