MCM40L512S10

MCM40512 MOTOROLA | Alldatasheet

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FEB 19 199t Order this data sheet MOTOROLA by MCM40512/D

2 SEMICONDUCTOR Giessen

~ TECHNICAL DATA MCM40512 Product Preview MCM40L512 512K x 40 Bit Dynamic Random Access Memory Module for Error Correction Applications The MCM40512S and MCM40L512S are 20M, dynamic random access memory 1 | (2) (DRAM) modules organized as 524,288 x 40 bits. The module is a double-sided =] 72-lead single-in-line memory module (SIMM) consisting of twenty MCM514256A [=| DRAMs housed in 20/26 J-lead small outline packages (SOJ), mounted on a =I substrate along with a 0.22 uF (min) decoupling capacitor mounted under each =I DRAM. The MCM514256A is a 1.0 1 CMOS high speed, dynamic random access =] memory organized as 262,144 four-bit words and fabricated with CMOS silicon-gate e process technology. 2 | « Three-State Data Output =| « Early-Write Common I/O Capability = « Fast Page Mode Capability = © TTL-Compatible Inputs and Outputs 1S * RAS Only Refresh | « CAS Before RAS Refresh 36 [SI * Hidden Refresh 7 * 512 Cycle Refresh: a (=| MCM40512 = 8 ms (Max) = MCM40L512 = 64 ms (Max) * Consists of Twenty 256K x 4 DRAMs, and Twenty 0.22 yF (Min) Decoupling Capacitors = Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection = « Fast Access Time (trac): =| MCM405125-70 +7 ns (Max) = MCM40512S-80 = 80 ns (Max) iS MCM40512S-10 = 100 ns (Max) | Low Active Power Dissipation: =| MCM40512S-70 = 4.51 W (Max) S MCM40512S-80 = 3.96 W (Max) || MCM40512S-10 = 3.41 W (Max) iS © Low Standby Power Dissipation: 7 TTL Levels = 220 mW (Max) Oma CMOS Levels (MCM40512) = 110 mW (Max) (MCM40L512) = 22 mW (Max) PINOUT [ PINNAMES [ie Trams [ rin Trane [ rin [Wene [ Pin [None [ Pin [nave [Pr [name ] | oe bagi 1... Batatnpuvoutput Peo Socr " EiorContatte boaue CASO-CASS ... . Column Address Strobe [3 foos [is [os [27 [oo | | vss | 51 [oc | 62 [oom | | rotten nr Reaarinte Input [7 [oo [ve as [oe [omer | ss [oan | er | or | | [oe [oe [20 [oo [se [nc | a [arse] se [cer | os_| Poe | | [-8 [eos [ar [oczo [so [rasa | as [asi] 67 | oar] co | oo | | [0 [Moc [2 [005 | [ruse | as [eces | se | ooze [70 Pos | Dave [a [ooer [w ecci [a [we | voo [fee [2 [me [2 [eos | Jecce] w | co [ co [oae] v2 | vss | This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. a & MOTOROLA @ © MOTOROLA INC., 1990 wrsee

CASO: TS vor as TASH OE ow pons vos} 0 | 0s_ao-ns ow ee ee os a eee oS —- weap Fee #8 = Volo toe a OE Ww AQ-AB_VO4 o VO4__AQ-AB w | ee ee RAS | RAS aa 103 9] 8 a: Or Ww AO-AB_VO4 o wos Aoas WO a DQ12-DQ15 | — — vot © vot CASI aS [Gg ASI +} ss i nr bh Ra oe ® too tos a & Ww. AQ-A8__ /O4 o 04 __A0-A8 Ww | DQ16-DQ19 a oS i) ene oA fed © CAS \\S2 8 pe ae na OF W AQ-A8__VO4 | O04 __AO-A8 W OF re ee ons vor 801 we SE FS oe nD aan FaS|} ——} 9 FASS OW Ao-AB yout ——o———[ oa _ao-as ow a a oS ors i) a a [a oS ew tog} 0 lio a Ww AO-A8 04 res yO4__AO-AB Ww a a Se —__ vot o vot — os Tce os] ——}- os RAS [gd AAS RAS wos ° v3 _ aS oe WW wo-as_vos} 0 vos_so-rs WO LT eccoeces = 1 I ors) ems fa] ee oS — , V —-| co Oy no-rs vost —o——} vo4_aons WOE a Se ems ol ene ba Es 0 ie HAS oa 193-208 a oe Ww AO-AB_VO4 o vos Aves WO AQ-AS- Vee a Uo-U19 i 0.22 uF (MIN) | Vsg O's wets [ Pinname | 70ns] sons 100ns | PDI NC NC NC PD2 Vss Vss Vss PD3 Vss No Vgs | PD4 Nc | vss | Vss | a | MOTOROLA MCM40512 « MCM40L512

ABSOLUTE MAXIMUM RATINGS (See Note) This device contains circuitry to [Rating TT symbot [value] unit | protect the inputs against damage ~~ - fields; however, it is advised that Voltage Relative to Vg Vin: Vout —1to+7 v normal precautions be taken to (For Any Pin Except Voc) avoid application of any voltage Data Output Current per DQ Pin [50m | higher than maximum rated voltages pu reo [ow | to these high impedence circuits. [Fowrosspain SS P| as | Uw NOTE: Permanent device damage may ocour if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDI- TIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS [Parameter syembot [win [typ [mex [unit | rots | | ves | o [io fo | RECOMMENDED OPERATING CONDITIONS Voc Power Supply Current lect mA MCM40512-70, tac = 130 ns 820 MCM40512-80, tag = 150 ns 720 MCM40512-10, tac = 180 ns 620 Voc Power Supply Current During RAS only Refresh Cycles loca MCM40512-70, tac = 130 ns 820 MCM40512-80, tac = 150 ns 720 MCM40512-10, tac = 180 ns. 620 Voc Power Supply Current During Fast Page Mode Cycle loca mA MCM40512-70, tac = 40 ns 620 MCM40512-80, tac = 45 ns 520 MCM40512-10, tac = 55 ns 420 Voc Power Supply Current (Standby) (RAS = CAS = Vgc - 0.2 V) _MCM40512 | Iocs mA MCM40L512 Voc Power Supply Current During CAS Before RAS Refresh Cycle loce mA MCM40512-70, tac = 130 ns 820 MCM40512-80, tac = 150 ns 720 MCM40512-10, tac = 180 ns 620 | Output Leakage Current (CAS at Logic 1, Vgg < Vout $ Voc) tego) | -20 | 2 | wa | | NOTES: H 1. All voltages referenced to Vgg. 2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. MCM40512 « MCM40L512 MOTOROLA

CAPACITANCE (f = 1.0 MHz, Ta = 25°C, Voc = 5 V, Periodically Sampled Rather Than 100% Tested) rot ara i VO Gapactance (EOO0-ECC7) Soo | — [| a [oor | + | NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 At/ AV. AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V t 10%, Ta = 0 to 70°C, Unless Otherwise Noted) READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4) [neem [sae ane oe ef te | | |e FAS Pulse Width (Fast Page Mode) | treLREH 100,000 | 80 | 100,000 | 100 | 100,000 | ns |_| (continued) NOTES: 1. Vip min and Vy_ max are reference levels for measuring timing of input signals. Transition times are measured between Vj} and Vi. 2. Aninitial pause of 200 us is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between Vj} and Vj, (or between Vj_ and Vj}4) in a monotonic manner. 4. AC measurements ty = 5.0 ns. 5. The specifications for tac (min) and tayyc (min) are used only to indicate cycle time at which proper operation over the full temperature range (0°C < Ta < 70°C) is assured. 6. Measured with a current load equivalent to 2 TTL (~200 nA, + 4 mA) loads and 100 pF with the data output rip points set at Vo} = 2.0 Vand VoL = 08 V. 7. Assumes that tcp <tacp (max). 8. Assumes that tcp 2 tacD (max). 9. Assumes that tap 2 (Rap (max). 10. torr (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Operation within the tap (max) limit ensures that tac (max) canbe met. tacp (max) is specified as areference point only; ftacp is greater than the specified tcp (max) limit, then access time is controlled exclusively to tc ac. 12. Operation within the trap (max) limit ensures that tac (max) can be met. tp (max) is specified as areference pointonly;iftrap is greater than the specified trap (max), then access time is controlled exclusively by ta. | MOTOROLA MCM40512 « MCM40L512

READ AND WRITE CYCLES (Continued) TAS Precharge Time (Page Mode | tceHceL | tcp 10 Cyle Only) Column Address Hold Time tRELAX 75 Referenced to RAS Read Command Setup Time waoe. [ros | o | — [oo [ -— fo | - [ow] | Read Command Hold Time tcenwx | taCH 13 Reterenced to CAS Read Command Hold Time treHWx | ARH Referenced to RAS ‘Write Command Hold Time tcerwH | ‘WoH 15 15 Referenced to CAS Write Command Hold Time thew | ‘wor 75 Referenced to RAS [oaanseuptire [own | os_| © | - [oe] —- |o] — |= |mn Data in Hold Time Referenced to tRELDX 75 RAS Refresh Period mcm40512 | tavav | tRFSH 8 8 8 MCM40L512 64 64 64 CAS Setup Time for CAS Before trecce. | csr 10 10 RAS Refresh TAS Hold Time for CAS Before RAS | treLcEH | tcHR 30 Refresh CAS Precharge Time tor CAS tceHcEL | topT Before RAS Counter Test CAS Precharge Time cence | tpn [19 [ — [io | - [os | - [os] | NOTES: 13. Either tH oF tacH must be satisfied for a read cycle. 14. These parameters are referenced to CAS leading edge in random write cycles. 15. Early write only (twos 2 twcs (min)). 16. twogisnotarestrictive operating parameter. Itis included in the data sheet as an electrical characteristic only; iftwos2twcs (min), the cycle ' is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not satisited, | the condition of the data out (at access time) is indeterminate. | 17. To avoid bus contention and potential damage to the module, RASO and RAST may not be active low simultaneously. Similarly, RAS2 and | RASS may not be simultaneously active low. MCM40512 ¢ MCM40L512 MOTOROLA

tRAS’ tAP: Ras) IH Vi- CAS ‘ASC Kem] feo “AH wmeses SO ae KOE KAKA {RAH tacH tacs lf > Ya" " ve XXOXXXXXXXXKY XXXXX EARLY WRITE CYCLE tae 'RAS tRP’ Ras (VIN Vit = tesH a ‘cre oo | CAS {|} Vi ~ , tur Kt} taSC’ ‘AH vmeses "OR as KOLB KXXIXIXKKKKEENR tCWL ae ve " ve XXXXXXXXXAM |_| | KXXXXXXXXXKXKX _ eer tT | ‘os SF 7 DH Ve | “ows” XXXXXXXXXK waioowm KXXXXXXXXXXXKAXXX a | MOTOROLA MCM40512 « MCM40L512

• = Vn - 'RASP’ | ‘RP Vi = == - re tRSH ‘aco P P ‘opn I a Chet oS “ 7AH - Aroma rooneses: XX) sO SS KO tt KOO Ses AXXKAXX or a erie tril SE ‘1 < vH ~ TH | RYF RYF XXX Woe QA ) ) MAA Te re ni a L | a >| Dao-pa31 You ~ ln} VALID ¥ Ly VALID ¥ Ky a {DATA OUT) _ (x) HX) LN DATA Yo. ‘oF torr ‘oFF 'OLZ tz CLZ FAST PAGE MODE WRITE CYCLE (EARLY WRITE) tRASP’ tap as WT I icp P to Se ee ee oS Vit NS NS RAH A "AH t ‘RAD cS, twoH tworR TI ‘WCH < ‘HK YYYyyyyyv KX) we >V/VYVVYVVY W i" — XOXOXO YN] YET PP XXXXXX J Spedeep ee Te ‘DH | "pany OXXKKX KOE Wak KOK BER KX Bie KXXXXXXX | . —$§orn a MCM40512 « MCM40L512 MOTOROLA

(W and A8 are Don't Care) RAS 1H YL torP 'RPC — VHT AS Vie ~ ‘ASR 'RAH vu — YY ROW VAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVATAVAVAVATAYAYATAYAYANA AAT ve - XK ates 3 OXXXXXXKKXXXXAAKAAAAAAK KAKA ao-0031 You — Yo. -— CAS BEFORE RAS REFRESH CYCLE (W and AO to A8 are Don’t Care) Re tras” <— np a «(VIH > AAS “vu ~ tapc tos ’ tcpn CHR Vin CAS Me ‘orF Dao-0031 VoH — i (DATA OUT) HIGH-Z Vo. ~ ee MOTOROLA MCM40512 « MCM40L512

HIDDEN REFRESH CYCLE (READ) tRC TRAS ~ tRAS’ Peli AS Vin Vit | topp* tcpn’ CAS vn 'RAD h - tr Ss tCAH taSR lq | H— so | Vin = roonesses J OE SRSSKOR Saws KXXXXXXXXXXXXXXXXXAXK [ns L a) 'RRH | © it RONG] XEOEROROOROOOI ‘aw torr tRAC Vow - toz HIDDEN REFRESH CYCLE (WRITE) tae tRAS = YO ‘ras ‘RP Vit ‘orp ‘op — HOT CAS Vi = — tasr | Vin AS wom ROLEX se HXXXRRRRRRKRRRERKKNE et ‘wes ‘WCH — VIH — Ba ceo MIM cexcecoxeconceonc wi tl ‘on | DS" | Dao-pas1 iH ~ VYVYYVYYYY VY YY VY | (ATAIN) [Ruane KXXXKXXXMKXXXAAA a MCM40512 » MCM40L512 MOTOROLA

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE ‘RAS tap Vu - ‘RSH |_| BAS 1H Vit = —. VIH~ CAS Vit = se ---— ‘oat Mee roonesses "” XXXXXXXXXKXXNXY cousmnoonessye XXXXXXXAXXAAX Lee ‘tf READ CYCLE af | RAL” [| ort Vow 'Res — tcwz RRH — VHo WI RXXXXXXXXXXKX? | - ‘nore XX aaa | Ee > WRITE CYCLE t -—>| ‘om ‘wou w YO ‘we VYVVVVVY ©" YRKKKKXEXEKK | _AXXXXXXXKXKKX tos tOH Vu vanes SEKKRRKKKRKKKHON ws KEKKKXKKKKREK I ——— irre | MOTOROLA MCM40512 « MCM40L512

DEVICE INITIALIZATION stay inactive for the minimum (trp) time. The former is for the completion of the cycle in progress, and the latter is for the de- On power-up an initial pause of 200 microseconds is re- vice internal circuitry to be precharged for the next active cycle. quired for the internal substate generator pump to establish the Data out is not latched and is valid as long as the CAS clock correct bias voltage. This is to be followed by a minimum of is active; the output will switch to the three-state mode when eight active cycles of the row address strobe (clock) to initialize the CAS clock goes inactive. To perform a read cycle, the write the various dynamic nodes internal to the module. During an (W) input must be held at the Vj} level from the time the CAS extended inactive state of the module (greater than 4 millisec- clock makes its active transition (tag) to the time when it tran- onds with device powered up), the wake up sequence (8 active sitions into the inactive (tH) mode. cycles) will be necessary to assure proper device operation. WRITE CYCLE ADDRESSING THE RAM __Awrite cycle is similar toa read cycle except that the write The nine address bus pins on the device are time multi- (W) clock must go active (Vj__level) at or before the CAS clock plexed with two separate 9-bit address fields that are strobed goes active at a minimum twcs time. If the above condition is atthe beginning of the memory cycle by two clocks (active neg- met, then the cycle in progress is referred to as an early write ative) called the row address strobe (RAS) and the column ad- cycle. In an early write cycle, the write clock and the datain are dress strobe (CAS). A total of eighteen address bits will decode referenced to the active transition of the CAS clock edge. one of the 524,288 word locations in the device. The column There are two important parameters with respect to the write address strobe follows the row address strobe by a specified cycle: the column strobe to write lead time (tcw ) and the row minimum and maxium time called tacp, which is the row to strobe to write lead time (try). These define the minimum column strobe delay. This time intervalisalsoreferredto asthe _ time that RAS and CAS clocks need to be active after the write multiplex window which gives flexibility to a system designer operation has started (W clock at Vj, level). to set up the external addresses into the RAM. These condi- tions have to be met for normal read or write cycles. This initial PAGE-MODE CYCLES portion of the cycle accomplishes the normal addressing of the device. These are, however, other variations in addressing the Page mode operation allows fast successive data opera- module: the refresh modes (RAS only refresh, CAS before tions at all 512 column locations on a selected row. Page ac- RAS refresh, hidden refresh), and another mode called page cess (tac) is typically half the regular RAS clock access mode which allows the user to column access all words within (tRAc) on the Motorola 1M dynamic RAM. Page mode opera- a selected row. The refresh mode and page mode operations tion consists of holding the RAS clock active while cycling the are described in more detail in later sections. CAS clock to access the column locations determined by the ~ 10-bit column address field. The page cycle is always initiated with a row address being READ CYCLE provided and latched by the RAS clock, followed by the column Aread cycle is referred to as anormal read cycle to differen- address and CAS clock. From the timing illustrated, the initial tiate it from a page mode read cycle, which is covered in a later cycle is a normal read or write cycle, that has been previously section. described, followed by the shorter CAS cycles (tp). The CAS The memory read cycle begins with the row addresses valid cycle time (tpc) consists of the CAS clock active time (tcas). and the RAS clock transitioning from Vjj4to the Vj, level. The aNd CAS clock precharge time (tcp) and two transitions. In TAS clock must also make atransition from Vjytothe Vj, level__‘ractice, any combination of read and write cycles can be per- atthe specified tacp timing limits when the column addresses ___‘f0r™ed to suit a particular application. are latched. Both the RAS and CAS clocks trigger a sequence of events which are controlled by several delayed internal REFRESH CYCLES clocks. Also, these clocks are linked in such a manner that the access time of the device is independent of the address multi- The dynamic RAM design is based on capacitor charge plex window. The only stipulation is that the CAS clock must be storage for each bit in the array. This charge will tend to de- active before or at the taop maximum specification for an ac- grade with time and temperature. Therefore, to retain the cor- cess (data valid) from the RAS clock edge to be guaranteed rect information, the module needs to be refreshed at least (tRAC)- If the tap maximum condition is not met, the access once every 8 milliseconds. This is accomplished by sequen- (tac) from the CAS clock active transition will determine read tially cycling through the 512 row address locations every 8 mil- nal RAS signal is available. This gating feature on the CAS normal read or write operation to the module will also refresh clock will allow the external CAS signal to become active as all the words associated with the particular row(s) decoded. ‘soon as the row address hold time (tRAH) specification has | been met and defines the tac¢p minimum specification. The RAS-Only Refresh | time difference between tagp minimum and tap maximum | can be used to absorb skew delays in switching the address __In this refresh method, the system must perform a | bus from the row to column addresses and in generating the RAS-only cycle on 512 row addresses every 8 milliseconds. ' TAS clock. The row addresses are latched in with the RAS clock, and the Once the clocks have become active, they must stay active associated internal row locations are refreshed. As the for the minimum (tRas) period for the RAS clock and the mini- heading implies, the CAS clock is not required and must be i mum (tgs) period for the CAS clock. The RAS clock must inactive or at a Vj} level. ee MCM40512 « MCM40L512 MOTOROLA

been low (by togp). This activates the internal refresh counter while the external address input supplies the column address. as CAS is held active (hidden refresh). Hidden Refresh 1. Write “Os into all memory cells (normal write mode). refresh is performed by holding CAS at Vj, and taking RAS cycle. Repeat this operation 512 times. a — cycle. Repeat this operation 512 times. The internal refresh counter of the device can be tested with 3. aCAS before RAS refresh counter test. This refresh counter 5. Repeat steps 1 to 4 using complement data. Figure 1. Hidden Refresh Cycle

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0.400 BSC

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ORDERING INFORMATION

(Order by Full Part Number) MCM 40512 0r40L512 _x xx Motorola Memory oe Le Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns) Part Number Package (S = SIMM, SG = Gold Pad SIMM) Full Part Numbers - MCM40512S70 _ MCM40512SG70 MCM40512880 MCM40512SG80 MCM40512510 MCM40512SG10 MCM40L512870 MCM40L512SG70 MCM40L512880 MCM40L512SG80 MCM40L512810 MCM40L512SG10 i MCM40512 « MCM40L512 MOTOROLA