MCM40100

MCM40100 MOTOROLA | Alldatasheet

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@ SEMICONDUCTOR Sie ~ TECHNICAL DATA Product Preview O10 1M x 40 Bit Dynamic Random Access Memory Module for Error Correction Applications fo) The MCM40100S and MCM40L100S are 40M, dynamic random access memory [EI (DRAM) modules organized as 1,048,576 x 40 bits. The module is a 72-lead = [| single-in-line memory module (SIMM) consisting of ten MCM514400 DRAMs housed =I in 20/26 J-lead small outline packages (SOJ), mounted on a substrate along with a Ss 0.22 uF (min) decoupling capacitor mounted under each DRAM. The MCM514400 is =I a CMOS high speed, dynamic random access memory organized as 1,048,576 = four-bit words and fabricated with CMOS silicon-gate process technology. = [| © Three-State Data Output Ee * Early-Write Common I/O Capability =I « Fast Page Mode Capability = © TTL-Compatible Inputs and Outputs =| * RAS Only Refresh 6 |S « CAS Before RAS Refresh * Hidden Refresh a I [| * 1024 Cycle Refresh: e MCM40100 = 16 ms (Max) MCM40L100 = 128 ms (Max) e « Consists of Ten 1M x 4 DRAMs, and Ten 0.22 uF (Min) Decoupling Capacitors = _. * Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection =] [| * Fast Access Time (tac): = MCM40100S-80 = 80 ns (Max) EI MCM40100S-10 = 100 ns (Max) = « Low Active Power Dissipation: =I = MCM40100S-80 = 5.78 W (Max) es [| MCM40100S-10 = 4.95 W (Max) = * Low Standby Power Dissipation: R [e) TTL Levels = 110 mW (Max) CMOS Levels (MCM40100) = 55 mW (Max) MMO = NN [__enawes [pn [Nene | Fn [vanw | Pe [Rone] Pn [Wine | Fn [hone [Pr [Rone] | EocoWES07 dra concten Oat CASO-CASS ... Column Address Strobe | 2 [oor] ws [as | 27 [oor | co | ves | s1_| oa | 69 [oars | GB ooo. Ganguration Detection |_+ [oa | we | ae |e [a | oo | oaso] se [oces | e+ | oaat | Ves Ground All power supply and ground pins must be Fhe [pepe p ea forse afer connec or proper operation othe eves [2 [eas | 20 | oor | ve [as | | rasa] 56 [cer | ee | Poe | ee OE eo © eee ae [one [oe [ase [oe [acer [ae [om [0 [roe | [a [xe [a Yooer | Peco a Pw [ee [veo | me econ] Le [mo] [os | a6 [eoce] [co | eo [oa] 7 | vos | This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. | & MOTOROLA @ © MOTOROLA INC., 1990 NPSZS

—_ vO Dao CASO rs voz pat FASO RAS vo3 poe OE WH AD-AQ__VO4 a3 — TOT Dos on vo bas RAS vos 006 Or MW AQ-AQ_vO4 par a —_ vO Doe CAS woe pas RAS vos Dato OF Was part — og vor bai2 oS ye woe pais RA vos pag OF WD AD_ 04 pars a 8 io bot? pas vo2 DQI7 ~ vO3 bas W AD-AG_VO4 aig a = vor pazo _— CAS voe paat RAS2 RAS vos p22 OF Wong 04 p23 oS as vot pa24 AS? ee woe Das ze vos 0026 EW vo-ag_v08 027 a __ vOt D028 GAS wo2 Daze RAS vos 0a30 OF Wong 04 D031 _ = TO ECCO Pt ds woe Ecc! nw vos Ecce oe UW AD-AS OS ECC3 7A vot ECC4 a vo2 ECCS So vos ECOB or UW AO-AS _VO4 ECC? W A0-A9 La ea U0-U9 | 0.22 ywF (MIN) Presence Detect Pin Out [Finvme [ 700 | One [| i00ns | PDI Vss Vss Vss | pb2 Vss | Vss | Vss i PD3 vgs | NC | Vgs : PD4 NC | vss | Vss | [co | ves [ vss | vss | | MOTOROLA MCM40100 « MCM40L100 | 2

ABSOLUTE MAXIMUM RATINGS (See Note) This device contains circuitry to [ating TT symbot [value [unit] protect the inputs against damage ~ fields; however, it is advised that Voltage Relative to Vgg Vin» Vout ~1to+7 v normal precautions be taken to (For Any Pin Except Vcc) avoid application of any voltage Data Output Current per DO Pin Lo | higherthan maximum rated voltages vet orcien | tout _| [_ma_| to these high impedence circuits. [poweroseraon St PP iw NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS. es ee ed ‘Supply Voltage (Operating Voltage Range) | voc | 45 | 50 | 55 | v a [vss [oo [eo fo | RECOMMENDED OPERATING CONDITIONS Voc Power Supply Current lect MCM40100-80, tac = 150 ns 1050 MCM40100-10, tac = 180 ns 900 Voc Power Supply Current During RAS only Refresh Cycles loca MCM40100-80, tc = 150ns 1050 MCM40100-10, tc = 180.ns 900 Voc Power Supply Current During Fast Page Mode Cycle loca mA MCM40100-80, tc = 150 ns. 700 MCM40100-10, tac = 180 ns 600 Voc Power Supply Current (Standby) (RAS = CAS = Vog- 0.2 V) MCM40100 | Iccs 10 MCM40L100 4 Voc Power Supply Current During CAS Before RAS Refresh Cycle locs MCM40100-80, tac = 150 ns 1050 MCM40100-10, tac = 180 ns 900 i Output Leakage Current (CAS at Logic 1, Vgg < Vout $ Voc) tg) | -20 | 20 | wa | | NOTES: 1. All voltages referenced to Vgg. 2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. MCM40100 « MCM40L100 MOTOROLA

CAPACITANCE (f = 1.0 MHz, Ta = 25°C, Vcc = 5 V, Periodically Sampled Rather Than 100% Tested) iret Captian [ce [| — | © [er | VO Capactance (0G0-Dast) | coon | - [ov [or | | VO Capacitance (E0C0-ECO7) [ coo | = | 7 [oo | | NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 At/ AV. AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4) FAS to Column Adoress Delay Time wwe [tran [ 15 | 4 [2 | so [ons | i | (continued) NOTES: 1. VjH min and Vj, max are reference levels for measuring timing of input signals. Transition times are measured between Vjy and Vi. 2. An initial pause of 200 us is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. : 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must : transition between Vj} and Vj, (or between Vj_ and Vj) in a monotonic manner. | 4, AC measurements ty = 5.0 ns. | 5. The specifications for tc (min) and tawc (min) are used only to indicate cycle time at which proper operation over the full temperature range | (0°C < Ta $ 70°C) is assured. | 6. Measured with a current load equivalent to 2 TTL (—200 n/A, +4 mA) loads and 100 pF with the data output trip points set at Vo} = 2.0 Vand Vol = 0.8 V. | 7. Assumes that tacp $ tacp (max). 8. Assumes that tcp 2 tac (max). | 9. Assumes that tRap 2 tRAD (max). | 10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output vottage levels. | 11. Operation within the tcp (max) limit ensures thattac (max) can be met. cp (max) is specified as a reference point only; if tcp is greater ; than the specified tcp (max) limit, then access time is controlled exclusively to tcac. | 12. Operationwithin the tap (max) limit ensures that tac (max) can be met. trap (max) is specified as a reference point only; if pap is greater | than the specified rap (max), then access time is controlled exclusively by taa- | MOTOROLA MCM40100 » MCM40L100

READ AND WRITE CYCLES (Continued) ~ [EAS to RAS Precharge Time toenner | tone [os | — fo | = [os [| CAS Precharge Tine (Page Mode Cyle On) | toence. | top | 10 | — | | — | =| | Row Address Setup Tine wwret | wsa [| o [| - [| o | = [os] | Row Address Hold Tine taeax | ean [ to | — [os [ = [oe | | Column Address Setup Tine woe | so [| eo [| — | o | = [ow] | Column Adeross Hol Tine toe | can [8 [ — [oo [ = [ow] | Column Address Hold Time Referenced tRELAX 75 to RAS Golumn Address to RAS Lead Time tavnen | mm | 4 [| — [ [| = [os [| Read Command Setup Time [mice | wes | o [| — [oo | = [ow] | Read Command Hold Time Referenced tceHwx | tRCH 13 to CAS Read Command Hold Time Referenced treHwx | tRRH 13 to RAS Write Command Hold Time Referenced tceLwH | 'wcH 15 to CAS Write Command Hold Time Referenced tReLwH | ‘wor 7s to RAS Write Command Pusse With | ww | we [os | — [2 | = [ow] | Write Command to RAS Lead Time wren | tam | 2 [ — | 2 | = [we] | Write Command to GAS Lead Time wecen | tom | 2 [| — [2 [ = [ow | | Dala in Setup Tine ovo | wos | o [ - [oo | = | rs [rts | Datain Hold Time [ceux | tow | 6 | = | 2 [=f ne [145 | DaiainHelg Tine Reteenceato RAS | inevox | town | 60 | — | 7 [| — [os [| Refresh Period mcm40100 | tavav | tAFSH 16 16 ms MCM40L.100 128 128 Write Command Setup Tine woe | wos [| o | — [ o [ = | os [ist] CAS HoldTine torCASBetore RAS Retest [tmeicen | toa | oo | — [ 2% | = | | | CAS Precharge to GAS Acive Time tence. | treo | o [ — [oe | = [al] | TAS Precharge Time tor CAS Before RAS tcEHCEL | tcPT 40 Counter Test CAS Precharge Time tenor. | toon [to [ [os | = [ow] | NOTES: 13. Either tay oF tacH must be satisfied for a read cycle. 14, These parameters are referenced to CAS leading edge in random write cycles. 15. Early write only (twos 2 twes (min). 16. twcgisnotarestrictive operating parameter. Itis included in the data sheet as an electrical characteristic only; iftwos=twcs (min), thecycle isan early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not satisifed, the condition of the data out (at access time) is indeterminate. MCM40100 « MCM40L100 MOTOROLA

tras’ RP: Rag MIH vi tesH - 2S os Ven = QS ye tasR 0 — pat —* wweses SO is OL SE KXXXXKKKHKNNEERR TRAH 'RCH tacs Lew Vine v * ™” SYREN KKK = ‘a a 00-0031 VoH ~ Ao Ir] EARLY WRITE CYCLE tRAS * tap pas Vin vi ~ tcsH ‘orp .| ‘geo rss | ~ “AS a N KA 4 Ve - asc ter bao) ‘CAH : rooresses OK antes KOK SSSR KXXXXXXXXXXXXXXAXX tcwL a VIH ~ ‘we WY RXXXMRRRRN [TT "ARKXKRRRERRRRK Vu - | “pani 1" RXXXXXXXXKK woowa KXXXXXXXXXAXKAXXX k¢—— pun a MOTOROLA MCM40100 « MCM40L100

~ RS Viq ~ ‘se ey Vit > i — tosh 2 re tASH tro P tc Fa SSa aR CAS " al tr — Vi ~ ws XXXKXXXX) \\y YW XXX “ Saal ce ci = mre | ad ad dao-p031 You ~ Ln} VALID Lon VALID * Cae (DATAOUT) aus Xx oan} XM Dara tor tof tort we FF in F tclz ~ FAST PAGE MODE WRITE CYCLE (EARLY WRITE) ta ‘RP =e |ASP” fi VL | x0 <—— tre RSH cP P tc Fare i CAS VIL — NM MS A 'RAl Via - romesses "* ” YL EES KON ERE KO EEE KSEE KKK i ie ‘RAD ICS, ‘wou twor [>I ‘wok _ Vin VYVY P 4 YVYVYY Ww an OOOO YN | Nl i AXXXXXX ‘oH — Ley “nny XXXXXXXXA Bak HOOK SiR KOA tire KXXXXXXX a MCM40100 » MCM40L100 MOTOROLA

(W and AQ are Don’t Care) |< tc. Ve - RAS 1H Yi tcp trec —. “IH ~ oS ML TASR 'RAH vn ~ YY ROW AAV AVAVAVAVAVAVAVAVAVAVAVAVATAVAVAVAVAVAVAVAYAYAYATANS aan XX aoeness OXXXXXXXXAKXAKAAKAAARKARAAA pao-Das1 VoH ~ {DATA OUT) Hi 2 Vo. - CAS BEFORE RAS REFRESH CYCLE (W and AO to AQ are Don’t Care) tae 'RAS —— tap ae (YH AAS vu = tRPC tcsR’ 'cHR t —. WH ~ cen CAS Vi = torr oa0-pas1 You ~ — i (DATA OUT) HIGHZ i MOTOROLA MCM40100 » MCM40L100

HIDDEN REFRESH CYCLE (READ) tae tas ———| ~ _ tras tre RE Vin Vit ~ tcRP topn’ 7 RA , tRAHT , ie ‘CAH vy SS voonesses |" XXL ARRSKO SRE KXXXXXXXXXXXXXXKKKKKX [ns | 'RRH | w , ~ OXXXXXXKY ea DXXXXKXKXAXXXKXK IL trac ‘aA toFF von - toz ~ HIDDEN REFRESH CYCLE (WRITE) ‘Ro 'RAS Vw 'RAS tRP RAS Vi tcrP’ top ‘u a 'RAL tRAHT} Sy 'CAH task | Vin > aoonesses | XX acenessK OR Aamnees KAXKXXKXXXKKXKAXMAXAMA twor' 1 | a | ‘wes 'WCH ye | om eco MN cocoonecoKeonKeonKen wi : ‘on 'DS” Wu - | “ony YR wanna KXXXXXXXKXAMAMKKKENA <—— !pHR EEE | MCM40100 « MCM40L100 MOTOROLA

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE ‘RAS tap RAS Vit = Viq~ CAS Vit = Vee ADDRESSES a KXXXXKXKAXAXAAN A coun anoressK XX KXKKXKXXAXX L ke y READ CYCLE || ~— RAL [| vor (OATAQUT) ms VALID DATA 5 tacs | | teLz tRRH — ViqK™ ri w " ~ XXKXXKXKXKXKY | - noe KX aa | WRITE CYCLE ‘we: >| we — ViHO ‘we # SRKKKKKKKKK || KXXXXXXXXKKKX ‘os ‘DH Vm meus" KXXKRKXRRRRKKH wenn KXXKKXKKKKNEK On | MOTOROLA MCM40100 ¢ MCM40L100

DEVICE INITIALIZATION mum (tc ag) period for the CAS clock. The RAS clock must a . stay inactive for the minimum (tRp) time. The former is for the On power-up an initial pause of 200 microseconds is re- completion of the cycle in progress, and the latter is for the de- quired for the internal substate generator pumpto establish the vice internal circuitry to be precharged for the next active cycle. correct bias voltage. This is to be followed by a minimum of Data out is not latched and is valid as long as the CAS clock > eightactive cycles of the row address strobe (clock) to initialize is active; the output will switch to the three-state mode when the various dynamic nodes internal to the module. During an the CAS clock goes inactive. To perform a read cycle, the write extended inactive state of the device (greater than 4 millisec- (W) input must be held at the Vj level from the time the CAS onds with device powered up), the wake up sequence (8 active clock makes its active transition (t—acg) to the time when ittran- cycles) will be necessary to assure proper device operation. sitions into the inactive (tRc}) mode. ADDRESSING THE RAM WRITE CYCLE The ten address bus pins on the device are time multiplexed Awrite cycle is similar to a read cycle except that the write with two separate 10-bit address fields that are strobed at the (W) clock must go active (Vj,_ level) at or before the CAS clock beginning of the memory cycle by two clocks (active negative) goes active at a minimum tycs time. If the above condition is. called the row address strobe (RAS) and the column address met, then the cycle in progress is referred to as an early write strobe (CAS). A total of twenty address bits will decode one of cycle. In an early write cycle, the write clock and the data in are the 1,048,576 word locations in the device. The column ad- referenced to the active transition of the CAS clock edge. Gress strobe follows the row address strobe by a specified There are two important parameters with respect to the write minimum and maxium time called tcp, which is the row to cycle: the column strobe to write lead time (t¢w) and the row column strobe delay. This time interval is also referred to as the strobe to write lead time (tRw_). These define the minimum multiplex window which gives flexibility to a system designer time that RAS and CAS clocks need to be active after the write to set up the external addresses into the RAM. These condi- operation has started (W clock at Vj, level). tions have to be met for normal read or write cycles. This initial portion of the cycle accomplishes the normal addressing of the device. These are, however, two other variations in addressing PAGE-MODE CYCLES the module, one is called the RAS only refresh cycle (de- Page mode operation allows fast successive data opera- scribed later) where a 9-bit row address field is presented on tions at all 1024 column locations on a selected row. Page ac- the input pins and latched by the RAS clock. The most signifi- cess (tcac) is typically half the regular RAS clock access cant bit on Row Address Ais not required for refresh. The oth- (tRAc) on the Motorola 1M dynamic RAM. Page mode opera- er variation, which is called page mode, allows the user to tion consists of holding the RAS clock active while cycling the column access all words within a selected row. (See PAGE- CAS clock to access the column locations determined by the > MODE CYCLES section.) 10-bit column address field. The page cycle is always initiated with a row address being READ CYCLE provided and latched by the RAS clock, followed by the column address and CAS clock. From the timing illustrated, the initial Areadcycie is referred to as anormal read cycle to differen- cycle is a normal read or write cycle, that has been previously tiate it from a page mode read cycle, which is covered in a later described, followed by the shorter CAS cycles (tpc). The CAS. section. cycle time (tp¢) consists of the CAS clock active time (tcas), The memory read cycle begins with the row addresses valid and CAS clock precharge time (tcp) and two transitions. In and the RAS clock transitioning from Vj to the Vj, level. The practice, any combination of read and write cycles can be per- CAS clock must also make a transition from Vj} to the Vj,_ level formed to suit a particular application. at the specified tacp timing limits when the column addresses are latched. Both the RAS and CAS clocks trigger a sequence REFRESH CYCLES of events which are controlled by several delayed internal clocks. Also, these clocks are linked in such a manner that the The dynamic RAM design is based on capacitor charge access time of the device is independent of the address multi- storage for each bit in the array. This charge will tend to de- plex window. The only stipulation is that the CAS clock must be grade with time and temperature. Therefore, to retain the cor- active before or at the ta¢p maximum specification for an ac- tect information, the module needs to be refreshed at least cess (data valid) from the RAS clock edge to be guaranteed once every 16 milliseconds. This is accomplished by sequen- (trac). Ifthe tap maximum condition is not met, the access tially cycling through the 1024 row address locations every 16 (tac) from the CAS clock active transition will determine read milliseconds (i.e., at least one row every 15.6 microseconds). access time. The external CAS signal is ignored until an inter- Anormal read or write operation to the module will also refresh nal RAS signal is available. This gating feature on the CAS all the words associated with the particular row(s) decoded. clock will allow the external CAS signal to become active as 1 soon as the row address hold time (tay) specification has RAS-Only Refresh | been met and defines the tacp minimum specification. The time difference between tacop minimum and tacp maximum In this refresh method, the system must perform a | can be used to absorb skew delays in switching the address RAS-only cycle on 1024 row addresses every 16 milliseconds. ' bus from the row to column addresses and in generating the The row addresses are latched in with the RAS clock, and the TAS clock. associated internal row locations are refreshed. As the . Once the clocks have become active, they must stay active heading implies, the CAS clock is not required and must be i for the minimum (tag) period for the RAS clock and the mini- inactive or at a Vip level. a MCM40100 « MCM40L100 MOTOROLA

been low (by toga). This activates the intemal refresh counter while the external address input supplies the column address. cycle. If the output buffer was off before the automatic refresh RAS refresh counter test cycle timing diagram. as CAS is held active (hidden refresh). Hidden Refresh 1. Write “0’s into all memory cells (normal write mode). refresh is performed by holding CAS at Vj and taking RAS cycle. Repeat this operation 1024 times. cycle. Repeat this operation 1024 times. The internal refresh counter of the device can be tested with 3. aCAS before RAS refresh counter test. This refresh counter 5. Repeat steps 1 to 4 using complement data. Figure 1. Hidden Refresh Cycle

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ORDERING INFORMATION

(Order by Full Part Number) MCM £40100 or 40L100 x xX Motorola Memory on Le Speed (80 = 80 ns, 10 = 100 ns) Part Number: Package (S = SIMM, SG = Gold Pad SIMM) Full Part Numbers - MCM40100S80 MGM40100SG80 MCM40100S10 — MCM40100SG10 MCM40L100S80 MCM40L100SG80 | MCM40L100S10 MCM40L100SG10 | NOTE: Contact your Motorola representative for further information on the Gold Pad SIMM packages. MCM40100 « MCM40L100 MOTOROLA