MCM36F8 MOTOROLA | Alldatasheet

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MCM36F8 •MCM36F9 MOTOROLA FAST SRAM Advance Information 1MB and 2MB Synchronous Fast Static RAM Module The MCM36F8 (1MB) is configured as 256K x 36 bits and the MCM36F9 (2MB) is configured as 512K x 36 bits. Both are packaged in a 144–pin dual–in–line memory module (DIMM). Each module uses Motorola’s 3.3 V 256K x 18 bit flow– through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals. Synchronous byte write (BWx) and global byte write (WE) allows writes to either individual bytes or to both bytes.

  • Single 3.3 V + 10%, – 5% Power Supply
  • Multiple Clock Pins for Reduced Loading
  • All Inputs and Outputs are LVTTL Compatible
  • Byte Write and Global Write Capability
  • Fast SRAM Access Times: 10 ns
  • Berg Connector, Part Number: 61178–31844
  • 144–Pin DIMM Module This document contains information on a new product. Specifications and information herein are subject to change without notice. Order this document by MCM36F8/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA MCM36F8 MCM36F9 144–LEAD DIMM CASE 1154–01 TOP VIEW 143 2/10/98  Motorola, Inc. 1998

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM 256K x 18 ADSC SBa G ADSP SE1 A0 – A17 A0 – A17 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW VDD BW1 BW0 VSS DQ0 – DQ7 DQ8 – DQ15 DP1 DP0 256K x 18 ADSC SBa G SE1 A0 – A17 ADSP SGW K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ16 – DQ23 DQ24 – DQ31 DP3 DP2 PD1 = GND PD0 = GND BW3 BW2 MCM36F8 BLOCK DIAGRAM WE

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM 256K x 18 ADSC SBa G ADSP SE1 A0 – A17 A0 – A17 ADSP SGW SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW VDD BW1 WE BW0 VSS DQ0 – DQ7 DQ8 – DQ15 DP1 DP0 BW3 BW2 256K x 18 ADSC SBa G SE1 A0 – A17 ADSP SGW SBb ADV LBO DQa0 – DQa7 SE2 DQb0 – DQb7 SE3 DQb8 DQa8 SW VDD VSS 256K x 18 ADSC SBa G SE1 A0 – A17 ADSP K SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW 256K x 18 ADSC SBa G SE1 A0 – A17 ADSP SGW SBb ADV LBO DQb0 – DQb7 SE2 DQa0 – DQa7 SE3 DQa8 DQb8 SW DQ16 – DQ23 DQ24 – DQ31 DP3 DP2 PD1 = NC PD0 = GND MCM36F9 BLOCK DIAGRAM KK0 KK2 SGW K3 K

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM PIN ASSIGNMENT 144–LEAD DIMM TOP VIEW DQ2 DQ4 DQ6 VSS VDD 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 DQ30 DP2 VSS DQ31 DP3 VSS VSS A11 NC NC NC VSS DQ3 DQ5 DQ7 VSS VDD A13 A15 A17 VSS PD1 VSS BW1 VSS VSS DQ1 VDD VDD DQ9 DQ11 VSS DQ13 DQ15 DP1 NC NC VSS ADSP NC VDD NC NC NC VDD NC NC NC VSS BW3 VDD DQ17 DQ19 NC NC NC VSS VSS DQ21 VSS DQ23 DQ25 DQ27 DQ29 VDD VDD DQ8 DQ10 VSS DQ12 DQ14 DP0 NC NC VSS WE NC VDD NC NC NC VDD NC NC NC VSS BW2 VDD DQ16 DQ18 NC NC NC VSS VSS DQ20 VSS DQ22 DQ24 DQ26 DQ28 VDD VSS VDD NC NC VSS A10 NC VDD A12 A14 A16 VSS PD0 VSS BW0 VSS VSS DQ0 VDD

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM PIN DESCRIPTIONS Pin Locations Symbol Type Description 21, 22, 27, 28, 29, 30, 31, 32 A0 – A17 Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times.

82 ADSP Input Synchronous Addresss Status Controller: Initiates read, write, or

chip deselect cycle. 39, 40, 103, 104 BW0 – BW3 Input Synchronous Byte Write Inputs: x refers to the byte being written (byte a, b, c, d). WE overrides BWx. 73, 74, 141, 142 DP0 – DP3 Synchronous Parity Data Inputs/Outputs. (c) 109, 110, 111, 112, 125, 126, 129, 130 (d) 131, 132, 133, 134, 135, 136, 139, 140 DQ0 – DQ31 I/O Synchronous Data Inputs/Outputs. 41, 105 E0, E1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — deselects chip when ADSP is asserted. 42, 106 G0 , G1 Input Asynchronous Output Enable Input. 46, 45, 122, 121 K0 – K3 Input Clock: This signal registers the address, data in, and all control signals except G 35, 36 PD0, PD1 Output Presence Detect Bits.

81 WE Input Synchronous Global Write: This signal writes all bytes

regardless of the status of the BWx signals. If only byte write signals SBx are being used, tie this pin high. 94, 107, 108, 137, 138 VDD Supply Power Supply: 3.3 V + 10%, – 5%. 59, 60, 67, 68, 79, 80, 101, 102, 119, 120, 123, 124, 127, 128, 143, 144 VSS Supply Ground. 96, 97, 98, 99, 100, 113, 114, 115, 116, 117, 118 NC — No Connection: There is no connection to the chip.

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM TRUTH TABLE (See Notes 1 through 4) Next Cycle Address Used Ex ADSP Gx DQx WRITE 2, 4 Deselect None 1 0 X High–Z X Begin Read External 0 0 0 DQ Read Read Current X 1 1 High–Z Read Read Current X 1 0 DQ Read Begin Write External 0 0 X High–Z Write Write Current X 1 X High–Z Write NOTES: 1. X = don’t care, 1 = logic high, 0 = logic low. 2. Write is defined as either any BWx or WE low. 3. Gx is an asynchronous signal and is not sampled by the clock K. Gx drives the bus immediately (tGLQX ) following Gx going low. 4. On write cycles that follow read cycles, Gx must be negated prior to the start of the write cycle to ensure proper write data setup times. Gx must also remain negated at the completion of the write cycle to ensure proper write data hold times. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VDD – 0.5 to + 4.6 V Voltage Relative to VSS Vin, Vout – 0.5 to VDD + 0.5 V Output Current (per I/O) Iout ± 20 mA Temperature Under Bias Tbias – 10 to + 85 °C Storage Temperature Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up.

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit Supply Voltage VDD 3.135 3.3 3.6 V Input High Voltage VIH 2.0 — VDD + 0.5 V Input Low Voltage VIL – 0.5* — 0.8 V *V IL ≥ – 2.0 V for t ≤ tKHKH /2. DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (0 V ≤ Vin ≤ VDD ) Ilkg(I) — ± 1.0 µA Output Leakage Current (0 V ≤ Vin ≤ VDD ) Ilkg(O) — ± 1.0 µA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V POWER SUPPLY CURRENTS Parameter Symbol Min Max Unit Notes AC Supply Current (Device Selected, MCM36F8DG10 All Outputs Open, Cycle Time ≥ tKHKH min) MCM36F9DG10 IDDA — 550 860 mA 1, 2, 3 CMOS Standby Supply Current (Deselected, MCM36F8DG10 Clock (K) Cycle Time ≥ tKHKH , All Inputs Toggling MCM36F9DG10 at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB1 — 310 620 mA Clock Running Supply Current (Deselected, MCM36F8DG10 Clock (K) Cycle Time ≥ tKHKH , All Other Inputs MCM36F9DG10 Held to Static CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) ISB2 — 190 380 mA 4 NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (HSB). 3. Data states are all zero. 4. Device in deselected mode as defined by the Truth Table. MCM36F8 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance BWx , K Other Inputs C in — pF I/O Capacitance C I/O — 13 pF MCM36F9 CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance K Addr, ADSP, WE Other Inputs C in — pF I/O Capacitance C I/O — 21 pF

  1. Write is defined as either any BWx and SW low or WE is low.
  2. Chip Enable is defined as E0 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted.
  3. All read and write cycle timings are referenced from K0 or G0.
  4. G0 is a don’t care after write cycle begins. To prevent bus contention, G0 should be negated prior to start of write cycle.
  5. This parameter is sampled and not 100% tested.
  6. Measured at ± 200 mV from steady state.OUTPUT

the device never provides data later than that time. Figure 1. AC Test Load

MCM36F8 •MCM36F9 MOTOROLA FAST SRAM tKHKLtKHKH A tKLKH tKHQZ tKHQX1 tGLQX B C D E F G K Ax ADSP Ex BW Gx Q(n) Q(A) Q(B) Q(C) D(D) D(E) D(F) Q(G)DQx tGHQZ tGLQV READ/WRITE CYCLES tKHQV tKHQX2 WRITESREADDESELECTED READ MCM 36F X XX XX Motorola Memory Prefix Part Number Full Part Numbers — MCM36F8DG10 MCM36F9DG10 Speed (10 = 10 ns) Package (DG = Gold Pad DIMM) Memory Size (8 = 1MB, 9 = 2MB)

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MCM36F8 •MCM36F9 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 144–LEAD DIMM CASE 1154–01 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ (3.3) 67.75 67.45 CL 4.8 63.6 24.5 4.6 2.5 M0.1 A BC 25.55 25.25 23.2 32.8 2X R MIN3 2X 1.95 1.65 OF MODULE (DATUM C) A APIN 1 PIN 143VIEW B OPTIONAL HOLES M0.1 C BA 32.8 23.2 4.6 2.1 VIEW C PIN 2 PIN 144 (DATUM C) (3.7)2X FULL R 2X MIN2 M0.1 C BA 2X 4.1 3.9 COMPONENT AREA (FRONT) COMPONENT AREA (BACK) MAX3.8 MAX5MIN3.2 1.1 0.9 M0.15 A VIEW A–A B MIN4 MIN4.2 1.6 1.4 C VIEW BMAX0.25 4.1 3.9 (DATUM C)FULL R 0.65 0.55 2.7 2.4 0.8 VIEW C BL0.1 C A L0.5 A NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M, 1994. 2. ALL DIMENSIONS ARE IN mm. 3. CARD THICKNESS APPLIES ACROSS TABS AND INCLUDES PLATING AND/OR METALIZATION. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, P .O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 Motorola Fax Back System – US & C anada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com/mfax / HOME PAGE : http://motorola.com/sps / CUSTOMER FOCUS CENTER: 1-800-521-6274 MCM36F8/D◊