MCM32L512S80

MCM32512 MOTOROLA | Alldatasheet

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~ TECHNICAL DATA Aavance Information MCM32L512 512K x 32 Bit Dynamic Random , Access Memory Module : The MCM32512S is an 16M, dynamic random access memory (DRAM) module | organized as 524,288 x 32 bits. The module is a 72-lead double-sided single-in-line 1@) | memory module (SIMM) consisting of sixteen MCM514256A DRAMs housed in 20/26 i |=] | J-lead small outline packages (SOJ) mounted on a substrate along with a 0.22 uF = (min) decoupling capacitor mounted under each DRAM. The MCM514256A is a 1.0 1 =I CMOS high speed, dynamic random access memory organized as 262,144 four-bit =} words and fabricated with CMOS silicon-gate process technology. =} « Three-State Data Output =I « Early-Write Common I/O Capability = * Fast Page Mode Capability = ¢ TTL-Compatible inputs and Outputs Ss + RAS Only Refresh = | « CAS Before RAS Refresh | « Hidden Retresh 36 | « 512 Cycle Refresh: | MCM32512 = 8 ms (Max) a | MCM32L512 = 64 ms (Max) | « Consists of Sixteen 256K x 4 DRAMs and Sixteen 0.22 F (Min) Decoupling = | Capacitors = | « Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection = * Fast Access Time (trac): = MCM32512S-70 = 70ns (Max) = MCM32512S-80 = 80 ns (Max) = | MCM32512S-10 = 100 ns (Max) = * Low Active Power Dissipation: = MCM32512S-70 = 3.608 W (Max) = MCM32512S-80 = 3.168 W (Max) =F MCM325128-10 = 2.728 W (Max) 2B | « Low Standby Power Dissipation: eo) | TTL Levels = 176 mW (Max) CMOS Levels = 88 mW (Max) 18 mW (Max, MCM32L512) PIN OUT Ci fis [eps | [ols [we [© [ow fs [oo] [ ___twnawes_| [ oa7 | [no | A0-A8S- ue eesee.. Address Inputs | |_2 [ooo] w | m | 2 [oar] a | no | so [oom] «2 | oar | Boog 2.22.1 ara inpurOeaput [+ [oor [ie [om | ve | ar | a [caso] se [oas | s+ [oan | RASO-RASS |... ow Address Strobe sfoor [7 [as | w [vo | a Pease ss [oar] es [oars Wo Be Romerte 8 |_7 [oars [ie [nc [os [ve | [east] ss [oon | 67 | ro | We NO Comeion [ 20 | [ xc | [ 0027 | All power supply and ground pins must be | @ | oas | [oor | se | nc | a [aso] s6 [ooo | os | Poe | Cornected or beeper operation athe device, [_@ [oars [a1 [oa | x [ass | as [asi] 57 [aw] eo | 0 | [10 [Voc | 2 [vas [e+ [ruse] «6 [nc | se [ooze | 70 | Pos | La [xe [a foots [xe fa fw | [veo [ 7 | we | Le [mo [a Joos | a6 [nc | ae | nc | oo [ooze] 72 | vss | This document contains information on a new product. Specifications and information herein are subject to change without notice. a (Sy MOTOROLA @ © MOTOROLA INC., 1990 1 ADITS914

— vot Oo vor — ws [6 oS mS +——| =s ho a a aS ai OE mors vos} oI oe rons a SS ee os ifs —T'"e ES pai 02 oO vo2 — RAS a AAS o tof o] Wee ae ors! a TS a ams po] a oS a or a ae oe UW AQ-AB_VO4 O Os AO-AB OW a | DaQr2-Dar5 | 6 — oS eT 10 oS “* Woz oO voz 4 RAS | | RAS OE 4 ae of ow AO-A8_VO4 on WO4_A0-AB W. an CAS a Daié-pais a oS to _ i us aS -—| as 103 | —o— 10s Se oe Ww AQ-A8__VO4 | 5 | VO4_AQ-AB Ww OF ee Ss oS ioe —o J 02 ors —— vo2 C°_] yo2 RAS as 03 O vos oz Ww AQ-AB_ 04 Ho WO4_A0-AB WH CASS a oS i -3—_ 2 oS P| SAS 2 -—-O-— 02 | oe Ww AO-AB_UO4 O O04 Ao-AB WW | 0028-DQ31 | oS too} 10) oS mS ios —o J tos mS RA vos -—o—} 0 _ oF OF WW Aoas 104 a O04 A0-A8 We x a | A0-/ Veco a. ae U0-U15 0.22 uF (MIN) wm 0S PRESENCE DETECT PIN OUT [ Pinnone | 7ome | cons | i0one_| PDI NC NC NC PD2 Vss Vss Vss PD3 Vss NC Vs PD4 NC Vss Vss MOTOROLA MCM32512 » MCM32L512

ABSOLUTE MAXIMUM RATINGS (See Note) This device contains circuitry to [ating TT symbor [value | unit | protec the inputs against damage Power Supply Voltage due to high static voltages or electric fields; however, it is advised that Voltage Relative to Vgg Vin: Vout —tto+7 v normal precautions be taken to (For Any Pin Except Voc) avoid application of any voltage Data Output Current per DQ Pin [Lo | higher than maximumrated voltages ut Curent er DO | tow | | mA] these nigh mpodone oeuts a Storage Temperature Range NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS [Parameter | Symbor [min [tye [max | unit_| nots | ‘Supply Voltage (Operating Voltage Range) | vec | 45 | 50 | 55 | v RECOMMENDED OPERATING CONDITIONS [eharactoristic TT ymbot [win | Max | unit_| Notes | Voc Power Supply Current lect mA MCM32512-70, tac = 130 ns 656 MCM32512-80, tag = 150 ns. 576 MCM32512-10, tag = 180 ns. 496 Voc Power Supply Current (Standby) (RAS = CAS = Vi) | tcce | — | 2 | m | | Voc Power Supply Current During RAS only Refresh Cycles loca mA MCM32512-70, tag = 130 ns 656 MCM32512-80, tc = 150 ns. 576 MCM32512-10, tao = 180 ns 496 Voc Power Supply Current During Fast Page Mode Cycle loca MCM32512-70, tac = 40 ns 496 MCM32512-80, tac = 45 ns 416 MCM32512-10, tag = 55 ns 336 Voc Power Supply Current (Standby) (RAS = CAS = Veg - 0.2 V)_ MCM32512 locs 16 MCM32L512 32 Voc Power Supply Current During CAS Before RAS Refresh Cycle lece mA 2 MCM32512-70, tac = 130 ns. 656 MCM32512-80, tac = 150 ns. 576 MCM32512-10, tac = 180 ns 496 Output Leakage Current (CAS at Logic 1, Vgg < Vout $ Voc) tigi) | -20 | 2 | wa | | NOTES: 1. All voltages referenced to Vgg. 2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. MCM32512 « MCM32L512 MOTOROLA

CAPACITANCE (f = 1.0 MHz, Ta = 25°C, Vcc = 5 V, Periodically Sampled Rather Than 100% Tested) in apatance O-A8) re ee a int Cepaance re nt apace ASE RS [es [= [| fr [| UO Capacitance (0G0-D031) [ coo | - | a [or | t | NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 At/ AV. AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4) RAS Pulse Width (Fast Page Mode) | tRELREH | tRASP 100,000 | 80 | 100,000 | 100 | 100000 | ns | | (continued) NOTES: 1. Vi min and Vi_ max are reference levels for measuring timing of input signals. Transition times are measured between Viyq and Vit. 2. An initial pause of 200 1s is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. 3. The transition time specification applies for all input signals. in addition to meeting the transition rate specitication, all input signals must transition between Vj} and Vi (or between Vi_ and Vj}) in a monotonic manner. 4. AC measurements ty = 5.0 ns. 5. The specifications for tac (min) and tawc (min) are used only to indicate cycle time at which proper operation over the full temperature range (0°C < Ta < 70°C) is assured 6. Measured with a current load equivalent to 2 TTL (-200 HA, +4 mA) loads and 100 pF with the data output trip points set at Voy = 2.0 V and Voy = 0.8. 7. Assumes that tacp S$ tRcp (max). 8. Assumes that tcp 2 tacp (max). 9. Assumes that tRap 2 tRaD (max). 10. tofF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Operation within the tap (max) limit ensures that tac (max) can be met. tcp (max) is specified as areference point only; it fRcp is greater than the specified tap (max) limit, then access time is controlled exclusively to tcac. 12. Operation within the trap (max) limit ensures that trac (max) can be met. trap (max) is specified as areference point only; if taapis greater than the specified trap (max), then access time is controlled exclusively by ta, MOTOROLA MCM32512 « MCM32L512

READ AND WRITE CYCLES (Continued) [Senora [terse [win [ox | Min [Moe | Min [tox CAS Precharge Time (Page Mode | tcecer | tcp 10 10 Cyle Only) Column Address Hold Time {RELAX tar 55 75 Referenced to RAS. Read Command Hold Time tceHwx | tach 13 Referenced to CAS. Read Command Hold Time tREHWx | 'RRH Referenced to RAS Write Command Hold Time tcewH | twoH Referenced to CAS: Write Command Hold Time treLwH | twor 75 Referenced to RAS. Data in Hold Time Referenced to tRELDX 75 ns RAS Refresh Period mcms2512 | tavav | tarsH 8 8 8 MCM32L512 64 64 64 CAS Setup Time for CAS Before tRELCEL | ‘csr 10 10 RAS Refresh CAS Hold Time for CAS Before RAS | trecen | tcHR 30 30 30 Refresh CAS Precharge Time for CAS tceHceL | topT Before RAS Counter Test [eaSrecmpetine —[eenca | ow [0 | = pw} = es) ~*l—] NOTES: 13. Either taRH oF tay must be satisfied for a read cycle. 14. These parameters are referenced to CAS leading edge in random write cycles. 15. Early write only (twos 2 twos (min)). 16. twcsis nota restrictive operating parameter. Itisincluded in the data sheet as an electrical characteristic only; iftwog>twcg (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not satisifed, the condition of the data out (at access time) is indeterminate. 17. To avoid bus contention and potential damage to the module, RASO and RAST may not be active low simultaneously. Similarly, RAS2 and RAS3 may not be simultaneously active low. MCM32512 « MCM32L512 MOTOROLA

as YHA tRAS' tRE Vi~ SH | : = we Inco ~ ess —t ‘ore [>| Vi Kt + tASR “res 7 ‘ASC tem] feo AH va- wes SCs KOC RE KOO 'RAH’ 'RCH \\ tacos LL 'RRH — Vin- ON RXXXXXXXXY) XXXXX t ibe: ir] oxo | HIGH-Z xX) VALID DATA EARLY WRITE CYCLE ‘RA * ‘ap mas) VIH — s Vi ~ test ae Sa tasc ‘CAH Vu - el bee woes” SO a KO BERK XKRRNNRRRRXRRKKK 'RAH pe tow. | w MAO a pall we ~ VYVYVYVV VY YY YY YYY . LP mT Dq0-0031 ViIH ~ ol WAAYAVAAATAAvAAaaeaay OAAOUT) = XXXXXXXXXAMA vauwoara_KXKXXXKXKXXMAMAA h+— our a MOTOROLA MCM32512 « MCM32L512

. as 'RASP’ [my tre Vi == , fe tRSH 4 cr SP Via _ tore [| ars rm tcas’ | tcas ot om a mea eae, “ + er > H+ foal Vw = A avonesses " XX)E soteeos KOK ASbness KYL ASSneeS KOK SSGRESMKXXXKKX uw - Aas) Ws — YW ~ YYYVVVYVy¥ V7; VY VVVVY . XY KY NY, Wo XXX ) ’ XX . ‘cao | | na Piha ml “md und (DATA OUT) Vou - A\\ DATA ZN DATA JN DATA. tOFF ‘OFF tOFF’ teLz tcLz oz FAST PAGE MODE WRITE CYCLE (EARLY WRITE) tRASP trp m= WO — Vit = | ‘Roo ; << hi tRSH CP iP” ‘CPN LR Rar oS Vit NS NS TARY ayn ay a Ve ~ vooreses "XML sons KOH Sess OOK ASoess KYO Sess KXXXXAXX m0 wor ‘wer ‘woe ag “4” YYyYyvyv Q P 4 VAVAVAVAVAY, wo XOXOXO VX | A EXXXXX Vib | CI ‘oH we Me) “ian” XXXXXXXXE Sek KOO Sk KO oie KXXXXKNX a MCM32512 ¢ MCM32L512 MOTOROLA

(W and A8 are Don’t Care) + tro Ve - as YM Yi ‘cre Rec —_ Viq — AS Vit ~ tASR 'RAH vn — YY ROW VAVAVAVAVAVAVAVAVAVAYAVAVAVAVAVAVAVAVAVAVAYAVAYATAYANA A-AT a XX» t sorrtss KXXXXXXXXKAMAXXAXAKAKAAXXAAN ao-pa31 You - {DATA OUT) —. Sm tic 2 —— i i oom — Yo. - CAS BEFORE RAS REFRESH CYCLE (W and AO to A8 are Don’t Care) tre ‘Ras —<— trp ae (VI RAS “= tapC tcsR ‘CHR k vp - ON oS Vi ~ ‘OFF Da0-0031 You — {DATA OUT) HIGH Vou — a MOTOROLA MCM32512 « MCM32L512

HIDDEN REFRESH CYCLE (READ) tac tras | ~ tras [trp HAS Vin — Vi ~ % r PN Vin > z Mt | tan Pt a ' tRAHT | eracel tCAH 'ASR Vin roomeses KYSER SKOOACRS_ KAKO [ms a) tARH | woY™ XXXXXXXX NXXXXXKXXXXXXXKAXXX Vit tcac , Aw torr _ RAC ORnout a Vou ‘ow : HIDDEN REFRESH CYCLE (WRITE) tre 'RAS Ve - tRAS [tae mg YH VL = t “ Vit 'RAD’ — tar ey "RAL von eye ol Rasy Viq = woes” SM aaRsKOL SHES XXX RRRRKRXRKRRRMN ‘woR-} — V ~ w SRR, XXX RRXRRRKRRKRRK ' on Ds Va - OR | k_smunowta_KXXXXXXXXXXXXXKKKKXX MCM32512 « MCM32L512 MOTOROLA

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE 'RAS tap Vy 'RSH |_| AAS Vit ~ ae VHT oS Vi Ve- voonesses: " XXXXXXXXXXAXAXY)A co. aooness COXXXKXXAKAK al tcac ty READ CYCLE _ vaio RAL or tres — tz 'RRH — VH~ ¢ w \\ SRRRRRRRRIIINY | ed on KOX J TRWL WRITE CYCLE Parl ‘ow. ‘wes >| 'WCH _ Vi ‘we Im OAOACOAOA000000 RI AOCAOACOACOACOACO tos’ ‘or Via - MORAN yy XXXXXXXXXKXXXY)E —woowa —KOXXXXXMXXXX a MOTOROLA MCM32512 MCM32L512

DEVICE INITIALIZATION stay inactive for the minimum (tRp) time. The former is for the a - - completion of the cycle in progress, and the latter is for the de- On power-up an initial pause of 200 microseconds is re- vice internal circuitry to be precharged for the next active cycle. quired for the internal substate generator pump to establish the Data outis not latched and is valid as long as the CAS clock — correct bias voltage. This is to be followed by a minimum of is active; the output will switch to the three-state mode when eight active cycles of the row address strobe (clock) to initialize the CAS clock goes inactive. To perform a read cycle, the write the various dynamic nodes internal to the module. During an (W) input must be held at the Vj} level from the time the CAS. extended inactive state of the module (greater than 4 millisec- clock makes its active transition (tcg) to the time when ittran- onds with device powered up), the wake up sequence (8 active sitions into the inactive (tacH) mode. cycles) will be necessary to assure proper device operation. WRITE CYCLE ADDRESSING THE RAM Awrite cycle is similar to a read cycle except that the write The nine address bus pins on the device are time multi- (W) clock must go active (Vj, level) at or before the CAS clock plexed with two separate 9-bit address fields that are strobed goes active at a minimum twcs time. If the above condition is atthe beginning of the memory cycle by two clocks (active neg- met, then the cycle in progress is referred to as an early write ative) called the row address strobe (RAS) and the column ad- cycle. In an early write cycle, the write clock and the data in are dress strobe (CAS). A total of eighteen address bits will decode referenced to the active transition of the CAS clock edge. one of the 524,288 word locations in the device. The column There are two important parameters with respect to the write address strobe follows the row address strobe by a specified cycle: the column strobe to write lead time (tcyy_) and the row minimum and maxium time called tacop, which is the row to strobe to write lead time (tRyy_)- These define the minimum column strobe delay. This time interval is also referred to as the time that RAS and CAS clocks need to be active after the write multiplex window which gives flexibility to a system designer _ operation has started (W clock at Vj,_ level). to set up the external addresses into the RAM. These condi- tions have to be met for normal read or write cycles. This initial PAGE-MODE CYCLES portion of the cycle accomplishes the normal addressing of the device. These are, however, other variations in addressing the Page mode operation allows fast successive data opera- module: the refresh modes (RAS only refresh, CAS before tions at all 512 column locations on a selected row. Page ac- RAS refresh, hidden refresh), and another mode called page cess (tC Ac) is typically half the regular RAS clock access mode which allows the user to column access all words within (tRAC) on the Motorola 1M dynamic RAM. Page mode opera- a selected row. The refresh mode and page mode operations tion consists of holding the RAS clock active while cycling the are described in more detail in later sections. CAS clock to access the column locations determined by the 10-bit column address field. The page cycle is always initiated with a row address being READ CYCLE provided and latched by the RAS clock, followed by the column Aread cycle is referred to as anormal read cycle to differen- accross and CAS ck from jel hac been previously fate trom apage mode read cycle, which is covered in a later described, followed by the shorter CAS cycles (tpc). The GAS The memory read cycle begins with the row addresses valid cycle time (tpc) consists of the CAS clock active time (tas), and the RAS clock transitioning from Vjjj to the Vj level. The Nd CAS clock precharge time (tcp) and two transitions. In TAS clock must also make atransition from Vi4tothe Vj, level _Practice, any combination of read and write cycles can be per- atthe specified tcp timing limits when the column addresses _—‘f0r"med to suit a particular application. are latched. Both the RAS and CAS clocks trigger a sequence of events which are controlled by several delayed internal REFRESH CYCLES clocks. Also, these clocks are linked in such a manner that the access time of the device is independent of the address multi- The dynamic RAM design is based on capacitor charge plex window. The only stipulation is that the CAS clock must be storage for each bit in the array. This charge will tend to de- active before or at the tac maximum specification for an ac- grade with time and temperature. Therefore, to retain the cor- cess (data valid) from the RAS clock edge to be guaranteed rect information, the module needs to be refreshed at least (tRAC). Ifthe ta¢p maximum condition is not met, the access once every 8 milliseconds. This is accomplished by sequen- (tcac) from the CAS clock active transition will determine read tially cycling through the 512 row address locations every 8 mil- nal RAS signal is available. This gating feature on the CAS normal read or write operation to the module will also refresh clock will allow the external CAS signal to become active as all the words associated with the particular row(s) decoded. soon as the row address hold time (tay) specification has been met and defines the tacp minimum specification. The RAS-Only Refresh time difference between tacp minimum and tacp maximum can be used to absorb skew delays in switching the address In this refresh method, the system must perform a bus from the row to column addresses and in generating the RAS-only cycle on 512 row addresses every 8 milliseconds. CAS clock. The row addresses are latched in with the RAS clock, and the Once the clocks have become active, they must stay active associated internal row locations are refreshed. As the for the minimum (tas) period for the RAS clock and the mini- heading implies, the CAS clock is not required and must be mum (tcag) period for the CAS clock. The RAS clock must _inactive or at a Vij level. MCM32512 « MCM32L512 MOTOROLA

CAS Before RAS Refresh test is performed with read and write operations. During this This refresh cycle is initiated when RAS falls, after CAS has test, the internal refresh counter generates the row address, been low (by tcgp). This activates the internal refresh counter while the external address input supplies the column address. which generates the row address to be refreshed. Externally The entire array is refreshed after 512 test cycles, as indicated applied addresses are ignored during the automatic refresh by the check data written in each row. See CAS before RAS cycle. If the output buffer was off before the automatic refresh refresh counter test cycle timing diagram. cycle, the output will stay in the high impedance state. If the The test can be performed only after a minimum of 8 CAS output was enabled by CAS in the previous cycle, the data out before RAS initialization cycles. The test procedure is as will be maintained during the automatic refresh cycle as long follows: as CAS is held active (hidden refresh). Hidden Refresh 1. Write “0"s into all memory cells (normal write mode). The hidden refresh method allows refresh cycles to be per- 2. Select a column address, and read “0” out of the cell by formed while maintaining valid data at the output pin. Hidden performing CAS before RAS refresh counter test, read refresh is performed by holding CAS at Vj, and taking RAS cycle. Repeat this operation 512 times. high and after a specified precharge period (tp), executing a 3. Select a column address, and write “1” into the cell by CAS before RAS refresh cycle. (See Figure 1.) performing CAS before RAS refresh counter test, write — cycle. Repeat this operation 512 times. CAS BEFORE RAS REFRESH COUNTER TEST 4. Read “1"s (normal read mode), which were written at step The internal refresh counter of the device can be tested with 3. aCAS before RAS refresh counter test. This refresh counter 5. Repeat steps 1 to 4 using complement data. MEMORY __py REFRESH >| REFRESH CYCLE CYCLE CYCLE RAS | Figure 1. Hidden Refresh Cycle eee | MOTOROLA MCM32512 ¢ MCM32L512 i

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ORDERING INFORMATION

(Order by Full Part Number) MCM 32512 or 32L512 _x Xxx Motorola Memory voi] LL Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns) Part Number Package (S = SIMM, SG = Gold Pad SIMM) Full Part Numbers - MCM32512S70 MCM32512SG70 MCM32512S80 MCM32512SG80 MCM32512S810 MCM32512SG10 MCM32L512S70 MCM32L512SG70 MCM32L512S80 MCM32L512SG80 MCM32L512S10 MCM32L512SG10 MCM32512 « MCM32L512 MOTOROLA