MCM32257B MOTOROLA | Alldatasheet

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6–1 MOTOROLA FAST SRAM 256K x 32 Bit Fast Static RAM Module The MCM32257B is an 8M bit static random access memory module orga- nized as 262,144 words of 32 bits. The module is a 64–lead zig–zag in–line pack- age (ZIP) of eight MCM6229 fast static RAMs packaged in 28–lead SOJ packages and mounted on a printed circuit board along with eight decoupling ca- pacitors. The MCM6229 is a high–performance CMOS fast static RAM organized as 262,144 words of 4 bits, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM32257B is equipped with output enable (G) and four separate byte enable (E1 – E4) inputs, allowing for greater system flexibility. The G input, when high, will force the outputs to high impedance. Ex high will do the same for byte x. PD0 and PD1 are reserved for density identification. PD0 and PD1 are con- nected to ground. These pins can be used to identify the density of the memory module.

  • Single 5 V ± 10% Power Supply
  • Fast Access Time: 15/20/25 ns
  • Three–State Outputs
  • Fully TTL Compatible
  • JEDEC Standard Pinout
  • Power Requirement: 960/880/840 mA Maximum, Active AC
  • High Board Density ZIP Package
  • Byte Operation: Four Separate Chip Enables, One for Each Byte (Eight Bits)
  • High Quality Four–Layer FR4 PWB with Separate Internal Power and Ground Planes
  • Incorporates Motorola’s State–of–the–Art Fast Static RAMs For proper operation of the device, VSS must be connected to ground. PIN NAMES Order this document by MCM32257B/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA MCM32257B PD0 2 A15 52 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 W VSS PD1 DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 DQ15 VSS DQ11 DQ24 A10 A12 A14 G DQ25 DQ27 VSS DQ16 DQ17 DQ18 DQ19 A11 A13

43 DQ26

64 LEAD ZIP — CASE 871–01

 Motorola, Inc. 1995

6–2 MOTOROLA FAST SRAM FUNCTIONAL BLOCK DIAGRAM DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 A0 – A17 E W G DQ0 – DQ3 DQ4 – DQ7 DQ8 – DQ11 DQ12 – DQ15 DQ16 – DQ19 DQ20 – DQ23 DQ24 – DQ27 DQ28 – DQ31 W G VCC VSS A0 – A17 PD0 – PD1 256K x 32 MEMORY MODULE

6–3 MOTOROLA FAST SRAM TRUTH TABLE Ex G W Mode VCC Current Output Cycle H X X Not Selected ISB1 or ISB2 High–Z — L H H Read ICCA High–Z — L L H Read ICCA D out Read Cycle L X L Write ICCA D in Write Cycle ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V) Rating Symbol Value Unit Power Supply Voltage VCC – 0.5 to 7.0 V Voltage Relative to VSS Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 30 mA Power Dissipation PD 8.8 W Temperature Under Bias Tbias – 10 to + 85 °C Operating T emperature TA 0 to + 70 °C Storage Temperatrue Tstg – 25 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V) Parameter Symbol Min Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.5 V Input High Voltage VIH 2.2 VCC +0.3* V Input Low Voltage VIL – 0.5** 0.8 V * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns) ** VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns) DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC ) Ilkg(I) — ± 8 µA Output Leakage Current (G, Ex = VIH, Vout = 0 to VCC ) Ilkg(O) — ± 8 µA AC Active Supply Current (G, Ex = VIL, Iout = 0 mA, MCM32257B–15: t AVAV = 15 ns Cycle time ≥ tAVAV min) MCM32257B–20: t AVAV = 20 ns MCM32257B–25: tAVAV = 25 ns ICCA — 960 880 840 mA AC Standby Current (Ex = VIH, Cycle time ≥ tAVAV min) ISB1 — 320 mA CMOS Standby Current (Ex ≥ VCC – 0.2 V, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V) ISB2 — 40 mA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V NOTE: Good decoupling of the local power supply should always be used. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Characteristic Symbol Max Unit Input Capacitance (All pins except DQ0 – DQ31 and E1 – E4) (E1 – E4) C in 48 pF Input/Output Capacitance (DQ0 – DQ31) C out 9 pF The devices on this module contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high imped- ance circuits. These CMOS memory circuits have been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The module is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

6–4 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) READ CYCLE TIMING (See Notes 1 and 2) MCM32257B–15 MCM32257B–20 MCM32257B–25 Parameter Symbol Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 15 — 20 — 25 — ns 3 Address Access Time tAVQV — 15 — 20 — 25 ns Enable Access Time tELQV — 15 — 20 — 25 ns Output Enable Access Time tGLQV — 8 — 9 — 10 ns Output Hold from Address Change tAXQX 5 — 5 — 5 — ns Enable Low to Output Active tELQX 5 — 5 — 5 — ns 4,5,6 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 4,5,6 Enable High to Output High–Z tEHQZ 0 6 0 7 0 8 ns 4,5,6 Output Enable High to Output High–Z tGHQZ 0 6 0 7 0 8 ns 4,5,6 Power Up Time tELICCH 0 — 0 — 0 — ns Power Down Time tEHICCL — 15 — 20 — 25 ns NOTES: 1. W is high for read cycle. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. 3.All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. 6.This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). See Read Cycle 1. AC TEST LOADS Figure 1A Figure 1B The table of timing values shows either a minimum or a maximum limit for each param- eter. Input requirements are specified from the external system point of view. Thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never pro- vides data later than that time. TIMING LIMITS OUTPUT Z0 = 50 Ω R L = 50 Ω VL = 1.5 V 5 pF + 5 V OUTPUT 255 Ω 480 Ω

6–5 MOTOROLA FAST SRAM READ CYCLE 1 (See Note 7 Above) tAVAV tAXQX tAVQV DATA VALIDPREVIOUS DATA VALID A (ADDRESS) Q (DATA OUT) READ CYCLE 2 (See Note) NOTE: Addresses valid prior to or coincident with E going low. tAVAV tELQV tELQX tEHQZ tAVQV tELICCH tEHICCL ISB Q (DATA OUT) A (ADDRESS) Ex (BYTE ENABLE) VCC SUPPLY CURRENT ICC G (OUTPUT ENABLE) tGHQZtGLQX tGLQV DATA VALID

6–6 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM32257B–15 MCM32257B–20 MCM32257B–25 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 15 — 20 — 25 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 15 — 17 — ns Write Pulse Width tWLWH, tWLEH 12 — 15 — 17 — ns Data Valid to End of Write tDVWH 7 — 8 — 10 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 6 0 7 0 8 ns 4,5,6 Write High to Output Active tWHQX 5 — 5 — 5 — ns 4,5,6 Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don‘t care when W is low. 3.All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured ±/n636861720000000000000000500 mV from steady–state voltage with load of Figure 1B. 5.This parameter is sampled and not 100% tested. 6.At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 DATA VALID HIGH–Z HIGH–Z tAVAV tAVWH tWHAX tWHDX tWHQX tWLWH tAVWL tDVWH tWLQZ A (ADDRESS) Ex (BYTE ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT)

6–7 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM32257B–15 MCM32257B–20 MCM32257B–25 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 15 — 20 — 25 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 15 — 17 — ns Enable to End of Write tELEH 10 — 12 — 15 — ns 4,5 Enable to End of Write tELWH 10 — 12 — 15 — ns Write Pulse Width tWLEH 10 — 12 — 15 — ns Data Valid to End of Write tDVEH 7 — 8 — 10 — ns Data Hold Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don’t care when W is low. 3.All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 DATA VALID HIGH–Z tAVAV tAVEH tAVEL tELEH tELWH tEHAX tWLEH tDVEH tEHDX A (ADDRESS) Ex (BYTE ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) Motorola Memory Prefix Part Number

ORDERING INFORMATION

(Order by Full Part Number) MCM 32257B X XX Full Part Numbers — MCM32257BZ15 MCM32257BZ20 MCM32257BZ25 Package (Z = ZIP Module) Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)

6–8 MOTOROLA FAST SRAM PACKAGE DIMENSIONS

64 LEAD

CASE 871–01 PP G 62 PL N S E H J 64 PL D 64 PL -A- -B- -T- K U V LR A A DETAIL B DETAIL C G H DETAIL C SEATING PLANE CARD EDGE DETAIL B F C Y W VIEW A-A T0.25 (0.010) BAM S S T0.25 (0.010) BAM S S MIN MIN MAX MAX INCHES MILLIMETERS DIM A B C D E F G H J K L N P R S U V W X 92.46 0.38 0.89 1.02 0.20 3.05 84.96 0.25 1.14 3.43 92.96 13.97 9.40 0.64 1.40 1.40 0.36 4.06 85.22 1.40 1.40 4.19 2.54 8.76 3.81 3.640 0.015 0.035 0.040 0.008 0.120 3.345 0.010 0.045 0.135 3.660 0.550 0.370 0.025 0.055 0.055 0.014 0.160 3.355 0.055 0.055 0.165 0.100 0.345 0.150

1.27 BSC

2.54 BSC

0.050 BSC

0.100 BSC

39.37 REF

6.35 REF

1.550 REF

0.250 REF

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE X Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. MCM32257B/D /C0042/C0077/C0067/C0077/C0051/C0050/C0050/C0053/C0055/C0066/C0047/C0068/C0042