MCM32100 | DigiCamel IC Datasheet

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—_ vor a0 AS oe woe ar RASO RAS 103 Dae o OW AO-A9_ 04 003 — vOT Das se voe 00s a vos Das OF WOAH a7 TT vot Das 8 woe oo9 RS v03 Dato __ oe UW AQ-AS_O. bar CAST a — vor parz | L & vo pars xe « vo3 para WW Ao-A9 04 pars = 1 _ = vor pars oe a voz vai7 RAS2 we v03 pare OF WAI 04 parg TOT azo OHS voe paat RAS vO3 paz OE WADAD vO re) — voi Da24 OS vo2 pas we vos D026 OF WW ADAD 14 0a27 TS — a vor DQ28 | Be ve ace ew vo3 paso Ww AO-A9_vO4 bast W AO-AS 0.22 pF (MIN) Vig: i te PRESENCE DETECT PIN OUT | Pinan [rome [ome [oom | PDI Vss Vss Vss Po2 Vgs Vss Vgs PDS Vss NC Vss Po4 NC Vss Vss MOTOROLA MCM32100 « MCM32L100

ABSOLUTE MAXIMUM RATINGS (See Note) This device contains circuitry to [Rating | Symbot | vate | unit | protec the inputs against damage a “ “e fields; however, it is advised that Voltage Relative to Vsg Vin» Vout —1to+7 v normal precautions be taken to (For Any Pin Except Voc) avoid application of any voltage put Current [tour | ™ to these high impedence circuits. [Poverdssowion S| |W NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could attect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS fo arameter ymbot Tin | tye [max | unit | notes | Supply Voltage (Operating Voltage Range) [ voc | 45 | 50 | 55 | v 1 [LosicHion vonage. Atinputs Tm fee | [os Tv Tt Logic Low Voltage, Al Inputs [ vm [-10[ = | oe [Tv [+ | RECOMMENDED OPERATING CONDITIONS Voc Power Supply Current lor MCM32100-80, tac = 150 ns 840 MCM32100-10, tac = 180 ns 720 Voc Power Supply Current During RAS only Refresh Cycles locs 2 MCM32100-80, tag = 150 ns 840 MCM32100-10, tac = 180 ns 720 Voc Power Supply Current During Fast Page Mode Cycle loca MCM32100-80, tac = 150 ns 700 MCM32100-10, tac = 180 ns 600 Voc Power Supply Current (Standby) (RAS = CAS = Voc - 0.2 V) MCM32100 locs MCM32L100 Voc Power Supply Current During CAS Before RAS Retresh Cycle loce mA MCM32100-80, tag = 150 ns 840 MCM32100-10, tac = 180 ns 720 Output Leakage Current (CAS at Logic 1, Vgg < Vout S Voc) tugioy) | -10 | 10 | wa | | NOTES: 1. All voltages referenced to Vgs. 2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. MCM32100 » MCM32L100 MOTOROLA

CAPACITANCE (f = 1.0 MHz, Ta = 25°C, Voc = 5 V, Periodically Sampled Rather Than 100% Tested) 10 capac (060-0 ee ee NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 At/AV. AC OPERATING CONDITIONS AND CHARACTERISTICS (Voc = 5.0 V + 10%, Ta = 0 to 70°C, Unless Otherwise Noted) READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4) MCM32100-80 MCM32100-10 RAS Pulse Width (Fast Page Mode) treuneH | rasp | 80 | 100,000 100,000 | ns | | (continued) NOTES: 1. Vin min and Vj, max are reference levels for measuring timing of input signals. Transition times are measured between Vi and Vit. 2. An initial pause of 200 us is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must : transition between Vij and Vj__ (or between Vi and Vj}) in a monotonic manner. 4. AC measurements ty = 5.0 ns. : 5. The specifications for tac (min) and tawe (min) are used only to indicate cycle time at which proper operation over the full temperature range i (0°C < Tp < 70°C) is assured. 6. Measured with a current load equivalent to 2 TTL (-200 WA, + 4 mA) loads and 100 pF with the data output trip points set at Vo} = 2.0 V and | Voi = 08 V. ' 7. Assumes that tacp < tRcp (max). 8. Assumes that tacp 2 tRcp (max) i 9. Assumes that trap 2 tap (max). | 10. tof (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. ! 11, Operationwithin the tacp (max) limit ensures that tac (max) can be met. tcp (max) is specified as a reference point only; itp is greater than the specified tap (max) limit, then access time is controlled exclusively to tcac- 12. Operation within the tap (max) limitensures that tac (max) can be met. trap (max) is specified as a reference point only; if rap is greater than the specified trap (max), then access time is controlled exclusively by tan; MOTOROLA MCM32100 » MCM32L100

READ AND WRITE CYCLES (Continued) suas in Pa > ae ee CAS to RAS Precharge Time tre | s | ~ fo | -~ [wT | CAS Precharge Time Page Mode Cyie On) | tcenoe. | top [| 10 [ — [wo [| — [= [| Row Aderess Setup Time avec | wsa | o [ — [oo [= fs || Flow Adsress Hold Time [trevax | tra [vo | — [os [= [os [| Column Address Setup Tine vor. | so | o | — | o | ~ fos [| Column Adaress Hold Time [ wcevax | toa | ts | — [oo [= [is [| Column Address Hold Time Referenced tRELAX tar 75 to RAS Column Adress 1o RAS Lead Time tavren | trae | | — | % [of [| Read Command Setup Time ween | res | o | — [oo [ — [we [| Read Command Hold Time Referenced tceHwx | trcH to CAS Read Command Hold Time Referenced tREHWX 13 to RAS Write Command Hold Time Referenced tcetwH | ‘WcH to CAS Write Command Hold Time Referenced trewH | twor 75 to RAS Write Command Pulse Width wow | we | [fa [= fs [| Wate Command to RAS Lead Time were | tam [20 [| — [2 | — [os [| Write Command to GAS Lead Time wecen | tom [ 2 | — [2 | — [os [| Data in Setup Time ovo. | twos | o | — [oo [= [irs [ians | Data in Hold Time tceuox | ton | ts | [oa [= [ns [ia | DatainHold Time Reterencecto AS | tpevox | town | 60 | — [7 | — [one [| Refresh Period McM32100 | tavav | tRFSH 16 16 MCM32L100 128 128 Write Commana Setup Tine wee. | wes | o | — | o | — J re [i5i6 | CAS Setup Tine for CAS Before RAS Retesh | taercer | tosn | 1 | — [1 | — [ms [| CAS Hold Time or CAS Betore RASRetesh | trevcen | town | 90 | — [a | — [ns [| TAS Precharge to CAS Active Time tence. | treo [| 0 | — | o | = [os [| CAS Precharge Time tor CAS Before RAS tceHce | tcpT Counter Test GAS Precharge Time Licence. | toen [ to | — [os [= [os [| NOTES: 13. Either tRRH oF tacH must be satistied for a read cycle, 14. These parameters are referenced to CAS leading edge in random write cycles 15. Early write only (twog 2 twos (min)). 16. twesisnotarestrictive operating parameter. Itis includedin the data sheet as an electrical characteristic only; iftwog2twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. Ifthis condition is not satisited, the condition of the data out (at access time) is indeterminate. MCM32100 MCM32L100 MOTOROLA

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(W and AQ are Don’t Care) Va - + tras >| ‘RP ae YH Vi ~ ‘cre trec —. Vi ~ CS Vit ~ ‘sR 'RAH A VAVA SIE AVAVAVAVAVAVAVAVAVAN AV AVN AVY AN AV AV AVAVAVAVANAVAVAVANA AD-AB ‘ - XX) AXXXXXXAKXXAKAXAKAXAKAKAKRAAA Da0-p0s1 You - (DATA OUT) —_—e— HIGH — A A Vou - CAS BEFORE RAS REFRESH CYCLE (W and AO to A9 are Don’t Care) tre _ RA —— trp a (VIM RAS Yi ~ REC ‘csr tcpn’ ‘CHR — VIH — CAS Vi = ‘OFF Da0-Da31 YoH ~ Vo. - MOTOROLA MCM32100 « MCM32L100

HIDDEN REFRESH CYCLE (READ) _ wast 7 ‘ras as MM tor 7 IOPN’ ‘tasH ‘oHR || us VW tRAD” hi = tar Vid ~ rooresses |" XX MarraeesK ON soos KXXXXKXXXXXXXXXXXXAKX [x ol 'RRH |

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TAS BEFORE RAS REFRESH COUNTER TEST CYCLE ‘Ras ‘ke Vy tRSH |_| FAS Vi ~ = VHT OHS . =a asc wn voonesses \\" XXXXXXXXXXXXXXX corm aooressy{ XXXXXXXXXXXXX a READ CYCLE pal ‘RAL ‘RCs — to 'RRH ~ ViKO { * SOO || he or eX ~— 'RWL WRITE CYCLE -—t tow ‘we >| ‘WCH _ VN ‘we Im AOA0A0000.000010 MR OACOOCOCOAOOAOO ‘Ds ‘DH Vim - Mim yy XXXXXXXXXXKXXNE won KKXXXXXXXKKXX a MOTOROLA MCM32100 « MCM32L100

DEVICE INITIALIZATION mum (tas) period for the CAS clock. The RAS clock must . . . stay inactive for the minimum (trp) time. The former is for the On power-up an initial pause of 200 microseconds is re- completion of the cycle in progress, and the latter is for the de- quired for the internal substate generator pump to establish the vice internal circuitry to be precharged for the next active cycle. correct bias voltage. This is to be followed by a minimum of Data out is not latched and is valid as long as the CAS clock eight active cycles of the row address strobe (clock) to initialize is active; the output will switch to the three-state mode when the various dynamic nodes internal to the module. During an the CAS clock goes inactive. To perform a read cycle, the write extended inactive State of the device (greater than 4 millisec- (W) input must be held at the Vix level from the time the CAS onds with device powered up), the wake up sequence (8 active clock makes its active transition (tcg) to the time when it tran- cycles) will be necessary to assure proper device operation. sitions into the inactive (tao}y) mode. ADDRESSING THE RAM WRITE CYCLE The ten address bus pins on the device are time multiplexed Awrite cycle is similar to a read cycle except that the write with two separate 10-bit address fields that are strobed at the (W) clock must go active (Vj level) at or before the CAS clock beginning of the memory cycle by two clocks (active negative) goes active at a minimum twcs time. If the above condition is called the row address strobe (RAS) and the column address met, then the cycle in progress is referred to as an early write strobe (CAS). A total of twenty address bits will decode one of cycle. In an early write cycle, the write clock and the datain are the 1,048,576 word locations in the device. The column ad- referenced to the active transition of the CAS clock edge. dress strobe follows the row address strobe by a specified There are two important parameters with respect to the write minimum and maxium time called tcp, which is the row to cycle: the column strobe to write lead time (tw) and the row column strobe delay. This time interval is also referred to as the strobe to write lead time (tay). These define the minimum multiplex window which gives flexibility to a system designer time that RAS and CAS clocks need to be active after the write to set up the external addresses into the RAM. These condi- operation has started (W clock at Vj level). tions have to be met for normal read or write cycles. This initial portion of the cycle accomplishes the normal addressing of the device. These are, however, two other variations in addressing PAGE-MODE CYCLES the module, one is called the RAS only refresh cycle (de- Page mode operation allows fast successive data opera- scribed later) where a 9-bit row address field is presented on tions at all 1024 column locations on a selected row. Page ac- the input pins and latched by the RAS clock. The most signifi- cess (tcc) is typically half the regular RAS clock access cant bit on Row Address AQ is not required for refresh. The oth- (tRAC) on the Motorola 1M dynamic RAM. Page mode opera- er variation, which is called page mode, allows the user to tion consists of holding the RAS clock active while cycling the column access all words within a selected row. (See PAGE- CAS clock to access the column locations determined by the MODE CYCLES section.) 10-bit column address field. The page cycle is always initiated with a row address being READ CYCLE provided and latched by the RAS clock, followed by the column: address and CAS clock. From the timing illustrated, the initial Aread cycle is referred to as a normal read cycle to differen- cycle is a normal read or write cycle, that has been previously tiate it from a page mode read cycle, which is covered in a later described, followed by the shorter CAS cycles (tpg). The CAS section. cycle time (tpc) consists of the CAS clock active time (tos), The memory read cycle begins with the row addresses valid and CAS clock precharge time (tcp) and two transitions. In and the RAS clock transitioning from Vj}; to the Vj__ level. The practice, any combination of read and write cycles can be per- CAS clock must also make a transition from Vj} to the Vj, level formed to suit a particular application. atthe specified tap timing limits when the column addresses are latched. Both the RAS and CAS clocks trigger a sequence REFRESH CYCLES of events which are controlled by several delayed internal clocks. Also, these clocks are linked in such a manner that the The dynamic RAM design is based on capacitor charge access time of the device is independent of the address multi- storage for each bit in the array. This charge will tend to de- plex window. The only stipulation is that the CAS clock must be grade with time and temperature. Therefore, to retain the cor- active before or at the tacp maximum specification for an ac- rect information, the module needs to be refreshed at least cess (data valid) from the RAS clock edge to be guaranteed once every 16 milliseconds. This is accomplished by sequen- (trac). Ifthe tagp maximum condition is not met, the access tially cycling through the 1024 row address locations every 16 (tcc) from the CAS clock active transition will determine read milliseconds (i.e., at least one row every 15.6 microseconds). access time. The external CAS signal is ignored until an inter- Anormal read or write operation to the module will also refresh nal RAS signal is available. This gating feature on the CAS all the words associated with the particular row(s) decoded. clock will allow the external CAS signal to become active as soon as the row address hold time (tRAH) specification has RAS-Only Refresh been met and defines the tacp minimum specification. The time difference between tacp minimum and tacp maximum In this refresh method, the system must perform a can be used to absorb skew delays in switching the address RAS-only cycle on 1024 row addresses every 16 milliseconds. bus from the row to column addresses and in generating the The row addresses are latched in with the RAS clock, and the CAS clock. associated internal row locations are refreshed. As the ‘Once the clocks have become active, they must stay active heading implies, the CAS clock is not required and must be for the minimum (tgs) period for the RAS clock and the mini- inactive or at a Vj} level. a MCM32100 « MCM32L100 MOTOROLA

been low (by t¢gp). This activates the internal refresh counter __While the external address input supplies the column address. cycle. if the output butter was off before the automatic refresh RAS refresh counter test cycle timing diagram. as CAS is held active (hidden refresh). refresh is performed by holding CAS at Vj, and taking RAS cycle. Repeat this operation 1024 times. RAS cycle. Repeat this operation 1024 times. The internal refresh counter of the device can be tested with 3. aCAS before RAS refresh counter test. This refresh counter 5. Repeat steps 1 to 4 using complement data. Figure 1. Hidden Refresh Cycle

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ORDERING INFORMATION

(Order by Full Part Number) MCM £32100 or 32L100 _x xX Motorola Memory on ie LL Speed (80 = 80 ns, 10 = 100 ns) Part Number. Package (S = SIMM, SG = Gold Pad SIMM) Full Part Numbers— MCM32100S80 MCM32100SG80 MCM32100S10 — MCM32100SG10 MCM32L100S80 -MCM32L100SG80 MCM32L100S10 - MCM32L100SG10 NOTE: Contact your Motorola representative for further information on the Gold Pad SIMM packages. MCM32100 « MCM32L100 MOTOROLA

Product Information

MCM32100 specifications and overview.

Summary

1M x 32 Bit Dynamic Random Access Memory Module

Description

1M x 32 Bit Dynamic Random Access Memory Module

Source title MCM32100 Datasheet(PDF) - Motorola, Inc

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