MCM28F256ACH

MCM28F256ACH TI1 | Alldatasheet

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MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers Literature Number: SNOS764A

MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers PRELIMINARY July 1995 MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers General Description The MCM28F256ACH is a 268,435,456-bit flash memory module, organized as 16 pages with 16,777,216 bytes (8,388,608 words) per page. Utilizing Intel’s FlashFile TM Memory and National’s SCAN TM I/O buffers, the MCM28F256ACH offers several revolutionary features, in- cluding a user-configurable x8/x16 architecture, selective block locking, on-board write buffers, pipelined command execution and boundary scan test capability. Several power reduction features are also incorporated, including Automat- ic Power Savings (APS), which puts the module into a low current state when it is being accessed by a slowed or stopped CPU. The MCM28F256ACH includes sixteen 28F016SA flash memories, decoding logic and IEEE 1149.1 compliant I/O buffers. The module is offered in a 68-lead, hermetic pack- age. Both through-hole and surface mount lead configura- tions are available.

Features

Y Read access time of 140 ns over the industrial temper- ature range (160 ns over the military temperature range) Y Utilizes Intel’s FlashFile architecture with 512 indepen- dently lockable blocks (16 pages with 32 blocks per page) Y Choice of x8 or x16 architecture (user-configurable) Y Pipelined command execution Y Automated write and erase capability can be executed simultaneously in all 16 pages, greatly improving aver- age write/erase cycle times Y National’s lEEE 1149.1 compliant SCAN I/O buffers simplify the integration of design and test Y TTL compatible inputs Y Low noise, TRl-STATE É outputs drive 50 X transmission line to TTL levels (75 X transmission line over military temperature range) Y Hermetically sealed, integral substrate package Y DIP and surface mount packaging available Connection Diagram TL/Z/12436–1 Pin DescriptionNames A0 Byte-Select Address Input A1 –A24 Word-Select Address Inputs DQ0 –DQ7 Low-Byte Data I/O Bus DQ8 –DQ15 High-Byte Data I/O Bus CE Chip Enable Input (Active LOW) RP Reset/Power-Down Input (Active LOW) OE Output Enable Input (Active LOW) WE Write Enable Input (Active LOW) RY/BY Ready/Busy Output WP Write Protect Input (Active LOW) BYTE Byte Enable Input (Active LOW) VPP Erase/Write Power Supply VCC Device Power Supply GND Ground NC No Connection TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. SCANTM is a trademark of National Semiconductor Corporation. FlashFileTM is a trademark of Intel Corporation C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A. Obsolete

TL/Z/12436–2 Functional Description The MCM28F256ACH is a 268,435,456-bit (256-Mbit) flash memory module, organized as 16 pages with 16,777,216 bytes (8,388,608 words) per page. The module is segment- ed into 512 independently lockable blocks (32 blocks per page). A Command User Interface (CUI) serves as the interface between the system controller and each page of internal memory. Automation of the byte/word write and block erase functions allow these commands to be executed using a two-write command sequence to the CUI. An internal Write State Machine (WSM) automatically executes the algo- rithms, timings and verifications necessary for the write and erase operations, thereby relieving the system controller of these tasks. Each page of memory has three types of status registers and a RY/BY output to provide information on the progress of the requested operation. The Compatible Status Register (CSR) is 100% compatible with status register used in previ- ous FlashFile memory devices. The Global Status Register (GSR) informs the system of command queue status, sector buffer status and WSM status. Block Status Registers (BSR) provide block-specific status information such as the block lock bit status. A choice of four different RY/BY configura- tions can be selected via special CUI commands: level- mode (default), pulse-on-write, pulse-on-erase, or disabled. Obsolete

Functional Description (Continued) Memory data is written in byte/word increments typically within 6 ms. Each page of memory incorporates two sector buffers of 256 bytes (128-words) which allow sector data writes at SRAM speeds. Writes from sector buffers to the flash array can be initiated with a single command and will complete independently, freeing the system controller for other tasks. Any one of the 512 blocks can be erased typically within 0.6 seconds, without affecting the contents of the remaining blocks. Write and erase operations can be executed simul- taneously in all 16 pages, greatly improving average write/ erase cycle times. A write protection scheme has been incorporated that pro- vides maximum flexibility for selecting which blocks can be modified by the end user. A non-volatile lock bit is assigned to each block, and is used in conjunction with the master write protect input (WP ). With WP at logic low, block locking capability is invoked and the WSM is notified if a requested write or erase operation is not allowed. With WP at logic high, the status of all lock bits is overridden, allowing write or erase operations in any block. The MCM28F256ACH reduces system overhead by allow- ing a subset of commands to be pipelined to the CUI on each page of memory. Ordinarily the command queue is 3- commands deep. However, if only single block erase com- mands are queued, the queue becomes virtually 32-com- mands deep. Commands in the queue are prioritized. In order to capture data as it arrives in real time, write commands are executed before erase commands regardless of the command order. Also, multiple erase commands are queued in conjunction with write commands. If the CUI receives a write command affecting a block which is in queue to be erased, it will priori- tize that block erase command ahead of other erase opera- tions, allowing the complete block modification to occur as quickly as possible. The BYTE input allows either x8 or x16 read/writes to the MCM28F256ACH. With BYTE at logic low the device oper- ates in the 8-bit mode. Address A 0 selects either the low or high byte, and the high-byte data bus (DQ 8 –DQ15) floats to TRI-STATE. With BYTE at logic high the device is in the 16- bit mode of operation. In this case A 1 becomes the lowest order address, A 0 is not used (don’t care) and data is input and output on all 16 bits of the data bus (DQ 0 –DQ15). The MCM28F256ACH offers several low power modes of operation. Standby mode is entered when the module is deselected (CE at logic high). The typical I CC current draw in this mode is 20 mA. If a WSM is processing a command when the module is deselected, the operation continues and power consumption remains at the non-standby level until the command has completed. With RP at logic low, enters deep power-down mode. The typical I CC current draw in this mode is 4 mA. Bringing RP low interrupts any current or pending commands and resets all status registers, CUI and WSM. The contents of any memory location being written or block being erased will no longer be valid. The Sleep command puts a page of memory in sleep mode, which reduces the power consumption for that page of memory to deep power-down levels. The sleep command allows any current or pending commands to execute before going into sleep mode. Automatic Power Savings (APS) is a feature which puts the module into a low current state when it is being accessed by a slowed or stopped CPU. After data is read from the mem- ory array, power reduction control circuitry reduces the typi- cal I CC current draw to 20 mA until a new memory location is accessed. To get the lowest possible power consumption in all modes, input pins should be held at V CC or GND (CMOS levels), rather than V IH or V IL (TTL levels). For detailed information regarding the operation of the 28F016SA FlashFile Memory, refer to the Intel data sheet (order number 290489) and user’s manual (order number 297372). Obsolete

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Device Power Supply Voltage (V CC) b0.2V to a7.0V Erase/Write Power Supply Voltage (V PP) b0.2V to a14.0V DC Input Diode Current (I IK) VIN eb 0.5V b20 mA VIN e VCC a 0.5V a20 mA DC Output Diode Current (I OK) VOUT eb 0.5V b20 mA VOUT e VCC a0.5V a20 mA DC Output Voltage (V OUT) b0.5V to V CC a 0.5V DC Output Source/Sink Current (I OUT) g70 mA DC V CC or Ground Current Per Output Pin (I CC or I GND) g70 mA Thermal Resistance, Junction to Case ( iJC)5 §C/W Junction Temperature (T J) a150§C Storage Temperature (T STG) b65§Ct o a150§C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recom- mend operation of this module outside the datasheet specifications. Recommended Operating Conditions Device Power Supply Voltage (V CC) 4.5V to 5.5V Erase/Write Power Supply Voltage (V PP) (Note 2) Read-Only Operations (V PPL) 0.0V to 6.5V Erase/Write Operations (V PPH) 11.4V to 12.6V Input Voltage (V IN) 0 Vt oV CC Output Voltage (V OUT) 0 Vt oV CC Case Operating Temperature (T C) Industrial b45§Ct o a85§C Military b55§Ct o a125§C Minimum Input Edge Rate (dV/dt) 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Maximum Static Output Current High Level (I OH) b32 mA Low Level (I OL) a64 mA Note 2: Erase and write operations are inhibited when V PP e VPPL and not guaranteed In the range betveeen V PPL and V PPH. Military Industrial Symbol Parameter Conditions T C eb 55§Ct o a125§CT C eb 45§Ct o a85§C Units VCC e 4.5V to 5.5V V CC e 4.5V to 5.5V VIH Minimum High Input Voltage 2.0 2.0 V VIL Maximum Low Input Voltage 0.8 0.8 V IIH Maximum High Input Current V IN e VCC 1.0 1.0 mAAll inputs except TCK, TDI, TMS VIN e VCC 15.0 15.0 mATCK, TDI, TMS Inputs IIL Maximum Low Input Current V IN e GND b1.0 b1.0 mAAll inputs except TCK, TDI, TMS VIN e GND b1.2 b1.2 mATCK, TDI, TMS Inputs IOZT Maximum I/O Leakage Current V I/O e VCC or GND g15.0 g10.0 mA VOH Minimum High Output Voltage I OUTeb 50 mAV CC b 1.35 VCC b 1.35 IOUT eb 32 mA 2.4 V IOUT eb 24 mA 2.4 VOL Maximum Low Output Voltage I OUT e 50 mA 0.1 0.1 IOUT e 64 mA 0.55 V IOUT e 48 mA 0.55 IOLD Minimum Dynamic VOLD e 0.8 V Max 63 94 mA IOHD Output Current ² VOHD e 2.0 V Min b27 b40 IOS Minimum Output Short V OUT e 0V b100 b100 mACircuit Current ² ICCT Maximum V CC Current V IN e VCC b 2.1V 2.0 2.0 mAper Input at TTL HIGH All inputs except TCK,TDI, TMS ICCS Maximum V CC Standby CE e RP e VCC 25 25 mACurrent ²Maximum test duration 2.0 ms, one output loaded at a time. Obsolete

Symbol Parameter Conditions Military Industrial UnitsTC eb 55§CT C eb 45§C to a125§Ct o a85§C VCC e 4.5V to 5.5V V CC e 4.5V to 5.5V ICCD Maximum V CC Deep RP e GND, 55 m APower Down Current TDI e TMS e VCC ICCR Maximum V CC Read Current f e 5 MHz I OUT e 0 mA 120 120 mA ICCW Maximum V CC Write Current Single Write Operation 70 70 mA

16 Simultaneous Write 650 650 mAOperations

ICCE Maximum V CC Block Single Erase Operation 60 60 mAErase Current 16 Simultaneous Erase Operations 480 480 ICCES Maximum V CC Erase Single Erase Operation Suspended 45 45 mASuspend Current 16 Erase Operations 220 220Simultaneously Suspended IPPS Maximum V PP Standby Current V PP t VCC 11 m A IPPD Maximum V PP Deep RP e GND 11 m APower Down Current IPPR Maximum V PP Read Current V PP e VPPH 55 m A IPPW Maximum V PP Byte Single Write Operation 18 18 mAWrite Current 16 Simultaneous Write Operations 290 290 IPPE Maximum V PP Block Single Erase Operation 15 15 mAErase Current 16 Simultaneous Erase Operations 240 240 IPPES Maximum V PP Erase 1–16 Erase Operations 55 m ASuspend Current Suspended ²Maximum test duration 2.0 ms, one output loaded at a time. Military Industrial Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tAVAV Read Cycle Time (No Page Change) 160 140 ns Read Cycle Time (With Page Change) 180 160 tAVEL Address Setup to CE Going Low 20 15 ns tAVGL Address Setup to OE Going Low 0 0 ns tAVQV Address A 0 –A20 to Output Delay 160 140 ns Address A 21 –A24 to Output Delay 180 160 tELQV CE to Output Delay 200 180 ns tPHQV RP to Output Delay 800 700 ns tGLQV OE to Output Delay 80 70 ns tELQX CE to Output Low Z 0 0 ns tEHQZ CE to Output High Z 50 40 ns tGLQX OE to Output Low Z 0 0 ns tGHQZ OE to Output High Z 70 60 ns Obsolete

Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tOH Output Hold from Address CE or RE 00 n sChange, Whichever Occurs First tFLQV BYTE to Output Delay 160 140 nstFHQV tFLQZ BYTE Low to Output High Z 35 30 ns tELFL CE Low to BYTE 00 nstELFH Low or High Military Industrial Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tAVAV Write Cycle Time 160 140 ns tVPWH VPP Setup to WE Going High 300 250 ns tPHEL RP Setup to CE Going Low 700 600 ns tELWL CE Setup to WE Going Low 40 35 ns tAVWL Address A 20 –A24 Setup to 20 15 nsWE Going Low ² tAVWH Address A 0 –A20 Setup to 70 60 nsWE Going High tDVWH Data Setup to WE Going High 70 60 ns tWLWH WE Pulse Width Low 70 60 ns tWHDX Data Hold from WE High 10 5 ns tWHAX Address Hold from WE High 20 15 ns tWHEH CE Hold from WE High 20 15 ns tWHWL WE Pulse Width High 70 60 ns tGHWL Read Recovery before Write 0 0 ns tWHRL WE High to RY/BY Going Low 150 130 ns tRHPL RP Hold from Valid Status Register 00 n s(CSR, GSR, BSR) Data and RY/BY High tPHWL RP High Recovery to WE Going Low 1.5 1.25 ms tWHGL Write Recovery before Read 110 100 ns tQVVL VPP Hold from Valid Status Register (CSR, 00 msGSR, BSR) Data and RY/BY High tWHQV1 Duration of Word/Byte Write Operation 3.0 3.6 ms(Measured to Valid Status Register Data) tWHQV2 Duration of Block Erase Operation 0.2 0.24 ms(Measured to Valid Status Register Data) ²Address lines A 20 –A24 must be valid during the entire WE Low pulse. Obsolete

Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tAVAV Write Cycle Time 160 140 ns tVPEH VPP Setup to CE Going High 300 250 ns tPHWL RP Setup to WE Going Low 700 600 ns tWLEL WE Setup to CE Going Low 0 0 ns tAVEL Address A 20 –A24 Setup to CE Going Low ² 00 n s tAVEH Address A 0 –A20 Setup to CE Going High 55 45 ns tDVEH Data Setup to CE Going High 55 45 ns tELEH CE Pulse Width Low 70 60 ns tEHDX Data Hold from CE High 40 35 ns tEHAX Address Hold from CE High 55 45 ns tENWH WE Hold from CE High 55 45 ns tEHEL CE Pulse Width High 70 60 ns tGHEL Read Recovery before Write 0 0 ns tEHRL CE High to RY/BY Going Low 190 165 ns tRHPL RP Hold from Valid Status Register 00 n s(CSR, GSR, BSR) Data and RY/BY High tPHEL RP High Recovery to CE Going Low 1.5 1.25 ms tEHGL Write Recovery before Read 110 100 ns tQVVL VPP Hold from Valid Status Register 00 ms(CSR, GSR, BSR) Data and RY/BY High tEHQV1 Duration of Word/Byte Write Operation 3.0 3.6 ms(Measured to Valid Status Register Data) tEHQV2 Duration of Block Erase Operation 0.2 0.24 s(Measured to Valid Status Register Data) ²Address lines A 20 –A24 must be valid during the entire WE Low pulse. Military Industrial Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tAVAV Write Cycle Time 160 140 ns tELWL CE Setup to WE Going Low 40 35 ns tAVWL Address Setup to WE Going Low ² 20 15 ns tDVWH Data Setup to WE Going High 70 60 ns tWLWH WE Pulse Width Low 70 60 ns tWHDX Data Hold from WE High 10 5 ns tWHAX Address Hold from WE High 20 15 ns tWHEH CE Hold from WE High 20 15 ns tWHWL WE Pulse Width High 70 60 ns tGHWL Read Recovery before Write 0 0 ns tWHGL Write Recovery before Read 110 100 ns ²Address must be valid during the entire WE Low pulse. Obsolete

Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Min Max Min Max tAVAV Write Cycle Time 160 140 ns tWLEL WE Setup to CE Going Low 0 0 ns tAVEL Address Setup to CE Going Low ² 00 n s tDVEH Data Setup to CE Going High 55 45 ns tELEH CE Pulse Width Low 70 60 ns tEHDX Data Hold from CE High 40 35 ns tEHAX Address Hold from CE High 55 45 ns tEHWH WE Hold from CE High 55 45 ns tEHEL CE Pulse Width High 70 60 ns tGHEL Read Recovery before Write 0 0 ns tEHGL Write Recovery before Read 110 100 ns ²Address must be valid during the entire CE Low pulse. Military Industrial Symbol Parameter TC eb 55§Ct o a125§CT C eb 45§Ct o a85§C UnitsVCC e 4.5V to 5.5V VCC e 4.5V to 5.5V Typ² Max Typ² Max tWHRH1 Word/Byte Write Time 6 6 ms tWHRH2 Block Write Time (Byte Write Mode) 0.4 3.0 0.4 2.5 s tWHRH3 Block Write Time (Word Write Mode) 0.2 1.4 0.2 1.2 s Block Erase Time 0.6 1.4 0.6 12 s Full Page Erase Time 19.2 19.2 s ²25§C, V PP e 12.0V, V CC e 5.0V. Obsolete

Symbol Parameter Typ Units Conditions CIN Input Pin Capacitance 10 pF VCC e 5.0V CI/O Input/Output Pin Capacitance 25 pF VCC e 5.0 AC Testing Load Circuit TL/Z/12436–3 AC Reference Waveforms TL/Z/12436–4 Input rise and fall times (10%–90%) e 3n s Obsolete

Physical Dimensions (inches) 68-Lead, Hermetic, Dual-In-Line, Custom, ISPMCM-DC Package Obsolete

MCM28F256ACH 256-Mbit (32-Mbit x 8, 16-Mbit x 16) Flash Memory Module with Internal Decoding and Boundary Scan I/O Buffers Physical Dimensions (inches) (Continued) 68-Lead, Hermetic, Surface Mount, Custom, ISPMCM-DC Package LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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