MCM20014 MOTOROLA | Alldatasheet
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MOTOROLA, INC. 2000 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1/3” Color VGA Digital Image Sensor 640 x 480 pixel progressive/interlace scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control, timing, and pixel correction
features
Features:
- VGA resolution, active CMOS image sensor with square pixel unit cells 7 . 8 µm pitch pixels with patented pinned photodiode architecture Bayer-RGB color filter array with optional micro lenses High sensitivity, quantum efficiency, and charge conversion efficiency Low fixed pattern noise / Wide dynamic range Antiblooming and continuous variable speed shutter Single master clock operation Digitally programmable via I 2C interface Integrated on-chip timing/logic circuitry CDS sample and hold for suppression of low frequency and correlated reset noise 48X programmable variable gain to optimize dynamic range and facilitate white balance and iris adjustment 10-bit, pipelined algorithmic RSD ADC User selectable digital output formats: 8-bit companded data 10-bit linear data Column offset correction, and Bad Pixel Replacement for noise suppression Pixel addressability to support ‘Window of Interest’ windowing, resolution, and subsampling 30fps full VGA at 10Mhz Master Clock Rate Single 3.3V power supply 48 pin CLCC package The MCM20014 is a fully integrated, high performance CMOS image sensor with features such as integrated timing control, and analog signal processing for digital imaging applications. The part provides designers a complete im- aging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”. Sys- tem benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automo- tive among others. The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola’s sub-micron ImageMOS TM technology. The frame rate is completely adjustable from 0 to 30 frames per second without adjusting the system clock from 10Mhz. Each pixel on the sensor is individually addressable allowing the user to control “Window of Interest” (WOI) panning and zooming, sub-sampling, resolution, exposure, gain, and other image processing features via a two pin I 2C interface. Programmable digital signal processing blocks included in the data path are bad-pixel replacement and noise compensation for image enhancement. The sensor is run by supplying a single Master Clock. The sensor output is 8 or 10 digital bits depending on output mode selected. MCM20014IBMN 48 CLCC-IB Order this document by MCM20014/D
Ordering Information
This document contains information on a new product. Specifications and information herein are subject to change without notice. November 2000 MCM20014IBB 48 CLCC-IB Monochrome Color ImageMOSImageMOS
Figure 1. MCM20014 Simplified Block Diagram
10 Bit
Figure 2. MCM20014 Detailed Block Diagram
1.0 MCM20014 Overview
The MCM20014 is a solid state CMOS Active CMOS Imager (ACITM) that integrates the functionality of a complete analog image acquistion, digitizer, and digital signal processing system on a single chip. The image sensor comprises a 1/3” format pixel array with 640x480 (VGA) active elements. The image size is fully program- mable to user defined windows of interest. The pixels are on a 7.8µm pitch. High sensitivity and low noise are a characteristic of the pinned photodiode architecture utilized in the pixels. Optional microlenses are available to further enhance the sensitivity. The sensor is avail- able with Bayer patterned Color Filter Arrays (CFAs) for color output or as a monochrome imager. Integrated timing and programming controls allow video (CFCM) or still (SFCM) image capture mode supporting progressive or interlace scan modes. Frame rates are programmable while keeping Master Clock frequency constant. User programmable row and column start/ stop allow windowing to a minimum 1x1 pixel window. Windowing can also be performed by subsampling in multiple pixel increments to allow digital zoom. A high performance analog signal processing chain helps establish a new benchmark for digital image cap- ture. The sensor has an unprecedented level of integra- tion. The analog video output of the pixel array is processed by an on chip processing pipeline. Correlat- ed Double Sampling (CDS) eliminates low frequency correlated noise. The Frame Rate Clamp (FRC) en- ables real time optical black level calibration and offset correction. Digitally Programmable Amplifiers (DPGAs) allow real time color gain correction for Auto White Bal- ance (AWB) as well as global gain adjustment; offset calibration can be done on a per column basis or global- ly. This per-column offset correction can be applied au- tomatically or by using stored values in the on chip SRAM. A 10-bit Redundant Signed Digit (RSD) ADC converts the analog data to a 10-bit digital word stream. The fully differential analog signal processing pipeline serves to improve noise immunity, signal to noise ratio, and system dynamic range. A digital signal post processing block includes program- mable features for output data companding and pixel correction. User programmable thresholding allows re- placement of pixels beyond preset maximum and mini- mum levels by average, trailing, or leading pixels. A noise core allows companding of data that allows users to accentuate dark pixels. Data companding can be done by loading any one of eight hard coded compres- sion curves which performs a 10 to 8 bit transformation on the data. The sensor uses an industry standard two line I 2C serial interface. It operates with a single 3.3V power supply with no additional biases and requires only a single Master Clock for operation upto 13.5MHz. It is housed in a 48 pin ceramic LCC package. The MCM20014 is designed taking into consideration interfacing requirements to standard video encoders. In addition to the 10 bit bayer encoded data stream, the sensor outputs the valid frame, line and pixel sync sig- nals needed for encoding. The sensor interfaces with a variety of commercially available video image proces- sors to allow encoding into various standard video for- mats . The MCM20014 is an elegant and extremely flexible single chip solution that simplifies a system designer’s tasks of image sensing, processing, digital conversion, and digital signal processing to a high performance, low cost, low power IC. One that supports among others a wide range of low power, portable consumer digital im- aging applications.
2.0 MCM20014 Theory of Operation
This section reviews the concepts behind the operation of the image sensing and capture mechanisms em- ployed in the MCM20014.
2.1 Sensor Interface
2.1.1 Pixel Architecture
TM (1) sensor comprises a 640x480 active pixel array and supports both progres- sive and interlaced scan readout modes. The basic op- eration of the pixel relies on the photoelectric effect where due to its physical properties silicon is able to de- tect photons of light. The photons generate electron- hole pairs in direct proportion to the intensity and wave- length of the incident illumination. The application of an appropriate bias allows the user to collect the electrons and meter the charge in the form of a useful parameter such as voltage. The pixel architecture is based on a four transistor (4T) Advanced CMOS Imager TM(2) pixel which requires all pixels in a row to have common Reset, Transfer, and Row Select controls. In addition all pixels have common supply (V DD) and ground (VSS) connections. An opti- mized cell architecture provides enhancements such as noise reduction, fill factor maximizations, and anti- blooming. The use of pinned photodiodes (3) and pro- prietary transfer gate devices in the photoelements 1. ImageMOS is a Motorola trademark 2. Advanced CMOS Imager is a Kodak trademark 3. Patents held jointly by Motorola and Kodak
tral range and a lag free operation. Figure 3. MCM20014 Nominal spectral response sure timing in photographic terms, is a standard feature.
2.1.2 Color Separation and Fill Factor Enhancement
Figure 4. Optional on-chip Bayer CFA Figure 5. Improvement in pixel sensitivity results tions of the pixel by using microlenses.
2.1.3 Frame Capture Modes
tween the two available Frame Capture Modes (FCMs). gested guidelines for selection are given in this section. very fast or the illumination is varying. image where a flash illumination is utilized. Control Register, (Table 24), on page 31.
2.1.4 Image Scan Modes
modes: interlaced and progressive. and/or serrations to appear in the image. Control Register, (Table 25), on page 32.
2.1.5 Window of Interest Control
can be defined anywhere on the pixel array at any size.
Figure 6. WOI Definition
2.1.6 WOI Sub-sampling Control
sub-sampling is shown in Figure 7. Figure 7. Bayer Space Sub-sampling Example
2.1.7 CFCM Frame Rate and Integration Time
tion of the Virtual Frame and its relationship to the WOI. Figure 8. Virtual Frame Definition
sults in a Frame Rate of 32.21 frames per second.
2.1.8 SFCM Integration Time Control
integration time in steps of 16 MCLK periods.
2.2 Analog Signal Processing Chain Overview
a 10-bit Analog to Digital Converter (ADC).
2.2.1 Correlated Double Sampling (CDS)
of the signal eliminates correlated noise sources. Figure 9. Conceptual block diagram of CDS
2.2.2 Frame Rate Clamp (FRC)
ward dark level subtract reference level measurement. (dark) pixels to aid in establishing this reference. Figure 10. FRC Conceptual Block Diagram
the desired zero code at the ADC output. the CLRCA, B pins to reflect different frame rates. the per-column offsets is accomplished. Figure 11. Conceptual illustration of the auto calib- set adjust prior to the gain stages of the ASP.
2.2.3 Digitally Programmable Gain Amplifiers
2.2.3.1 White Balance Control PGA
gain of 0.9x to 4.6x in steps of 0.06x. el; and Reg (03h): green pixel of a blue-green row.
Figure 12. Color Gain Register Selection
2.2.3.2 Global Gain PGA
2.2.4 Global Digital Offset Voltage Adjust (DOVA)
Global DOVA Register, (Table 20), on page 28. and offsets of amplifiers in the analog chain.
2.2.5 Analog to Digital Converter (ADC)
characteristics for imaging applications. digitization of a 1.3V peak to peak signal.
2.3 Digital Signal Post Processing
bad pixels and output signal companding.
2.3.1 Bad Pixel Replacement
age, leading or trailing pixel value is made.
2.3.2 Data Compander
passed to output 10-bit linear data. Figure 13. Available Companding Curves
2.4 Additional Operational Conditions
user additional applications flexibility.
2.4.1 Initialization
achieved their required steady state values.
2.4.2 Standby Mode
ods which do not require operation of the MCM20014.
0 Data IN (10-bit)
2.4.3 References CVREFP, CVREFM
#18 respectively) to accurately hold the biases.
2.4.4 Internal Timing Control Register
tion to assure proper operation of the MCM20014.
2.4.5 Internal Bias Current Control
Figure 14. External Resistor Effect on Power Consumption at 13.5Mhz MCLK
3.0 MCM20014 Waveform Diagrams
waveform relationships for the pixel data.
3.1 CFCM Data Waveforms
16 depicts the first row of data in the frame.
3.2 SFCM Data Waveforms
22 depicts the first row of data in the frame. Figure 21. SFCM Default Frame Waveform Figure 22. SFCM Default Line Waveform row 12
Figure 23. SFCM Frame Waveform with Internal Timing Control Register = 00h Figure 24. SFCM Line Waveform with Internal Timing Control Register = 00h
4.0 MCM20014 Utility Programming Registers
4.1 Register Reference Map
Table 1. I2C Address Range Assignments
Table 2. I2C Address Assignments
Table 2. I2C Address Assignments (Continued)
5.0 Detailed Register Block Assignments
ease of addressability and use (see Table 1).
5.1 Analog Register Interface Block
5.1.1 Analog Color Configuration
CFA pattern color is listed in the title of each register. Table 3. DPGA Color 1 Gain Register Table 4. DPGA Color 2 Gain Register
a unique CFA option has been ordered. tion of 1, 2, or 4 rows and 1, 2, or 4 columns. Table 5. DPGA Color 3 Gain Register Table 6. DPGA Color 4 Gain Register Table 7. Color Tile Configuration Register
plied to pixel outputs as they are being read. Table 8. Color Tile Row 1 Definition Register
Table 9. Color Tile Row 2 Definition Register Table 10. Color Tile Row 3 Definition Register
5.1.2 Reference Voltage Adjust Registers
Table 11. Color Tile Row 4 Definition Register Table 12. Negative Voltage Reference Code Register
5.1.3 Analog Control Registers
Power Configuration Register by setting the dbt bit. Table 13. Positive Voltage Reference Code Register
7 Unused Unused x
6 Int/Ext
0 Software
Table 14. Power Configuration Register
sync signals SOF, VLCK, and HCLK. user programmable registers to a known reset state. those bits to 0 to enable continued operation.
5.2 Gain Caliberation Block
this register results in unity gain.
0 Soft Reset 0 b = Normal Mode
Table 15. Reset Control Register Table 16. DPGA Global Gain Register
5.3 Offset Calibration Block
final image black level set. resulting offset at the output. bal DOVA adjust circuit is enabled by default. 2C bus while writing to the Column DOVA RAM. bus as defined in this section. Table 17. Column DOVA DC Register
defined earlier in this section. the Column DOVA circuit must be taken into account. sents 2 code values in the 10-bit ADC output.
4 Column
1 Counter
Table 18. Column DOVA Control Register Table 19. Column DOVA RAM
5.4 Post ADC Block
registers and a general output control register. Care should be taken in assigning these thresholds. Table 20. Global DOVA Register
tain rudimentary transformations on the digitized data. are described in section 2.3.1 and above. the 10 to 8 bit noise coring described in section 2.3.2. breakpoint. Please see Figure 13, on page 11. Table 21. White Pixel Threshold Register Table 22. Black Pixel Threshold Register Table 23. Post ADC Control Register
5.5 Sensor Interface Block
5.5.1 Sensor Output Control
a timing diagram of this mode. or low. SOF is active high in default. rows or for the WOI rows only. The default is WOI only. or low. VCLK is active high in default. or low. HCLK is active high in default. 001b = 15 on the output axis. 010b = 31 on the output axis. 011b = 47 on the output axis. 100b = 63 on the output axis. 101b = 79 on the output axis. 110b = 95 on the output axis. 111b = 127 on the output axis.
(monochrome) or in color tiles of pixels (Bayer pattern). The pixels will be read in monochrome mode in default. of pixels out at the normal MCLK rate. is fully sampled in default.
7 Shutter
Table 24. Capture Mode Control Register
6 Scan Mode 1 b = Interlaced scan
5 Color
Table 25. Sub-sample Control Register
is one row wide while VLCK is 32 MCLKs wide. Table 26. SOF Control Register Table 27. VCLK Control Register
making these pulse widths 16 MCLKs wide.
5.5.2 Programmable “Window of Interest”
of the WOI within the active pixel array. anywhere within the active pixel array. Table 32), indicate the size of the WOI. Table 28. Internal Timing Control Register
addresses non-existant pixels.
0 WOI Row
Table 29. WOI Row Pointer MSB Register Table 30. WOI Row Pointer LSB Register Table 31. WOI Column Pointer MSB Register
Table 32. WOI Column Pointer LSB Register forms the 9-bit WOI Row Depth wrd[8:0]. Table 33. WOI Row Depth MSB Register forms the 9-bit WOI Row Depth wrd[8:0]. Table 34. WOI Row Depth LSB Register
5.5.3 Integration Time Control
Table 39, control the integration time for the pixel array. Frame and its relationship to the WOI. is sampled has no effect on integration time. forms the 10-bit WOI Column Width wcw[9:0]. Table 35. WOI Column Width MSB Register forms the 10-bit WOI Column Width wcw[9:0]. Table 36. WOI Column Width LSB Register
Table 37. Integration Time MSB Register ister, forms the 16-bit Integration Time cint[15:0]. Table 38. Integration Time ISB Register
ter, forms the 16-bit Integration Time cint[15:0]. Table 39. Integration Time LSB Register 41) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0]. Table 40. CFCM Virtual Frame Row Depth MSB Register
40) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0]. WOI is always top-left justified in Virtual Frame. Table 41. CFCM Virtual Frame Row Depth LSB Register Table 42. CFCM Virtual Frame Column Width MSB Register
6.0 I2C Serial Interface
into the Program Control Registers in the MCM20014.
6.1 MCM20014 I2C Bus Protocol
6.2 START Signal
6.3 Slave Address Transmission
vcw[13:0]. WOI is always top-left justified in Virtual Frame. Table 43. CFCM Virtual Frame Column Width LSB Register
1 = Read transfer, the slave transitions to a slave transmitter and sends the data to the master 0 = Write transfer, the master transmits data to the slave
6.4 Acknowledgment
Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDATA line low at the 9th clock (see Figure 25). If a transmitted slave address is acknowledged, successful slave addressing is said to have been achieved. No two slaves in the system may have the same address. The MCM20014 is configured to be a slave only.
6.5 Data Transfer
Once successful slave addressing is achieved, data transfer can proceed between the master and the se- lected slave in a direction specified by the R/W bit sent by the calling master. Note that for the first byte after a start signal (in Figure 25 and Figure 26), the R/W bit is always a “0” designating a write transfer. This is re- quired since the next data transfer will contain the reg- ister address to be read or written. All transfers that come after a calling address cycle are referred to as data transfers, even if they carry sub-ad- dress information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCLK is low and must be held stable while SCLK is high as shown in Figure 25. There is one clock pulse on SCLK for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pull- ing the SDATA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDATA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDATA line for the master to generate STOP or START signal.
6.6 Stop Signal
The master can terminate the communication by gener- ating a STOP signal to free the bus. However, the mas- ter may generate a START signal followed by a calling command without generating a STOP signal first. This is called a Repeated START. A STOP signal is defined as a low-to-high transition of SDATA while SCLK is at logical “1” (see Figure 25). The master can generate a STOP even if the slave has generated an acknowledge bit at which point the slave must release the bus.
6.7 Repeated START Signal
A Repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to commu- nicate with another slave or with the same slave in a dif- ferent mode (transmit/receive mode) without releasing the bus. As shown in Figure 26, a Repeated START signal is be- ing used during the read cycle and to redirect the data transfer from a write cycle (master transmits the register address to the slave) to a read cycle (slave transmits the data from the designated register to the slave).
Figure 25. WRITE Cycle using I2C Bus
6.8 I2C Bus Clocking and Synchronization
the slave releases the SCLK line.
6.9 Register Write
6.10 Register Read
Figure 26. READ Cycle using I2C Bus
7.0 Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS1 (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage -0.5 to 3.8 V Vin DC Input Voltage 0.5 to VDD + 0.5 V Vout DC Output Voltage -0.5 to VDD + 0.5 V I DC Current Drain per Pin, Any Single Input or Output ±50 mA I DC Current Drain, VDD and VSS Pins ±100 mA TSTG Storage Temperature Range -65 to +150 °C TL Lead Temperature (10 second soldering) 300 °C 1 Maximum Ratings are those values beyond which damage to the device may occur. VSS = AVSS = DVSS = VSSO (DVSS = VSS of Digital circuit, AVSS = VSS of Analog Circuit) VDD = AVDD = DVDD = VDDO (DVDD = VDD of Digital circuit, AVDD = VDD of Analog Circuit) RECOMMENDED OPERATING CONDITIONS (to guarantee functionality; voltage referenced to VSS) Symbol Parameter Min Max Unit VDD DC Supply Voltage, VDD = 3.3V (Nominal) 3.0 3.6 V TA Commercial Operating Temperature 0 40 °C TJ Junction Temperature 0 55 °C Notes: - All parameters are characterized for DC conditions after thermal equilibrium has been established. - Unused inputs must always be tied to an appropriate logic level, e.g., either V SS or VDD. - This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedan ce circuit. - For proper operation it is recommended that V in and Vout be constrained to the range VSS < (Vin or Vout) < VDD. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V ± 0.3V; VDD referenced to VSS; Ta = 0°C to 40°C) TA = 0°C to 40°C Symbol Characteristic Condition Min Max Unit VIH Input High Voltage 2.0 VDD+0.3 V VIL Input Low Voltage -0.3 0.8 V Iin Input Leakage Current, No Pull-up Resistor Vin = VDD or VSS -5 5µ A IOH Output High Current VDD = Min, VOH Min = 0.8 * VDD -3 mA IOL Output Low Current VDD = Min, VOL Max = 0.4 V 3m A VOH Output High Voltage VDD = Min, IOH = -100µAV DD - 0.2 V VOL Output Low Voltage VDD = Min, IOL = 100µA 0.2 V IOZ 3-State Output Leakage Current Output = High Impedance, Vout = VDD or VSS -10 10 µA IDD Maximum Standby Supply Current Iout = 0mA, Vin = VDD or VSS 0 15.0 mA
POWER DISSIPATION (VDD = 3.0V, VDD referenced to VSS; Ta = 25°C) Symbol Parameter Condition Typ Unit PDYN Dynamic Power 13.5 MHz MCLK Clock frequency 400 mW PSTDBY Standby Power STDBY Pin Logic High 50 mW PAVG Average Power 13.5 MHz Operation (using STDBY) 200 mW MCM20014 MONOCHROME CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS Symbol Parameter Typ Unit Notes Esat Saturation Exposure 0.14 µJ/cm2 1 QE Peak Quantum Efficiency (@550nm) 18 % 2 PRNU Photoresponse Non-uniformity 12 % pk-pk 3 Notes: 1.For λ = 550 nm wavelength. 2.Refer to typical values from Figure 3, MCM20014 nominal spectral response. 3.For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. MCM20014 COLOR CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS Symbol Parameter Typ Unit Notes Esat Saturation Exposure 0.3 µJ/cm2 1 QEr Red Peak Quantum Efficiency @ λ = 650 nm 12 % 2 QEg Green Peak Quantum Efficiency @ λ = 550 nm 11 % 2 QEb Blue Peak Quantum Efficiency @ λ = 450 nm 8 % 2 Notes: 1.For λ = 550 nm wavelength. 2.Refer to typical values from Figure 3, MCM20014 nominal spectral response. CMOS IMAGE SENSOR CHARACTERISTICS Symbol Parameter Typ Unit Notes Sensitivity 3.0 V/lux-sec Id Photodiode Dark Current 0.2 nA/cm2 DSNU Dark Signal Non-Uniformity (Entire Field) 0.4 % rms CTE Pixel Charge Transfer Efficiency 0.9995 % 1 fH Horizontal Imager Frequency 11.5 MHz 4 Xab Blooming Margin - shuttered light 200 2,3 Notes: 1. Transfer efficiency of photosite 2. Xab represents the increase above the saturation-irradiance level (H sat) that the device can be exposed to before blooming of the pixel will occur. 3. No column streaking 4. At 30fps VGA
ANALOG SIGNAL PROCESSOR CHARACTERISTICS GENERAL Symbol Parameter Typ Unit Notes ne- total Total System (equivalent) Noise Floor 70 e- rms 1 DR System Dynamic Range 50 dB Notes: 1.Includes amplifier noise, dark pattern noise and dark current shot noise at 13.5 MHz data rates. Analog to Digital Converter (ADC) Symbol Parameter Min Typ Max Units Resolution 10 bits VIN Input Dynamic Range8 2.5 Vpp INL Integral Non-Linearity + 1.0 LSB DNL Differential Non-Linearity + 0.5 LSB fmax ADC Clock Rate 13.5 MHz Notes:
8 Effective differential signal dynamic range
- INL & DNL test limits are adjusted to compensate for the effects of the LRC, DOVA and DPGA stages between teh EXT_VINS inpt and the input of the ADC.
Figure 27. I2C Bus Timing Diagram
6 I2C is a proprietary Philips interface bus
8 The capacitive load is 200 pF
Figure 28. Pixel Data Bus Timing Diagram
Figure 29. MCM20014 Pinout Diagram Table 44. MCM20014 Pin Definitions
1 ADC6 Output Bit 6 = 64 10 Weight O 25 SCLK I2C Serial Clock I/O
2 ADC5 Output Bit 5 = 32 10 Weight O 26 SDATA I2C Serial Data I/O
3 ADC4 Output Bit 4 = 16 10 Weight O 27 STBY Power Down Standby Enable I
4 ADC3 Output Bit 3 = 8 10 Weight O 28 INIT Sensor Intialize I
5 ADC2 Output Bit 2 = 4 10 Weight O 29 TS Three State Ouput Enable I
6 ADC1 Output Bit 1 = 2 10 Weight O 30 SYNC Sensor Sync Signal I
7 ADC0 Output Bit 0 = 1 10 Weight O 31 DVDD Digital Power P D
8 DVDD Digital Power P D 32 TEST_IN9 Test Input 9 I
9 DVSS Digital Ground G D 33 TEST_IN8 Test Input 8 I
10 BLANK Pixel In-valid O 34 TEST_IN7 Test Input 7 I
11 AVDD Analog Power P A 35 TEST_IN6 Test Input 6 I
12 AVSS Analog Ground G A 36 TEST_IN5 Test Input 5 I
13 EXTRES External Bias Resisitor Input I 37 TEST_IN4 Test Input 4 I
14 TEST_AI Test Analog Chain Input I 38 TEST_IN3 Test Input 3 I
15 TEST_AO Test Analog Video Output O 39 TEST_IN2 Test Input 2 I
16 AVDD Analog Power P A 40 TEST_IN1 Test Input 1 I
17 AVSS Analog Ground G A 41 TEST_IN0 Test Input 0 I
18 CVREFM Bias Reference Bottom Output O 42 DVSS Digital Ground G D
19 CVREFP Bias Reference Top Output O 43 HCLK Pixel Sync O
20 CLRCB Line Rate Clamp Output O 44 VCLK Line Sync O
21 CLRCA Line Rate Clamp Output O 45 SOF Start Of Frame O
22 AVDD Analog Power P A 46 ADC9 Output Bit 9 = 512
10 Weight O
23 AVSS Analog Ground G A 47 ADC8 Output Bit 8 = 256 10 Weight O
24 MCLK Master Clock I 48 ADC7 Output Bit 7 = 128 10 Weight O
Figure 30. 48 Terminal ceramic leadless chip carrier (bottom view)
Figure 31. Center of the focal plane array with respect to the die cavity (top view) Note: Pictured elements are shown for reference, not to scale.
- Dimensions are in inches.
- Interpret dimensions and tolerances per
Figure 32. Focal plane with respect to package.
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