MCM14537 | DigiCamel IC Datasheet

Online Datasheet

Read MCM14537 online.

MCM14537 MOTOROLA | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 8

Technical content

256-BIT STATIC RANDOM ACCESS MEMORY CMOS LSI The MCM14537 is a static random access memory (RAM) organ- (LOW-POWER COMPLEMENTARY MOS) ized in a 256 x 1-bit pattern and constructed with MOS P-channet tod N-channel enhancement mode devices In a single monolithic structure, The circuit consists of eight address inputs (An), one data 256-BIT (256 x 1) STATIC input (Din), one write enable input (WE), one strobe input (ST), two RANDOM ACCESS MEMORY chip enable inputs (CE p), and one data output (Dour). Using both chip enable inputs as extensions of the address inputs, a 10-bit address scheme may be employed. Four MCM14537 devices may be used to comprise a 1024-bit memory without additional address decoding. The CE and ST inputs are dissimilary designed to enable usage of the memory in a variety of applications. An output latch is provided on the chip for storing the data read or written into memory, making a data-out storage register unnecessary. The CE inputs control the data output for third-state (high output imped: 16 ance) or active operation which makes the memory very useful in a 1 bus oriented system. When CE2 is high the chip is fully disabled.

3 When CE1 is high the output is in the third state but data can be CERAMIC PACKAGE

written into the output latch during a read cycle. This enables the CASE 690 use of the memory for fast reading by using the CE 1 input to enable the latch, The memory is also designed so that de signals can operate ORDERING INFORMATION She memory with no maximum pulse width required on the CE and MCMTaxX Sutfix Denotes device useful in scratch pad and buffer applications where micro ower or battery operation and high noise immunity are required. Ae oe tance, © Quiescent Current = 0.5 uA/package typical @ 5 Vde C Limited Operating © Noise Immunity = 45% of Vop typical ee ‘© 3.state Output Capability for Memory Expansion © Output Data Latch Eliminates Need for Storage Buffer PIN ASSIGNMENT © Access Time = 700 ns typical @ Vpp = 10 Vde © Futly Decoded and Buffered + a © Supply Voltage Range = 3.0 Vde to 18 Vde acqae aos © Capable of Driving Two Low-power TTL Loads, One Low-power 31 On are Schottky TTL Load or Two HTL Loads Over the Rated Temper woe mba ‘ature Range s as ce2 12 MAXIMUM RATINGS (Voltages referenced to Vss) Vout! § Vop- ve Vo! 3-12

ELECTRICAL CHARACTERISTICS

a Symtt [ae [Mex [te te [en [in | oes Sos os [ees es 95, yee se yse 23 38 | ago (vos ns vee 35 xo | be oa ‘Sects "0 eo eo 3600 ia ea ~~ 7200, eo ico 3200 *Thow ~ -85°C for AL Device, -40°C for CLICP Device Thigh = 125°C for AL Device, +85°C for CL/CP Device. TricL) - triS0 pF) + 1 x 10°3 (Cy -50) Voot ** The formulas given are for the typical characteristics only at 25°C.

SWITCHING CHARACTERISTICS* (Cy = 50 pF, Ta - 25°C) [Characteristic TT FiureTsvmbot [Vo | Tye [Max] unit] ‘Output Rise Time *TLH 8 TTLH © (3.0 ns/pF) Cy + 30 ns 180 | 960 | TTLH = (1.5 ns/pF) Cy + 15 ns so | 10 | TTLH= (1.1 asipF) CL + 10 08 65 | 130 Duiput Fall Time THe 8 TTHL = (1.8 ns/pF) Cy + 25 08, 100 | 200 TTHL « (0.75 ns/pF) CL + 125 ns 80 | 100 LATHE = 10.55 nsipF) CL + 9.8 8 40 | 80 [Fread Access Time from ST or GE2 ‘acct % ace * (1.4 nsipF Cy + 2480 ns 400 | 2500 | 6000 ace * (0.7 lpF) CL + 690 ns 160 | 700 | 2000 ace = (0.5 nsipF) Cy +393 ns _ 415 | 400. | 1500_| | Output Enable Delay from CET or CE2 — TaceiCEq) 7 | 300 | 900 | ns | 25 | 100 | 300 20 | 70 | 25 ‘Setup Time from An to ST or CE2 45.6.7 woo | 600 | — ms 600 | 200 | - pC 450 | 140) | Hold Time from Aq to ST or CE2 45,67 | may | 50 | 600 | 200 | — “s 10 | 240 | go | - oo - ee Data Hold Time 7 mio) | 80 | 1400 | 480) ne 3 a is [am | no | VDeeSwetme SSS 7 tuto) | 60 | 3600 | 1200 | ne | 10 | 1800 | 600 | - | ! 1s | 1350 | 420 ‘Write Enable Hold Time 7 thiWe) 80 | 150 so ne | 10 60 2a) | ws | 45 | ts ‘Waite Enable Sotup Time 7 wwe) | 50 | 720°) 200) me ' to | 240) 8 | - Waite Enable to Duy Disable 4 we so | 720 | 20 | — 8 to | 240 | go | = i _ 1s | t80 | 55 | | Birabe or GE2 Pulse Width When Reading 4.5.6 | wor | 50 | 1360 | 450 | — m8 | ro | 450 | 16000 = | a ee ee ‘Sivobe, CET or CET uve Width When Writing 19 www) &O | e400] 4300 T= Tae Hite Recovery Tine at 7 Write Recovery Time a tRW) 7 t= (1.4 nsipF) Cy +219 ns | ' 50 | 7 | 240 | 720 tw (0.7 nsipF) Cy + 70 ns | : to | 2 | a0 | 240 L tw= (05 asfoF) Cy +475 ns | Lo 1_{ 20 | 35 | 190_| | i 10 | 25 | 100 | 300 Reed Setup Time — tas wiry) 8010 | 100 i wo | 0 | -ao | = Reed Hold Time a5 min) | 50 | 840 | 180 | ns | to | 20 | 6 | TRead Cycle Time 48 teyciA) 5.0 = 2500 | 6000 ns j 10 700 | 2100 / [Wate Gyele Time — 7 tye) | 50 | - | 1400 | 4800 | as “The formula given is for the typical characteristics only **10% output change into 9 1.0 KS load 3-14

ro 44 Output Source | Ovtput Sink Pulse ° as Characteristics [Characteristics j Vour~ Yi Vout — ~o od cet Externat = oe von , O—O ce2 Power Vss ———0 2 b vss pee sour (v0) i 1 o—iat { 1 oes af \\_Sf \\_ en Generator — ron 4 ar | : en “ due ce2 = | Vss FIGURE 3— AC TEST CIRCUIT |

9 Yoo

FIGURE 6 ~ READ CYCLE WAVEFORMS UTILIZING GEi AND CE2 TO ACCESS MEMORY v Across oo tas) T Vss twine tia) twoiray CER © ‘50% Vss aetay CE) — f- So Yoo ca ‘50% “accice,y — 26,9 v r on bee ouput YY (Pou! Y) WUD SY) MD“seta Vou NOTES: 1 High impedance output state occurs when GET or CE2 is maintained inthe logical "1 state (high level

2 WE is maintained at the logical "1" state for this example

3 allinput rn and tal mes are 208 kc} 4 taetay(CEz) Minimum auveres thet only deta presently sddressed ‘et appear at the output Ydelay(CE2) min. ~ "accg max, — @CC(EET) min, 5 WLIR2) > tgalay (CE2) min # face (Cn! max FIGURE 7 — WRITE CYCLE WAVEFORMS v Address had Inputs 50% An! Vss ———teyeww) tua) ol www) tna) ——e| SOBs oF — Von GET or CER fo) (ST, CE1, CED) Vss Le _ bene Wri EnabTe ® «Wey 50% vss Vou Date input (On) @ <2 > ail 2 Vou NOTES: 1 The Strobe, CE ang CEZ may be utilized to control a write cycle, however, during changes of adaress either Strobe or CE2 must be in the logical "1" state (high vel)

2 Date Input logic level i don’t care during the indicated intervals

3 Date input logic level must remain fined

44 Write Enable may be maintained ata logical "0" during the write cycle

All input rim and fall times are 20 08 3-17

Product Information

MCM14537 specifications and overview.

Summary

CMOS LSI

Description

CMOS LSI

Source title MCM14537 Datasheet(PDF) - Motorola, Inc

Related Parts

More parts from the same family.

Browse manufacturer