MCM101524 MOTOROLA | Alldatasheet
Document overview
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Technical content
The MCM101524 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits. This circuit is fabricated using high performance silicon–gate BiCMOS technology. Asynchronous design eliminates the need for external clocks or timing strobes. The MCM101524 is available in a 400 mil, 36 lead TAB.
- Fast Access Times: 12, 15 ns
- Equal Address and Chip Select Access Times
- Power Operation: – 195 mA Maximum, Active AC BLOCK DIAGRAM ROW DECODER MEMORY MATRIX
1024 ROWS x
4096 COLUMNS
S W A16 A7 A6 A4 A2 A17 VCC VEE PIN NAMES This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Order this document by MCM101524/D /C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA PIN ASSIGNMENT MCM101524 33A13 A12 A11 A10 S A14 VEE VCC A15 W A17 A16 A18 VCC NC VEE A19 NC TB PACKAGE
400 MIL TAB
CASE 984A–01 REV 2 Motorola, Inc. 1994
TRUTH TABLE (X = Don’t Care) S W Operation Data Output Current H X Not Enabled X L — L H Read X Q IEE L L Write X L IEE ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VEE Pin Potential (to Ground) VEE – 7.0 to + 0.5 V Voltage Relative to VCC for Any Pin Except VEE Vin, Vout VEE – 0.5 to+ 0.5 V Output Current (per I/O) Iout – 50 mA Power Dissipation PD 2.0 W Temperature Under Bias Tbias – 30 to + 85 °C Operating T emperature TJ 0 to + 60 °C Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the OPERATING CONDI - TIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 0 V, VEE = – 5.2 V ±/n6368617200000000000000005%, TJ = 0 to + 60°C, Unless Otherwise Noted) DC OPERATING CONDITIONS AND SUPPLY CURRENTS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VEE – 5.46 – 5.2 – 4.94 V Input High Voltage VIH – 1165 — – 880 mV Input Low Voltage VIL – 1810 — – 1475 mV Output High Voltage VOH – 1025 — – 880 mV Output Low Voltage VOL – 1810 — – 1620 mV Input Low Current IIL – 50 — — µA Input High Current IIH — — 220 µA Chip Select Input Low Current IIL(CS) 0.5 — 170 µA Operating Power Supply Current: tAVAV = 20 ns (All Outputs Open)* IEE — — – 195 mA Quiescent Power Supply Current: fo = 0 MHz (Outputs Open) IEEQ — — – 150 mA Voltage Compensation (VOH ) ΔVOH /ΔVEE ±/n63686172000000000000000035 mV/V @ – 4.94 to – 5.46 V Voltage Compensation (VOL ) ΔVOL /ΔVEE ±/n63686172000000000000000060 mV/V @ – 4.94 to – 5.46 V * Address Increment RISE/FALL TIME CHARACTERISTICS Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr 20% to 80% 0.5 1.0 1.5 ns Output Fall Time tf 20% to 80% 0.5 1.0 1.5 ns CAPACITANCE (f = 1.0 MHz, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Typ Max Unit Input Capacitance Address and Data S, W C in C ck 3.5 pF Output Capacitance Q C out 4 8 pF This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is ad- vised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifica- tions shown in the tables, after thermal equi- librium has been established. The circuit is in a test socket or mounted on a printed cir- cuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Output Timing Measurement Reference LevelVOH = – 1165 mV. .
- W is high for read cycle.
2.Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3.All read cycle timings are referenced from the last valid address to the first transitioning address. 4.This parameter is sampled and not 100% tested.
- Device is continuously selected (S ≤ VIL).
6.Addresses valid prior to or coincident with S going low. Figure 1. Input Levels Figure 2. AC Test Circuit
READ CYCLE 1 (See Notes 1, 2, and 5) Q (DATA OUT) A (ADDRESS) DATA VALIDPREVIOUS DATA VALID tAVAV tAXQX tAVQV READ CYCLE 2 (See Note 6) DATA VALID tSHQL S (CHIP SELECT) Q (DATA OUT) tSLQV A (ADDRESS) tAVAV tSHIEELtSLIEEH SUPPLY CURRENT IEE
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM101524–12 MCM101524–15 Parameter Symbol Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — ns 3 Address Setup Time tAVWL 1 — 1 — ns Address Valid to End of Write tAVWH 9 — 10 — ns Write Pulse Width tWLWH , tWLSH 8 — 9 — ns Data Valid to End of Write tDVWH 8 — 9 — ns Data Hold Time tWHDX 1 — 1 — ns Write High to Output Active tWHQX 4 — 4 — ns 4 Write High to Output Valid tWHQV — 13 — 16 ns Write Recovery Time tWHAX 1 — 1 — ns Write Low to Output Low tWLQL 0 8 0 9 ns NOTES: 1. A write occurs during the overlap of S low and W low. 2.Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3.All write cycle timings are referenced from the last valid address to the first transitioning address. 4.This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) tDVWH tAVWL tAVWH tAVAV tWHAX tWLWH tWHDX tWLQL tWHQX A (ADDRESS) S (CHIP SELECT) Q (DATA OUT) D (DATA IN) tWLSH W (WRITE ENABLE) tWHQV DATA VALID ADDRESS VALID Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
WRITE CYCLE 2 (S Controlled, See Notes 1 and 2) MCM101524–12 MCM101524–15 Parameter Symbol Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — ns 3 Address Setup Time tAVSL 1 — 1 — ns Address Valid to End of Write tAVSH 9 — 10 — ns Write Pulse Width (S ) (W ) tSLSH tSLWH 8 — 9 — ns Data Valid to End of Write tDVSH 8 — 9 — ns Chip Select Set–Up Time tSLWL 0 — 0 — ns Data Hold Time tSHDX 1 — 1 — ns Write Recovery Time tSHAX 1 — 1 — ns NOTES: 1. A write occurs during the overlap of S low and W low. 2.Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3.All write cycle timings are referenced from the last valid address to the first transitioning address. WRITE CYCLE 2 (S Controlled, See Notes 1 and 2) tSLWH tSHAX tDVSH tAVSL tSLSH tAVSH DATA VALID tAVAV A (ADDRESS) W (WRITE ENABLE) S (CHIP SELECT) Q (DATA OUT) D (DATA IN) tSHDX tSLWL
ORDERING INFORMATION
(Order by Full Part Number) MCM 101524 XX XX XX Motorola Memory Prefix Part Number Speed (12 = 12 ns, 15 = 15 ns) Package (TB = TAB) Shipping Method (Blank = Rails) Full Part Numbers — MCM101524TB12 MCM101524TB15
CASE 984A–01 PACKAGE DIMENSIONS VIEW AM REF 3X TAB TAPE WV U S R TAB TAPE CARRIER K J AD P Z SECTION AN–AN DIM A MIN MAX MIN MAX INCHES 18.14 REF 0.714 REF MILLIMETERS B 8.03 REF 0.316 REF C 26.95 BSC 1.061 BSC C1 26.95 BSC 1.061 BSC P 3.00 REF 0.118 REF R 2.39 REF 0.094 REF S 50.00 REF 1.969 REF S1 50.00 REF 1.969 REF U 6.00 REF 0.236 REF U1 6.00 REF 0.236 REF V 39.40 REF 1.551 REF W 45.68 REF 1.798 REF Y 38.00 REF 1.496 REF Z 1.15 1.25 0.045 0.049 AA 16.21 16.31 0.638 0.642 AB 11.20 11.30 0.441 0.445 AC 8.99 9.09 0.354 0.358 AD 0.15 0.21 0.006 0.008 AE 0.762 BSC 0.030 BSC AF 0.18 0.28 0.007 0.011 AG 21.31 21.24 0.832 0.836 AH 35.00 REF 1.378 REF AJ 25.40 REF 1.000 REF AK 26.95 BSC 1.061 BSC AL 34.98 REF 1.377 REF AR 0.65 0.75 0.026 0.030 AS 0.50 BSC 0.020 BSC AT 0.60 0.70 0.024 0.028 AU 26.95 REF 1.061 REF AV 25.35 25.45 0.998 1.002 AV1 25.35 25.45 0.998 1.002 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. Y RETAINERCARRIER 1 36 B VIEW AM A -M- -H- ANAN 4X 1.40 (0.055) H0.05 (0.002)S T M-N S S -N- TAPE CARRIER RETAINER ELIMINATED FROM VIEW FOR CLARITY C -T-
CASE 984A–01 (cont.) AV1 AV BOTTOM VIEW AU REF 4X 2.00 (0.78) AL AE/2 AE AK AJ AA AB AC H0.25 (0.010)S T M-N S S H0.25 (0.010)S T M-N S S VIEW AP AH 36X AF AG H0.05 (0.0020) S T M-N S S 34X AS194X 196X AR H0.10 (0.004)L T M-N S S AT REF AS H0.10 (0.004)L T M-N S S VIEW AP Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. MCM101524/D /C0042/C0077/C0067/C0077/C0049/C0048/C0049/C0053/C0050/C0052/C0047/C0068/C0042 ◊ CODELINE TO BE PLACED HERE