MCL908QT1

MC68HLC908QY4 FREESCALE | Alldatasheet

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freescale.com MC68HLC908QY4 MC68HLC908QT4 MC68HLC908QY2 MC68HLC908QT2 MC68HLC908QY1 MC68HLC908QT1 Data Sheet MC68HLC908QY4/D Rev. 3

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 3 Freescale™ and the Freescale logo are trade marks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004. All rights reserved. MC68HLC908QY4 MC68HLC908QT4 MC68HLC908QY2 MC68HLC908QT2 MC68HLC908QY1 MC68HLC908QT1 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/

Revision History

MC68HLC908QY/QT Family Data Sheet, Rev. 3

4 Freescale Semiconductor

The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Number(s) August,

2003 N/A Initial release N/A

October, 2003 1.0 Figure 2-2. Control, Status, and Data Registers Deleted unimplemented areas from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also corrected $FFBF designation from unimplemented to reserved. Figure 6-1. COP Block Diagram — Reworked for clarity 57

6.3.2 STOP Instruction — Added su bsection for STOP instruction 58

13.4.2 Active Resets from Internal Sources — Reworked notes for clarity. 115 15.3 Monitor Module (MON) — Clarified seventh bullet. 154 16.5 DC Electrical Characteristics — Corrected notes 4 and 5. 169

16.6 Control Timing — Updated values for RST input pulse width low and IRQ

interrupt pulse width low 170 January, 2004 2.0 Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the FLASH Block Protect Register at address location $FFBE and the Internal Oscillator Trim Value at $FFC0. Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for clarity. 37 July, 2005 3.0 Reformatted to meet current documentation standards Throughout Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary: Reworked definitions for STOP instruction Added WAIT instruction 13.8.1 SIM Reset Status Register — Clarified SRSR flag setting. 117 14.9.1 TIM Status and Control Register — Added information to TSTOP note. 127 17.3 Package Dimensions — Updated package information. 163

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 5 List of Chapters

MC68HLC908QY/QT Family Data Sheet, Rev. 3

6 Freescale Semiconductor

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 7 Table of Contents Chapter 1 General Description Chapter 2 Memory Chapter 3 Analog-to-Digital Converter (ADC)

MC68HLC908QY/QT Family Data Sheet, Rev. 3

8 Freescale Semiconductor

Auto Wakeup Module (AWU) Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 9 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI)

MC68HLC908QY/QT Family Data Sheet, Rev. 3

10 Freescale Semiconductor

Low-Voltage Inhibit (LVI) Chapter 11 Oscillator Module (OSC)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 11 Chapter 12 Input/Output Ports (PORTS) Chapter 13 System Integration Module (SIM)

MC68HLC908QY/QT Family Data Sheet, Rev. 3

12 Freescale Semiconductor

Timer Interface Module (TIM) Chapter 15 Development Support

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 13 Chapter 16 Electrical Specifications Chapter 17 Ordering Information and Mechanical Specifications

MC68HLC908QY/QT Family Data Sheet, Rev. 3

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 15 Chapter 1 General Description

1.1 Introduction

The MC68HLC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4

1.2 Features

Features include:  High-performance M68HC08 CPU core  Fully upward-compatible object code with M68HC05 Family  Operating voltage range of 2.2 V to 3.6 V  2-MHz internal bus operation  Trimmable internal oscillator – 1.0 MHz internal bus operation – 8-bit trim capability allows 0.4% accuracy (1) – ± 25% untrimmed  Auto wakeup from STOP capability  Configuration (CONFIG) register for MCU configuration options, including: – Low-voltage inhibit (LVI) trip point  In-system FLASH programming  FLASH security (2) Table 1-1. Summary of Device Variations Device FLASH Memory Size Analog-to-Digital Converter Pin Count MC68HLC908QT1 1536 bytes — 8 pins MC68HLC908QT2 1536 bytes 4 ch, 8 bit 8 pins MC68HLC908QT4 4096 bytes 4 ch, 8 bit 8 pins MC68HLC908QY1 1536 bytes — 16 pins MC68HLC908QY2 1536 bytes 4 ch, 8 bit 16 pins MC68HLC908QY4 4096 bytes 4 ch, 8 bit 16 pins 1. The oscillator frequency is guaranteed to ±5% over temperature and voltage range after trimming. 2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

MC68HLC908QY/QT Family Data Sheet, Rev. 3

16 Freescale Semiconductor

 On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) – MC68HLC908QY4 and MC68HLC908QT4 — 4096 bytes – MC68HLC908QY2, MC68HLC908QY1, MC 68HLC908QT2, and MC68HLC908QT1— 1536 bytes  128 bytes of on-chip random-access memory (RAM)  2-channel, 16-bit timer interface module (TIM)  4-channel, 8-bit analog-to-digital converter (ADC) on MC68HLC908QY2, MC68HLC908QY4, MC68HLC908QT2, and MC68HLC908QT4  5 or 13 bidirectional input/output (I/O) lines and one input only: – Six shared with keyboard interrupt function and ADC – Two shared with timer channels – One shared with external interrupt (IRQ) – Eight extra I/O lines on 16-pin package only – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an individual bit basis – Three-state ability on all port pins  6-bit keyboard interrupt with wakeup feature (KBI)  Low-voltage inhibit (LVI) module features: – Software selectable trip point in CONFIG register  System protection features: – Computer operating properly (COP) watchdog – Low-voltage detection with optional reset – Illegal opcode detection with reset – Illegal address detection with reset  External asynchronous interrupt pin with internal pullup (IRQ ) shared with general-purpose input pin  Master asynchronous reset pin (RST ) shared with general-purpose input/output (I/O) pin  Power-on reset  Internal pullups on IRQ and RST to reduce external components  Memory mapped I/O registers  Power saving stop and wait modes  MC68HLC908QY4, MC68HLC908QY2, and MC68HLC908Q Y1 are available in these packages: – 16-pin plastic dual in-line package (PDIP) – 16-pin small outline integrated circuit (SOIC) package – 16-pin thin shrink small outline package (TSSOP)  MC68HLC908QT4, MC68HLC908QT2, and MC68HLC9 08QT1 are available in these packages: – 8-pin PDIP – 8-pin SOIC – 8-pin dual flat no lead (DFN) package

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 17 Features of the CPU08 include the following:  Enhanced HC05 programming model  Extensive loop control functions  16 addressing modes (eight more than the HC05)  16-bit index register and stack pointer  Memory-to-memory data transfers  Fast 8 × 8 multiply instruction  Fast 16/8 divide instruction  Binary-coded decimal (BCD) instructions  Optimization for controller applications  Efficient C language support

1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HLC908QY4.

1.4 Pin Assignments

The MC68HLC908QT4, MC68HLC908QT2, and MC68HLC908QT1 are available in 8-pin packages and the MC68HLC908QY4, MC68HLC908QY2, and MC68HLC908QY1 in 16-pin packages. Figure 1-2 shows the pin assignment for these packages.

MC68HLC908QY/QT Family Data Sheet, Rev. 3

18 Freescale Semiconductor

Figure 1-1. Block Diagram RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in

12.1 Introduction)

ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC

128 BYTES RAM

MC68HLC908QY4 AND MC68HLC908QT4

4096 BYTES

MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1:

1536 BYTES

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 19 Figure 1-2. MCU Pin Assignments PTB0 PTB2 PTB3PTB4 VSS PTB6 PTB7 PTB1 8-PIN ASSIGNMENT MC68HC908QT1 PDIP/SOIC 16-PIN ASSIGNMENT MC68HC908QY1 PDIP/SOIC VSSVDD PTA5/OSC1/KBI5 PTA4/OSC2/KBI4 PTA3/RST/KBI3 PTA1/TCH1/KBI1 PTA0/TCH0/KBI0 PTA2/IRQ/KBI2/TCLK VDD PTA1/TCH1/KBI1 PTB5 PTA2/IRQ/KBI2/TCLK PTA0/TCH0/KBI0PTA5/OSC1/KBI5 PTA4/OSC2/KBI4 PTA3/RST/KBI3 PTB2 PTB3 PTB4 PTB6 PTB7 16-PIN ASSIGNMENT MC68HC908QY1 TSSOP PTA1/TCH1/KBI1 PTB5 PTA2/IRQ/KBI2/TCLK PTA5/OSC1/KBI5 PTA4/OSC2/KBI4 PTA3/RST/KBI3 PTA0/TCH0/KBI0 PTB1 PTB0 VSS VDD 8-PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC VSSVDD PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTA3/RST/KBI3 PTA1/AD1/TCH1/KBI1 PTA0/AD0/TCH0/KBI0 PTA2/IRQ/KBI2/TCLK PTB0 PTB2 PTB3PTB4 VSS PTB6 PTB7 PTB1 16-PIN ASSIGNMENT MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC VDD PTA1/AD1/TCH1/KBI1 PTB5 PTA2/IRQ/KBI2/TCLK PTA0/AD0/TCH0/KBI0PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTA3/RST/KBI3 16-PIN ASSIGNMENT MC68HC908QY2 AND MC68HC908QY4 TSSOP PTA0/TCH0/KBI0 V SS VDD PTA5/OSC1/KB15 8-PIN ASSIGNMENT MC68HC908QT1 DFN 8-PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 DFN PTA1/TCH1/KBI1 PTA3/RST/KBI3 PTA2/IRQ/KBI2/TCLK PTA4/OSC2/KBI4 PTA0/AD0/TCH0/KBI0 VSS VDD PTA5//OSC1/AD3/KB15 PTA1/AD1/TCH1/KBI1 PTA3/RST /KBI3 PTA2/IRQ/KBI2/TCLK PTA4/OSC2/AD2/KBI4 PTB2 PTB3 PTB4 PTB6 PTB7 PTA1/AD1/TCH1/KBI1 PTB5 PTA2/IRQ/KBI2/TCLK PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTA3/RST/KBI3 PTA0/AD0/TCH0/KBI0 PTB1 PTB0 VSS VDD

MC68HLC908QY/QT Family Data Sheet, Rev. 3

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1.5 Pin Functions

Table 1-2 provides a description of the pin functions. Table 1-2. Pin Functions Pin Name Description Input/Output VDD Power supply Power VSS Power supply ground Power PTA0 PTA0 — General purpose I/O port Input/Output AD0 — A/D channel 0 input Input TCH0 — Timer Channel 0 I/O Input/Output KBI0 — Keyboard interrupt input 0 Input PTA1 PTA1 — General purpose I/O port Input/Output AD1 — A/D channel 1 input Input TCH1 — Timer Channel 1 I/O Input/Output KBI1 — Keyboard interrupt input 1 Input PTA2 PTA2 — General purpose input-only port Input IRQ — External interrupt with programmable pullup and Schmitt trigger input Input KBI2 — Keyboard interrupt input 2 Input TCLK — Timer clock input Input PTA3 PTA3 — General purpose I/O port Input/Output RST — Reset input, active low with internal pullup and Schmitt trigger Input KBI3 — Keyboard interrupt input 3 Input PTA4 PTA4 — General purpose I/O port Input/Output OSC2 —XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) Output Output AD2 — A/D channel 2 input Input KBI4 — Keyboard interrupt input 4 Input PTA5 PTA5 — General purpose I/O port Input/Output OSC1 —XTAL, RC, or external oscillator input Input AD3 — A/D channel 3 input Input KBI5 — Keyboard interrupt input 5 Input PTB0:7 1. The PTB pins are not available on the 8-pin packages (see note in 12.1 Introduction). 8 general-purpose I/O ports Input/Output

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 21

1.6 Pin Function Priority

Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function Priority in Shared Pins Pin Name Highest-to-Lowest Priority Sequence PTA0 AD0 → TCH0 → KBI0 → PTA0 PTA1 AD1 →TCH1 → KBI1 → PTA1 PTA2 IRQ → KBI2 → TCLK → PTA2 PTA3 RST → KBI3 → PTA3 PTA4 OSC2 → AD2 → KBI4 → PTA4 PTA5 OSC1 → AD3 → KBI5 → PTA5

MC68HLC908QY/QT Family Data Sheet, Rev. 3

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 23 Chapter 2 Memory

2.1 Introduction

The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:  4096 bytes of user FLASH for MC68HLC908QT4 and MC68HLC908QY4  1536 bytes of user FLASH for MC68HL C908QT2, MC68HLC908QT1, MC68HLC908QY2, and MC68HLC908QY1  128 bytes of random access memory (RAM)  48 bytes of user-defined vectors, located in FLASH  416 bytes of monitor read-only memory (ROM)  1536 bytes of FLASH program and erase routines, located in ROM

2.2 Unimplemented Memory Locations

Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, unimplemented locations are shaded.

2.3 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.

MC68HLC908QY/QT Family Data Sheet, Rev. 3

24 Freescale Semiconductor

$0000 $003F I/O REGISTERS

64 BYTES

Note 1. Attempts to execute code from addresses in this range will generate an illegal address reset. $0040 $007F RESERVED(1) $0080 $00FF RAM

128 BYTES

$0100 $27FF UNIMPLEMENTED(1)

9984 BYTES

$2800 $2DFF AUXILIARY ROM $2E00 $EDFF UNIMPLEMENTED(1)

49152 BYTES UNIMPLEMENTED

51712 BYTES

$2E00 $F7FF $EE00 $FDFF FLASH MEMORY MC68HLC908QT4 AND MC68HLC908QY4 $F800 $FDFF $FE00 BREAK STATUS REGISTER (BSR) MC68HLC908QT1, MC68HLC908QT2, MC68HLC908QY1, and MC68HLC908QY2 Memory Map $FE01 RESET STATUS REGISTER (SRSR) $FE02 BREAK AUXILIARY REGISTER (BRKAR) $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR) $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 BREAK ADDRESS HIGH REGISTER (BRKH) $FE0A BREAK ADDRESS LOW REGISTER (BRKL) $FE0B BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0C LVISR $FE0D $FE0F RESERVED FOR FLASH TEST

3 BYTES

$FE10 $FFAF MONITOR ROM 416 BYTES $FFB0 $FFBD FLASH

14 BYTES

$FFBE FLASH BLOCK PROTECT REGISTER (FLBPR) $FFBF RESERVED FLASH $FFC0 INTERNAL OSCILLATOR TRIM VALUE $FFC1 RESERVED FLASH $FFC2 $FFCF FLASH $FFD0 $FFFF USER VECTORS

48 BYTES

Figure 2-1. Memory Map

Input/Output (I/O) Section MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 25

2.4 Input/Output (I/O) Section

Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses:  $FE00 — Break status register, BSR  $FE01 — Reset status register, SRSR  $FE02 — Break auxiliary register, BRKAR  $FE03 — Break flag control register, BFCR  $FE04 — Interrupt status register 1, INT1  $FE05 — Interrupt status register 2, INT2  $FE06 — Interrupt status register 3, INT3 $ F E 0 7 — R e s e r v e d  $FE08 — FLASH control register, FLCR  $FE09 — Break address register high, BRKH  $FE0A — Break address register low, BRKL  $FE0B — Break status and control register, BRKSCR  $FE0C — LVI status register, LVISR $ F E 0 D — R e s e r v e d  $FFBE — FLASH block protect register, FLBPR  $FFC0 — Internal OSC trim value — Optional  $FFFF — COP control register, COPCTL A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 $0000 Port A Data Register (PTA) See page 98. Read: R AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: Unaffected by reset $0001 Port B Data Register (PTB) See page 100. Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write: Reset: Unaffected by reset $0002 Unimplemented $0003 Unimplemented $0004 Data Direction Register A (DDRA) See page 98. Read: R R DDRA5 DDRA4 DDRA3 DDRA1 DDRA0 Write: R e s e t : 00000000 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)

MC68HLC908QY/QT Family Data Sheet, Rev. 3

26 Freescale Semiconductor

$0005 Data Direction Register B (DDRB) See page 101. Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write: R e s e t : 00000000 $0006 $000A Unimplemented $000B Port A Input Pullup Enable Register (PTAPUE) See page 99. Read: OSC2EN PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Write: R e s e t : 00000000 $000C Port B Input Pullup Enable Register (PTBPUE) See page 102. Read: PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0 Write: R e s e t : 00000000 $000D $0019 Unimplemented $001A Keyboard Status and Control Register (KBSCR) See page 83. R e a d : 0000 K E Y F 0 IMASKK MODEK Write: ACKK R e s e t : 00000000 $001B Keyboard Interrupt Enable Register (KBIER) See page 84. Read: 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write: R e s e t : 00000000 $001C Unimplemented $001D IRQ Status and Control Register (INTSCR) See page 77. R e a d : 0000 I R Q F 0 IMASK MODE Write: ACK R e s e t : 00000000 $001E Configuration Register 2 (CONFIG2)(1) See page 53. Read: IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN Write: R e s e t : 0000000 0 (2) 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 6)

Input/Output (I/O) Section MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 27 $001F Configuration Register 1 (CONFIG1)(1) See page 54. Read: COPRS LVISTOP LVIRSTD LVIPWRD LVDLVR SSREC STOP COPD Write: R e s e t : 0000 0 (2) 000 1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits. 2. LVDLVR reset to 0 by a power-on reset (POR) only. $0020 TIM Status and Control Register (TSC) See page 127. Read: TOF TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST R e s e t : 00100000 $0021 TIM Counter Register High (TCNTH) See page 129. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: R e s e t : 00000000 $0022 TIM Counter Register Low (TCNTL) See page 129. R e a d : B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: R e s e t : 00000000 $0023 TIM Counter Modulo Register High (TMODH) See page 129. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: R e s e t : 11111111 $0024 TIM Counter Modulo Register Low (TMODL) See page 129. Read: B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: R e s e t : 11111111 $0025 TIM Channel 0 Status and Control Register (TSC0) See page 130. Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write: 0 R e s e t : 00000000 $0026 TIM Channel 0 Register High (TCH0H) See page 133. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Indeterminate after reset $0027 TIM Channel 0 Register Low (TCH0L) See page 133. Read: B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: Reset: Indeterminate after reset $0028 TIM Channel 1 Status and Control Register (TSC1) See page 130. Read: CH1F CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: 0 R e s e t : 00000000 A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)

MC68HLC908QY/QT Family Data Sheet, Rev. 3

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$0029 TIM Channel 1 Register High (TCH1H) See page 133. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Indeterminate after reset $002A TIM Channel 1 Register Low (TCH1L) See page 133. Read: B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: Reset: Indeterminate after reset $002B $0035 Unimplemented $0036 Oscillator Status Register (OSCSTAT) See page 95. Read: RRRRRR E C G O N ECGST Write: R e s e t : 00000000 $0037 Unimplemented Read: $0038 Oscillator Trim Register (OSCTRIM) See page 96. Read: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 Write: R e s e t : 10000000 $0039 $003B Unimplemented $003C ADC Status and Control Register (ADSCR) See page 43. Read: COCO AIEN ADCO CH4 CH3 CH2 CH1 CH0 Write: R R e s e t : 00011111 $003D Unimplemented $003E ADC Data Register (ADR) See page 44. Read: B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: Reset: Indeterminate after reset $003F ADC Input Clock Register (ADICLK) See page 45. Read: ADIV2 ADIV1 ADIV0 00000 Write: R e s e t : 00000000 A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)

Input/Output (I/O) Section MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 29 $FE00 Break Status Register (BSR) See page 139. Read: RRRRRR SBSW R Write: See note 1 Reset: 0 1. Writing a 0 clears SBSW. $FE01 SIM Reset Status Register (SRSR) See page 117. Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: P O R : 10000000 $FE02 Break Auxiliary Register (BRKAR) See page 139. R e a d : 0000000 BDCOP Write: R e s e t : 00000000 $FE03 Break Flag Control Register (BFCR) See page 139. Read: B C F E RRRRRRR Write: Reset: 0 $FE04 Interrupt Status Register 1 (INT1) See page 77. Read: 0 IF5 IF4 IF3 0 IF1 0 0 W r i t e : RRRRRRRR R e s e t : 00000000 $FE05 Interrupt Status Register 2 (INT2) See page 77. R e a d : I F 1 4 0000000 W r i t e : RRRRRRRR R e s e t : 00000000 $FE06 Interrupt Status Register 3 (INT3) See page 77. R e a d : 0000000 I F 1 5 W r i t e : RRRRRRRR R e s e t : 00000000 $ F E 0 7 R e s e r v e d RRRRRRRR $FE08 FLASH Control Register (FLCR) See page 32. R e a d : 0000 HVEN MASS ERASE PGM Write: R e s e t : 00000000 $FE09 Break Address High Register (BRKH) See page 138. Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: R e s e t : 00000000 $FE0A Break Address low Register (BRKL) See page 138. Read: B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Write: R e s e t : 00000000 A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)

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$FE0B Break Status and Control Register (BRKSCR) See page 138. Read: BRKE BRKA 000000 Write: R e s e t : 00000000 $FE0C LVI Status Register (LVISR) See page 87. R e a d : L V I O U T 000000R Write: R e s e t : 00000000 $FE0D $FE0F R e s e r v e d f o r F L A S H T e s t RRRRRRRR $FFBE FLASH Block Protect Register (FLBPR) See page 37. Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write: Reset: Unaffected by reset $ F F B F R e s e r v e d RRRRRRRR $FFC0 Internal Oscillator Trim Value (Optional) Read: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 Write: Reset: Unaffected by reset $ F F C 1 R e s e r v e d RRRRRRRR $FFFF COP Control Register (COPCTL) See page 59. Read: LOW BYTE OF RESET VECTOR Write: WRITING CLEARS COP COUNTER (ANY VALUE) Reset: Unaffected by reset A d d r . R e g i s t e r N a m e B i t 7 654321 B i t 0 = Unimplemented R = Reserved U = Unaffected Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)

Random-Access Memory (RAM) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 31

2.5 Random-Access Memory (RAM)

The 128 bytes of random-access memory (RAM) are located at addresses $0080–$00FF. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805, M146805, and M68HC05 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Table 2-1. Vector Addresses Vector Priority Ve ctor Address Vector Lowest Highest IF15 $FFDE ADC conversion complete vector (high) $FFDF ADC conversion complete vector (low) IF14 $FFE0 Keyboard vector (high) $FFE1 Keyboard vector (low) IF13 IF6 — Not used IF5 $FFF2 TIM overflow vector (high) $FFF3 TIM overflow vector (low) IF4 $FFF4 TIM Channel 1 vector (high) $FFF5 TIM Channel 1 vector (low) IF3 $FFF6 TIM Channel 0 vector (high) $FFF7 TIM Channel 0 vector (low) IF2 — Not used IF1 $FFFA IRQ vector (high) $FFFB IRQ vector (low) $FFFC SWI vector (high) $FFFD SWI vector (low) $FFFE Reset vector (high) $FFFF Reset vector (low)

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2.6 FLASH Memory (FLASH)

This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are:  $EE00 – $FDFF; user memory, 4096 by tes: MC68HLC908QY4 and MC68HLC908QT4  $F800 – $FDFF; user memory, 1536 bytes: MC68HLC908QY2, MC68HLC908QT2, MC68HLC908QY1 and MC68HLC908QT1  $FFD0 – $FFFF; user interrupt vectors, 48 bytes. NOTE An erased bit reads as a 1 and a programmed bit reads as a 0. A security feature prevents viewing of the FLASH contents. (1)

2.6.1 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase operations. HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Address: $FE08 B i t 7 654321 B i t 0 R e a d : 0000 HVEN MASS ERASE PGM Write: R e s e t : 00000000 = Unimplemented Figure 2-3. FLASH Control Register (FLCR)

FLASH Memory (FLASH) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 33 MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation. 1 = Mass Erase operation selected 0 = Mass Erase operation unselected ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected

2.6.2 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the block to be erased. 4. Wait for a time, t NVS (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, t Erase (minimum 1 ms or 4 ms). 7. Clear the ERASE bit. 8. Wait for a time, t NVH (minimum 5 µs). 9. Clear the HVEN bit. 10. After time, t RCV (typical 1 µs), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. CAUTION A page erase of the vector page will erase the internal oscillator trim value at $FFC0. In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.

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2.6.3 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address (1) within the FLASH memory address range. 4. Wait for a time, t NVS (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, t MErase (minimum 4 ms). 7. Clear the ERASE and MASS bits. NOTE Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). 8. Wait for a time, t NVH (minimum 100 µs). 9. Clear the HVEN bit. 10. After time, t RCV (typical 1 µs), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. CAUTION A mass erase will erase the internal oscillator trim value at $FFC0.

2.6.4 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a row of FLASH memory Figure 2-4 shows a flowchart of the programming algorithm. NOTE Only bytes which are currently $FF may be programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4. Wait for a time, t NVS (minimum 10 µs). 5. Set the HVEN bit. 6. Wait for a time, t PGS (minimum 5 µs). 7. Write data to the FLASH address being programmed (2). 1. When in monitor mode, with security sequence failed (see 15.3.2 Security), write to the FLASH block protect register instead of any FLASH address. 2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG maximum.

FLASH Memory (FLASH) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 35 8. Wait for time, t PROG (minimum 30 µs). 9. Repeat step 7 and 8 until all desir ed bytes within the row are programmed. 10. Clear the PGM bit (1). 11. Wait for time, t NVH (minimum 5 µs). 12. Clear the HVEN bit. 13. After time, t RCV (typical 1 µs), the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set. This program sequence is repeated throughout the memory until all data is programmed. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t PROG maximum, see 16.12 Memory Characteristics.

2.6.5 FLASH Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. NOTE In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. When the FLBPR is programmed with all 0s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1s), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, V TST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode.

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Figure 2-4. FLASH Programming Flowchart SET HVEN BIT WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED WAIT FOR A TIME, tNVS SET PGM BIT WAIT FOR A TIME, tPGS WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG CLEAR PGM BIT WAIT FOR A TIME, tNVH CLEAR HVEN BIT WAIT FOR A TIME, tRCV COMPLETED PROGRAMMING THIS ROW? Y N END OF PROGRAMMING The time between each FLASH address change (step 7 to step 7), must not exceed the maximum programming time, tPROG max. or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) NOTES: Algorithm for Programming a Row (32 Bytes) of FLASH Memory This row program algorithm assumes the row/s to be programmed are initially erased. READ THE FLASH BLOCK PROTECT REGISTER2

FLASH Memory (FLASH) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 37

2.6.6 FLASH Block Protect Register

The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. BPR[7:0] — FLASH Protection Register Bits [7:0] These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. See Figure 2-6 and Table 2-2. Figure 2-6. FLASH Block Protect Start Address Address: $FFBE B i t 7 654321 B i t 0 Read: BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Write: Reset: Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory. Figure 2-5. FLASH Block Protect Register (FLBPR) Table 2-2. Examples of Protect Start Address BPR[7:0] Start of Address of Protect Range $00–$B8 The entire FLASH memory is protected. $B9 (1011 1001) $EE40 (11 10 1110 0100 0000) $BA (1011 1010) $EE80 (11 10 1110 1000 0000) $BB (1011 1011) $EEC0 (11 10 1110 1100 0000) $BC (1011 1100)$ E F 0 0 ( 1 1 10 1111 0000 0000) and so on... $DE (1101 1110) $F780 (11 11 0111 1000 0000) $DF (1101 1111)$ F 7 C 0 ( 1 1 11 0111 1100 0000) $FE (1111 1110) $FF80 (1111 1111 1000 0000) FLBPR, OSCTRIM, and vectors are protected $FF The entire FLASH memory is not protected.

0000011 FLBPR VALUESTART ADDRESS OF

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2.6.7 Wait Mode

Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode.

2.6.8 Stop Mode

Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The STOP instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode NOTE Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 39 Chapter 3 Analog-to-Digital Converter (ADC)

3.1 Introduction

This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to- digital converter. The ADC module is only available on the MC68HLC908QY2, MC68HLC908QT2, MC68HLC908QY4, and MC68HLC908QT4.

3.2 Features

Features of the ADC module include:  4 channels with multiplexed input  Linear successive approxi mation with monotonicity  8-bit resolution  Single or continuous conversion  Conversion complete flag or conversion complete interrupt  Selectable ADC clock frequency

3.3 Functional Description

Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 3-2 shows a block diagram of the ADC.

3.3.1 ADC Port I/O Pins

PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is at 0. If the DDR bit is 1, the value in the port data latch is read.

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Figure 3-1. Block Diagram Highlighting ADC Block and Pins PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4( see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 41 Figure 3-2. ADC Block Diagram

3.3.2 Voltage Conversion

When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE Input voltage should not exceed the analog supply voltages. INTERNAL DATA BUS INTERRUPT LOGIC CHANNEL SELECTADC CLOCK GENERATOR CONVERSION COMPLETE ADC VOLTAGE IN ADCVIN ADC CLOCK BUS CLOCK CH[4:0] ADC DATA REGISTER ADIV[2:0] AIEN COCO DISABLE DISABLE ADC CHANNEL x READ DDRA WRITE DDRA RESET WRITE PTA READ PTA DDRAx PTAx (1 OF 4 CHANNELS) ADCx

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3.3.3 Conversion Time

Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC internal clock the maximum sample rate is 62.5 kHz.

3.3.4 Continuous Conversion

In the continuous conversion mode (ADCO = 1), the ADC continuously converts the selected channel filling the ADC data register (ADR) with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until the next read of the ADC data register. When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading.

3.3.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.

3.4 Interrupts

When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.

3.5 Low-Power Modes

The following subsections describe the ADC in low-power modes.

3.5.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the microcontroller unit (MCU) out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction.

3.5.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before using ADC data after exiting stop mode.

16 ADC Clock CyclesConversion Time =

Number of Bus Cycles = Conversion Time × Bus Frequency

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 43

3.6 Input/Output Signals

The ADC module has four channels that are shared with I/O port A. ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC module.

3.7 Input/Output Registers

These I/O registers control and monitor ADC operation:  ADC status and control register (ADSCR)  ADC data register (ADR)  ADC clock register (ADICLK)

3.7.1 ADC Status and Control Register

The following paragraphs describe the function of the ADC status and control register (ADSCR). When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading. COCO — Conversions Complete Bit In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a 0. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) NOTE The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO bit position. AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update ADR at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion Address: $003C B i t 7 654321 B i t 0 Read: COCO AIEN ADCO CH4 CH3 CH2 CH1 CH0 Write: R R e s e t : 00011111 R= R e s e r v e d Figure 3-3. ADC Status and Control Register (ADSCR)

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CH[4:0] — ADC Channel Select Bits CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels. The five select bits are detailed in Table 3-1. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a 1. NOTE Recovery from the disabled state requires one conversion cycle to stabilize.

3.7.2 ADC Data Register

One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Table 3-1. MUX Channel Select CH4 CH3 CH2 CH1 CH0 ADC Channel Input Select

00000 A D 0 P T A 0

00001 A D 1 P T A 1

00010 A D 2 P T A 4

00011 A D 3 P T A 5

00100 — Unused (1) 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 11010 — 11011 — R e s e r v e d 1 0 0 — Unused 11 1 0 1— VDDA (2) 2. The voltage levels supplied from internal reference nodes, as specified in the table, are used to verify the operation of the ADC converter both in production test and for user applications. 11 1 1 0— VSSA (2) 11 1 1 1— ADC power off Address: $003E B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: Reset: Indeterminate after reset Figure 3-4. ADC Data Register (ADR)

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3.7.3 ADC Input Clock Register

This register selects the clock frequency for the ADC. ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set according to the MCU operating voltage. Lower operating voltages will require lower ADC clock frequencies for best accuracy. The analog input level should remain stable for the entire conversion time (maximum = 17 ADC clock cycles). Address: $003F B i t 7 654321 B i t 0 Read: ADIV2 ADIV1 ADIV0 00000 Write: R e s e t : 00000000 = Unimplemented Figure 3-5. ADC Input Clock Register (ADICLK) Table 3-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 Bus clock ÷ 1 0 0 1 Bus clock ÷ 2 0 1 0 Bus clock ÷ 4 0 1 1 Bus clock ÷ 8

1 X X Bus clock ÷ 16

X = don’t care

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 47 Chapter 4 Auto Wakeup Module (AWU)

4.1 Introduction

This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU.

4.2 Features

Features of the auto wakeup module include:  One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit  Exit from low-power stop mode without external signals  Selectable timeout periods  Dedicated low power internal oscillator s eparate from the main system clock sources

4.3 Functional Description

The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input (see Figure 4-1). A logic 1 applied to the AWUIREQ input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request. Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data register (PTA). This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data direction or PTA6 pullup exist for this bit. Entering stop mode will enable the auto wakeup generation logic. An internal RC oscillator (exclusive for the auto wakeup feature) drives the wakeup request generator. Once the overflow count is reached in the generator counter, a wakeup request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1. Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector.

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Figure 4-1. Auto Wakeup Interrupt Request Generation Logic The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was “borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no MCU clock available) in stop mode. The typical values of the periodic wakeup request are (at room temperature):  COPRS = 0: 875 ms @ 3.0 V, 1.1 s @ 2.3 V  COPRS = 1: 22 ms @ 3.0 V, 27 ms @ 2.3 V The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is not recommended for use as a time-keeping function. The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6 pullup exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register. Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-1) has no effect on AWUL reading. The AWU oscillator and counters are inactive in normal operating mode and become active only upon entering stop mode. D R VDD INT RC OSC EN 32 kHz CLK RST OVERFLOW AUTOWUGEN SHORT COPRS (FROM CONFIG1) 1 = DIV 29 0 = DIV 214 E RESET ACKK CLEAR RST RESET CLK(CGMXCLK) BUSCLKX4 ISTOP AWUIREQ CLRLOGIC RESET AWUL TO PTA READ, BIT 6 Q AWUIE TO KBI INTERRUPT LOGIC (SEE Figure 9-2. Keyboard Interrupt Block Diagram)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 49

4.4 Wait Mode

The AWU module remains inactive in wait mode.

4.5 Stop Mode

When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start from ‘0’ each time stop mode is entered.

4.6 Input/Output Registers

The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The following I/O registers control and monitor operation of the AWU:  Port A data register (PTA)  Keyboard interrupt status and control register (KBSCR)  Keyboard interrupt enable register (KBIER)

4.6.1 Port A I/O Register

The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition to the data latches for port A. AWUL — Auto Wakeup Latch This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally. There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits. 1 = Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending NOTE PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 12.2.1 Port A Data Register. Address: $0000 B i t 7 654321 B i t 0 Read: 0 AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: 0 0 Unaffected by reset = Unimplemented Figure 4-2. Port A Data Register (PTA)

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4.6.2 Keyboard Status and Control Register

The keyboard status and control register (KBSCR):  Flags keyboard/auto wakeup interrupt requests  Acknowledges keyboard/auto wakeup interrupt requests  Masks keyboard/auto wakeup interrupt requests Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard/auto wakeup interrupt pending 0 = No keyboard/auto wakeup interrupt pending ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit. 1 = Keyboard/auto wakeup interrupt requests masked 0 = Keyboard/auto wakeup interrupt requests not masked NOTE MODEK is not used in conjuction with the auto wakeup feature. To see a description of this bit, see 9.7.1 Keyboard Status and Control Register. Address: $001A B i t 7 654321 B i t 0 R e a d : 0000 K E Y F 0 IMASKK MODEK Write: ACKK R e s e t : 00000000 = Unimplemented Figure 4-3. Keyboard Status and Control Register (KBSCR)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 51

4.6.3 Keyboard Interrupt Enable Register

The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input. AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE. 1 = Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input NOTE KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9.7.2 Keyboard Interrupt Enable Register. Address: $001B B i t 7 654321 B i t 0 Read: 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Write: R e s e t : 00000000 = Unimplemented Figure 4-4. Keyboard Interrupt Enable Register (KBIER)

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 53 Chapter 5 Configuration Register (CONFIG)

5.1 Introduction

This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options:  Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles) S T O P i n s t r u c t i o n  Computer operating properly module (COP)  COP reset period (COPRS): 8176 × BUSCLKX4 or 262,128 × BUSCLKX4  Low-voltage inhibit (LVI) enable and trip voltage selection  OSC option selection I R Q pin R S T pin  Auto wakeup timeout period

5.2 Functional Description

The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. Exceptions are bits LVDLVR and LVIRSTD which may be written at any time. Most of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU) it is recommended that this register be written immediately after reset. The configuration registers are located at $001E and $001F, and may be read at anytime. Address: $001E B i t 7 6 54 32 1 B i t 0 Read: IRQPUD IRQEN R OSCOPT1 OSCOPT0 R R RSTEN Write: R e s e t : 000 0 0 00U P O R : 000 0 0 000 R = Reserved U = Unaffected Figure 5-1. Configuration Register 2 (CONFIG2)

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IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option (0, 0) Internal oscillator (0, 1) External oscillator (1, 0) External RC oscillator (1, 1) External XTAL oscillator RSTEN — RST Pin Function Selection 1 = Reset function active in pin 0 = Reset function inactive in pin NOTE The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. COPRS (Out of STOP Mode) — COP Reset Period Selection Bit 1 = COP reset short cycle = 8176 × BUSCLKX4 0 = COP reset long cycle = 262,128 × BUSCLKX4 COPRS (In STOP Mode) — Auto Wakeup Period Selection Bit 1 = Auto wakeup short cycle = 512 × INTRCOSC 0 = Auto wakeup long cycle = 16,384 × INTRCOSC LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD — LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. Unlike other configuration bits, the LVIRSTD can be written at any time. 1 = LVI module resets disabled 0 = LVI module resets enabled Address: $001F Bit 7 6 5 4 3 2 1 Bit 0 Read: COPRS LVISTOP LVIRSTD LVIPWRD LVDLVR SSREC STOP COPD Write: R e s e t : 0000U000 POR: 00000000 U = Unaffected Figure 5-2. Configuration Register 1 (CONFIG1)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 55 LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used as a low voltage warning, while LVR will commonly be used as a reset condition. Unlike other CONFIG bits, LVDLVR can be written multiple times after reset. 1 = LVI trip voltage level set to LVD trip voltage 0 = LVI trip voltage level set to LVR trip voltage NOTE The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay. 1 = Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles NOTE Exiting stop mode by an LVI reset will result in the long stop recovery. The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the MCU is not protected from a low-power condition. However, when using the short stop recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to avoid a period in startup where the LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 57 Chapter 6 Computer Operating Properly (COP)

6.1 Introduction

The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register.

6.2 Functional Description

Figure 6-1. COP Block Diagram COPCTL WRITE BUSCLKX4 RESET CIRCUIT RESET STATUS REGISTER INTERNAL RESET SOURCES 12-BIT SIM COUNTERCLEAR ALL STAGES 6-BIT COP COUNTER COP DISABLE (COPD FROM CONFIG1) RESET COPCTL WRITE CLEAR COPEN (FROM SIM) COP COUNTER COP CLOCK COP TIMEOUT STOP INSTRUCTION COP RATE SELECT (COPRS FROM CONFIG1) CLEAR STAGES 5–12

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The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 4.0-MHz oscillator gives a COP timeout period of 65.53 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter. NOTE Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register. NOTE Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.

6.3 I/O Signals

The following paragraphs describe the signals shown in Figure 6-1.

6.3.1 BUSCLKX4

BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the internal oscillator frequency, crystal frequency, or the RC-oscillator frequency.

6.3.2 STOP Instruction

The STOP instruction clears the SIM counter.

6.3.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP counter and clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.

6.3.4 Power-On Reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096× BUSCLKX4 cycles after power up.

6.3.5 Internal Reset

An internal reset clears the SIM counter and the COP counter.

6.3.6 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG).

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 59

6.3.7 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG).

6.4 COP Control Register

The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.

6.5 Interrupts

The COP does not generate CPU interrupt requests.

6.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin.

6.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

6.7.1 Wait Mode

The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter.

6.7.2 Stop Mode

Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.

6.8 COP Module During Break Mode

The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). Address: $FFFF B i t 7 654321 B i t 0 Read: LOW BYTE OF RESET VECTOR Write: CLEAR COP COUNTER Reset: Unaffected by reset Figure 6-2. COP Control Register (COPCTL)

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 61 Chapter 7 Central Processor Unit (CPU)

7.1 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

7.2 Features

Features of the CPU include:  Object code fully upward-compatible with M68HC05 Family  16-bit stack pointer with stack manipulation instructions  16-bit index register with x-re gister manipulation instructions  8-MHz CPU internal bus frequency  64-Kbyte program/data memory space  16 addressing modes  Memory-to-memory data moves without using accumulator  Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions  Enhanced binary-coded decimal (BCD) data handling  Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes  Low-power stop and wait modes

7.3 CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.

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Figure 7-1. CPU Registers

7.3.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.

7.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. B i t 7 654321 B i t 0 Read: Write: Reset: Unaffected by reset Figure 7-2. Accumulator (A) Bit 1 5 1 4 1 3 1 2 1 1 1 0 987654321 Bit Read: Write: R e s e t : 00000000 XXXXXXXX X = Indeterminate Figure 7-3. Index Register (H:X) ACCUMULATOR (A) INDEX REGISTER (H:X) STACK POINTER (SP) PROGRAM COUNTER (PC) CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG V11HINZC H X

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7.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.

7.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 1 5 1 4 1 3 1 2 1 1 1 0 987654321 Bit Read: Write: R e s e t : 0000000011111111 Figure 7-4. Stack Pointer (SP) Bit 1 5 1 4 1 3 1 2 1 1 1 0 987654321 Bit Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 7-5. Program Counter (PC)

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7.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. V — Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result B i t 7 654321 B i t 0 Read: V11HINZC Write: R e s e t : X11X1XXX X = Indeterminate Figure 7-6. Condition Code Register (CCR)

Arithmetic/Logic Unit (ALU) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 65 Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7

7.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

7.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

7.5.1 Wait Mode

The WAIT instruction:  Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.  Disables the CPU clock

7.5.2 Stop Mode

The STOP instruction:  Clears the interrupt mask (I bit) in the conditi on code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.  Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

7.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:  Loading the instruction register with the SWI instruction  Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.

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7.7 Instruction Set Summary

Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet 1 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP Add with Carry A ← (A) + (M) + (C) – IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE9 9ED9 ii dd hh ll ee ff ff ff ee ff ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP Add without Carry A ← (A) + (M) – IMM DIR EXT IX2 IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ff ee ff AIS # opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) –––––– I M M A 7 i i 2 AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) –––––– I M M A F i i 2 AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP Logical AND A ← (A) & (M) 0 – – – IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP Arithmetic Shift Left (Same as LSL) –– DIR INH INH IX1 IX SP1 9E68 dd ff ff ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP Arithmetic Shift Right –– DIR INH INH IX1 IX SP1 9E67 dd ff ff BCC rel Branch if Carry Bit Clear PC ← ( P C ) + 2 + r e l ? ( C ) = 0 –––––– R E L 2 4 r r 3 BCLR n, opr Clear Bit n in M Mn ← 0 –––––– DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? ( C ) = 1 –––––– R E L 2 5 r r 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? ( Z ) = 1 –––––– R E L 2 7 r r 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (N BGT opr Branch if Greater Than (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 –––––– R E L 9 2 r r 3 BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? ( H ) = 0 –––––– R E L 2 8 r r 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? ( H ) = 1 –––––– R E L 2 9 r r 3 BHI rel Branch if Higher PC ← (PC) + 2 + rel ? ( C ) | ( Z ) = 0 –––––– R E L 2 2 r r 3 C b0b7 b0b7 C

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 67 BHS rel Branch if Higher or Same (Same as BCC) PC ← (PC) + 2 + rel ? ( C ) = 0 –––––– R E L 2 4 r r 3 BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 –––––– R E L 2 F r r 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 –––––– R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test (A) & (M) 0 – – – IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE5 9ED5 ii dd hh ll ee ff ff ff ee ff BLE opr Branch if Less Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? ( C ) = 1 –––––– R E L 2 5 r r 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? ( C ) | ( Z ) = 1 –––––– R E L 2 3 r r 3 BLT opr Branch if Less Than (Signed Operands)PC ← (PC) + 2 + rel ? (N ⊕ V) =1 –––––– R E L 9 1 r r 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? ( I ) = 0 –––––– R E L 2 C r r 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? ( N ) = 1 –––––– R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? ( I ) = 1 –––––– R E L 2 D r r 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? ( Z ) = 0 –––––– R E L 2 6 r r 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? ( N ) = 0 –––––– R E L 2 A r r 3 BRA rel Branch Always PC ← (PC) + 2 + rel –––––– R E L 2 0 r r 3 BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? ( M n ) = 0 ––––– DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← ( P C ) + 2 –––––– R E L 2 1 r r 3 BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 + DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BSET n,opr Set Bit n in M Mn ← 1 –––––– DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel Compare and Branch if Equal DIR IMM IMM IX1+ IX+ SP1 9E61 dd rr ii rr ii rr ff rr rr ff rr CLC Clear Carry Bit C ← 0 –––––0 I N H 9 8 1 CLI Clear Interrupt Mask I ← 0 ––0––– I N H 9 A 2 Table 7-1. Instruction Set Summary (Sheet 2 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC

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CLR opr,X CLR ,X CLR opr,SP Clear M ← $00 A ← $00 X ← $00 H ← $00 M ← $00 M ← $00 M ← $00 0––01– DIR INH INH INH IX1 IX SP1 9E6F dd ff ff CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Compare A with M (A) – (M) –– IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff COM opr COMA COMX COM opr,X COM ,X COM opr,SP Complement (One’s Complement) M ← (M ) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) 0–– 1 DIR INH INH IX1 IX SP1 9E63 dd ff ff CPHX #opr CPHX opr Compare H:X with M (H:X) – (M:M + 1) –– IMM DIR ii ii+1 dd CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M (X) – (M) –– IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE3 9ED3 ii dd hh ll ee ff ff ff ee ff DAA Decimal Adjust A (A)

10 U–– INH 72 2

DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel Decrement and Branch if Not Zero PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0 DIR INH INH IX1 IX SP1 9E6B dd rr rr rr ff rr rr ff rr DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 M ← (M) – 1 –– – DIR INH INH IX1 IX SP1 9E6A dd ff ff DIV Divide A ← (H:A)/(X) H ← Remainder –––– INH 52 7 EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP Exclusive OR M with A A ← (A ⊕ M) 0–– – IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff INC opr INCA INCX INC opr,X INC ,X INC opr,SP Increment M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 M ← (M) + 1 –– – DIR INH INH IX1 IX SP1 9E6C dd ff ff Table 7-1. Instruction Set Summary (Sheet 3 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 69 JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Jump PC ← J u m p A d d r e s s –––––– DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP Load A from M A ← ( M ) 0–– – IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff LDHX #opr LDHX opr Load H:X from M H:X ← (M:M + 1) 0–– – IMM DIR ii jj dd LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP Load X from M X ← ( M ) 0–– – IMM DIR EXT IX2 IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE ii dd hh ll ee ff ff ff ee ff LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP Logical Shift Left (Same as ASL) –– DIR INH INH IX1 IX SP1 9E68 dd ff ff LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Logical Shift Right ––0 DIR INH INH IX1 IX SP1 9E64 dd ff ff MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr Move (M) Destination ← (M)Source H:X ← (H:X) + 1 (IX+D, DIX+) 0–– – DD DIX+ IMD IX+D dd dd dd ii dd dd MUL Unsigned multiply X:A ← (X) × ( A ) –0–––0 I N H 4 2 5 NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP Negate (Two’s Complement) DIR INH INH IX1 IX SP1 9E60 dd ff ff N O P N o O p e r a t i o n N o n e –––––– I N H 9 D 1 NSA Nibble Swap A A ← ( A [ 3 : 0 ] : A [ 7 : 4 ] ) –––––– I N H 6 2 3 ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP Inclusive OR A and M A ← (A) | (M) 0 – – – IMM DIR EXT IX2 IX1 IX SP1 SP2 AA BA CA DA EA FA 9EEA 9EDA ii dd hh ll ee ff ff ff ee ff PSHA Push A onto Stack Push (A); SP ← ( S P ) – 1 –––––– I N H 8 7 2 PSHH Push H onto Stack Push (H); SP ← ( S P ) – 1 –––––– I N H 8 B 2 PSHX Push X onto Stack Push (X); SP ← ( S P ) – 1 –––––– I N H 8 9 2 Table 7-1. Instruction Set Summary (Sheet 4 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC C b0b7 b0b7

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PULA Pull A from Stack SP ← (SP + 1); Pull (A) –––––– I N H 8 6 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) –––––– I N H 8 A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) –––––– I N H 8 8 2 ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP Rotate Left through Carry –– DIR INH INH IX1 IX SP1 9E69 dd ff ff ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP Rotate Right through Carry –– DIR INH INH IX1 IX SP1 9E66 dd ff ff RSP Reset Stack Pointer SP ← $ F F –––––– I N H 9 C 1 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) INH 80 7 RTS Return from Subroutine SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL) –––––– I N H 8 1 4 SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP Subtract with Carry A ← (A) – (M) – (C) –– IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE2 9ED2 ii dd hh ll ee ff ff ff ee ff SEC Set Carry Bit C ← 1 –––––1 I N H 9 9 1 SEI Set Interrupt Mask I ← 1 ––1––– I N H 9 B 2 STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP Store A in M M ← ( A ) 0–– – DIR EXT IX2 IX1 IX SP1 SP2 9EE7 9ED7 dd hh ll ee ff ff ff ee ff STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4 STOP Enable Interrupts, Stop Processing, Refer to MCU Documentation I ← 0 ; S t o p P r o c e s s i n g ––0––– I N H 8 E 1 STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP Store X in M M ← ( X ) 0–– – DIR EXT IX2 IX1 IX SP1 SP2 BF CF DF EF FF 9EEF 9EDF dd hh ll ee ff ff ff ee ff SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Subtract A ← (A) – (M) –– IMM DIR EXT IX2 IX1 IX SP1 SP2 9EE0 9ED0 ii dd hh ll ee ff ff ff ee ff Table 7-1. Instruction Set Summary (Sheet 5 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC C b0b7 b0b7 C

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 71

7.8 Opcode Map

See Table 7-2. SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte TAP Transfer A to CCR CCR ← (A) INH 84 2 TAX Transfer A to X X ← ( A ) –––––– I N H 9 7 1 TPA Transfer CCR to A A ← ( C C R ) –––––– I N H 8 5 1 TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – – DIR INH INH IX1 IX SP1 9E6D dd ff ff TSX Transfer SP to H:X H:X ← ( S P ) + 1 –––––– I N H 9 5 2 TXA Transfer X to A A ← ( X ) –––––– I N H 9 F 1 TXS Transfer H:X to SP (SP) ← ( H : X ) – 1 –––––– I N H 9 4 2 WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Inhibit CPU clocking until interrupted ––0––– I N H 8 F 1 A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with pos t increment addressing mode rr Relati ve program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offs et addressing SP1 Stack pointer , 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct des tination addressing mode | Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode « Sign extend IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, pos t increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location Set or cleared N Negative bit — Not affected Table 7-1. Instruction Set Summary (Sheet 6 of 6) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesVH I NZC

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Central Processor Unit (CPU) Table 7-2. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX 0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F BRSET0 3D I R BSET0 2D I R BRA 2R E L NEG 2D I R NEGA 1I N H NEGX 1I N H NEG 2I X 1 NEG

3 SP1

4 SP2

4 SP1

A BRSET5 3D I R BSET5 2D I R BPL 2R E L DEC 2D I R DECA 1I N H DECX 1I N H DEC 2I X 1 DEC B BRCLR5 3D I R BCLR5 2D I R BMI 2R E L DBNZ 3D I R DBNZA 2I N H DBNZX 2I N H DBNZ 3I X 1 DBNZ C BRSET6 3D I R BSET6 2D I R BMC 2R E L INC 2D I R INCA 1I N H INCX 1I N H INC 2I X 1 INC D BRCLR6 3D I R BCLR6 2D I R BMS 2R E L TST 2D I R TSTA 1I N H TSTX 1I N H TST 2I X 1 TST E BRSET7 3D I R BSET7 2D I R BIL 2R E L MOV 3D D MOV 2D I X + MOV 3I M D MOV 2I X + D STOP 1I N H * LDX 2I M M LDX 2D I R LDX 3E X T LDX 3I X 2 LDX F BRCLR7 3D I R BCLR7 2D I R BIH 2R E L CLR 2D I R CLRA 1I N H CLRX 1I N H CLR 2I X 1 CLR INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment *Pre-byte for stack pointer indexed instructions

0 High Byte of Opcode in Hexadecimal

Low Byte of Opcode in Hexadecimal 0 BRSET0 3D I R Cycles Opcode Mnemonic Number of Bytes / Addressing Mode MSB LSB MSB LSB

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 73 Chapter 8 External Interrupt (IRQ)

8.1 Introduction

The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI), provides a maskable interrupt input.

8.2 Features

Features of the IRQ module include the following:  External interrupt pin, IRQ I R Q interrupt control bits  Programmable edge-only or edge and level interrupt sensitivity  Automatic interrupt acknowledge  Selectable internal pullup resistor

8.3 Functional Description

IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and PTA2 will assume the other shared functionalities. A one enables the IRQ function. A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request. Figure 8-2 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the following actions occurs:  IRQ vector fetch — An IRQ vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch.  Software clear — Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt status and control register (INTSCR).  Reset — A reset automatically clears the IRQ latch. The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in INTSCR controls the triggering sensitivity of the IRQ pin.

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Figure 8-1. Block Diagram Highlighting IRQ Block and Pins When set, the IMASK bit in INTSCR masks the IRQ interrupt request. A latched interrupt request is not presented to the interrupt priority logic unless IMASK is clear. NOTE The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including the IRQ interrupt request. A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch, software clear, or reset clears the IRQ latch. PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 75 Figure 8-2. IRQ Module Block Diagram

8.3.1 MODE = 1

If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the following actions must occur to clear the IRQ interrupt request:  Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.  IRQ vector fetch or software clear. An IRQ vect or fetch generates an interrupt acknowledge signal to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the IRQ vector address. The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order. The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Use the BIH or BIL instruction to read the logic level on the IRQ pin.

8.3.2 MODE = 0

If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by IMASK, which makes it useful in applications where polling is preferred. NOTE When using the level-sensitive interrupt trigger, avoid false IRQ interrupts by masking interrupt requests in the interrupt routine. ACK IMASK DQ CK CLR IRQ HIGH INTERRUPT TO MODE SELECT LOGIC IRQ LATCH REQUEST VDD MODE VOLTAGE DETECT SYNCHRO- NIZER IRQF TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER INTERNAL ADDRESS BUS RESET VDD INTERNAL PULLUP DEVICE IRQ IRQPUD

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8.4 Interrupts

The following IRQ source can generate interrupt requests:  Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.

8.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

8.5.1 Wait Mode

The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of wait mode.

8.5.2 Stop Mode

The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode.

8.6 IRQ Module During Break Interrupts

The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Chapter 13 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state), software can read and write registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit.

8.7 I/O Signals

The IRQ module shares its pin with the keyboard interrupt, input/output ports, and timer interface modules. NOTE When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to read the logic level on the IRQ pin. If the IRQ function is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless of the actual level on the pin. Conversely, when the IRQ function is enabled, bit 2 of the port A data register will always read a 0. When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 77

8.7.1 IRQ Input Pins (IRQ)

The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device.

8.8 Registers

The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See Chapter 5 Configuration Register (CONFIG). The INTSCR has the following functions:  Shows the state of the IRQ flag  Clears the IRQ latch  Masks the IRQ interrupt request  Controls triggering sensitivity of the IRQ interrupt pin IRQF — IRQ Flag This read-only status bit is set when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK — IRQ Interrupt Request Acknowledge Bit Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. IMASK — IRQ Interrupt Mask Bit Writing a 1 to this read/write bit disables the IRQ interrupt request. 1 = IRQ interrupt request disabled 0 = IRQ interrupt request enabled MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. 1 = IRQ interrupt request on falling edges and low levels 0 = IRQ interrupt request on falling edges only Address: $001D B i t 7 654321 B i t 0 R e a d : 0000 I R Q F 0 IMASK MODE Write: ACK R e s e t : 00000000 = Unimplemented Figure 8-3. IRQ Status and Control Register (INTSCR)

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 79 Chapter 9 Keyboard Interrupt Module (KBI)

9.1 Introduction

The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are accessible via the PTA0–PTA5 pins.

9.2 Features

Features of the keyboard interrupt module include:  Six keyboard interrupt pins with separate ke yboard interrupt enable bits and one keyboard interrupt mask  Software configurable pullup device if i nput pin is configured as input port bit  Programmable edge-only or edge and level interrupt sensitivity  Exit from low-power modes

9.3 Functional Description

The keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port A pins. These six pins can be enabled/disabled independently of each other.

9.3.1 Keyboard Operation

Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register (KBIER) independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pullup device irrespective of PTAPUEx bits in the port A input pullup enable register (see 12.2.3 Port A Input Pullup Enable Register). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.  If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one input because another input is still low, software can disable the latter input while it is low.  If the keyboard interrupt is falling edge and low-le vel sensitive, an interrupt request is present as long as any keyboard interrupt input is low.

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80 Freescale Semiconductor

Figure 9-1. Block Diagram Highlighting KBI Block and Pins PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 81 Figure 9-2. Keyboard Interrupt Block Diagram If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request:  Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt inputs. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the central processor unit (CPU) loads the program counter with the vector address at locations $FFE0 and $FFE1.  Return of all enabled keyboard interrupt input s to logic 1 — As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input, AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR or reset. The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt input stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. KBIE0 KBIE5 DQ CK CLR VDD MODEK IMASKKKEYBOARD INTERRUPT FF VECTOR FETCH DECODER ACKK INTERNAL BUS RESET KBI5 KBI0 SYNCHRONIZER KEYF KEYBOARD INTERRUPT REQUEST TO PULLUP ENABLE AWUIREQ(1) TO PULLUP ENABLE 1. For AWUGEN logic refer to Figure 4-1. Auto Wakeup Interrupt Request Generation Logic.

Keyboard Interrupt Module (KBI) MC68HLC908QY/QT Family Data Sheet, Rev. 3

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To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin.

9.3.2 Keyboard Initialization

When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.

9.4 Wait Mode

The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.

9.5 Stop Mode

The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.

9.6 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect.

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 83

9.7 Input/Output Registers

The following I/O registers control and monitor operation of the keyboard interrupt module:  Keyboard interrupt status and control register (KBSCR)  Keyboard interrupt enable register (KBIER)

9.7.1 Keyboard Status and Control Register

The keyboard status and control register (KBSCR):  Flags keyboard interrupt requests  Acknowledges keyboard interrupt requests  Masks keyboard interrupt requests  Controls keyboard interrupt triggering sensitivity Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard interrupt request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wakeup. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Address: $001A B i t 7 654321 B i t 0 R e a d : 0000 K E Y F 0 IMASKK MODEKWrite: ACKK R e s e t : 00000000 = Unimplemented Figure 9-3. Keyboard Status and Control Register (KBSCR)

Keyboard Interrupt Module (KBI) MC68HLC908QY/QT Family Data Sheet, Rev. 3

84 Freescale Semiconductor

9.7.2 Keyboard Interrupt Enable Register

The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup to operate as a keyboard interrupt input. KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin NOTE AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU). Address: $001B B i t 7 654321 B i t 0 Read: 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0Write: R e s e t : 00000000 = Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 85 Chapter 10 Low-Voltage Inhibit (LVI)

10.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.

10.2 Features

Features of the LVI module include:  Programmable LVI reset  Programmable power consumption  Selectable LVI trip voltage  Programmable stop mode operation

10.3 Functional Description

Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVDLVR, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See Chapter 5 Configuration Register (CONFIG). Figure 10-1. LVI Module Block Diagram LOW VDD DETECTOR LVIPWRD STOP INSTRUCTION LVISTOP LVI RESET LVIOUT VDD > LVITRIP = 0 VDD ≤ LVITRIP = 1 FROM CONFIG FROM CONFIG VDD FROM CONFIG LVIRSTD LVDLVR FROM CONFIG

Low-Voltage Inhibit (LVI) MC68HLC908QY/QT Family Data Sheet, Rev. 3

86 Freescale Semiconductor

The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit (LVIPWRD) enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit (LVIRSTD) enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF or VDTRIPF. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to operate in stop mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the LVD trip point voltage. The actual trip thresholds are specified in 16.5 DC Electrical Characteristics. Either trip level can be used as a detect or reset. NOTE After a power-on reset, the LVI’s default mode of operation is LVR trip voltage. If a higher trip voltage is desired, the user must set the LVDLVR bit to raise the trip point to the LVD voltage. If the user requires the higher trip voltage and sets the LVDLVR bit after power-on reset while the VDD supply is not above the VTRIPR for LVD mode, the microcontroller unit (MCU) will immediately go into reset. The next time the LVI releases the reset, the supply will be above the VTRIPR for LVD mode. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery sequence. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and can be used for polling LVI operation when the LVI reset is disabled.

10.3.1 Polled LVI Operation

In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module, and the LVIRSTD bit must be set to disable LVI resets.

10.3.2 Forced Reset Operation

In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.

10.3.3 Voltage Hysteresis Protection

Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.

10.3.4 LVI Trip Selection

The LVDLVR bit in the configuration register selects whether the LVI is configured for LVD (low voltage detect) or LVR (low voltage reset) protection. The LVD trip voltage can be used as a low voltage warning. The LVR trip voltage will commonly be configured as a reset condition since it is very close to the minimum operating voltage of the device. The LVDLVR bit can be written to anytime so that battery applications can make use of the LVI as both a warning indicator and to generate a system reset.

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 87 Polling and forced reset operation modes can be combined to take full advantage of LVD and LVR trip voltages selection. LVD (LVDLVR = 1) in polling mode (LVIRSTD = 1) can be used as a low voltage warning in a slowly and continuously falling VDD application (for example, battery applications). Once LVD has been identified, the part can be set to LVR (LVDLVR = 0) and reset enabled (LVIRSTD = 0). So, as V DD continues to fall the part will reset when LVR trip voltage is reached. Unlike other bits in CONFIG registers, LVIRSTD and LVDLVR bits are allowed to be written multiple times after reset. NOTE The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (V TRIPF [LVD] or VTRIPF [LVR]) may be lower than this. See 16.5 DC Electrical Characteristics for the actual trip point voltages.

10.4 LVI Status Register

The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while LVI resets have been disabled. LVIOUT — LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.

10.5 LVI Interrupts

The LVI module does not generate interrupt requests. Address: $FE0C B i t 7 654321 B i t 0 R e a d : L V I O U T 000000R Write: R e s e t : 00000000 = Unimplemented R = Reserved Figure 10-2. LVI Status Register (LVISR) Table 10-1. LVIOUT Bit Indication VDD LVIOUT VDD > VTRIPR 0 VDD < VTRIPF 1 VTRIPF < VDD < VTRIPR Previous value

Low-Voltage Inhibit (LVI) MC68HLC908QY/QT Family Data Sheet, Rev. 3

88 Freescale Semiconductor

10.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby modes.

10.6.1 Wait Mode

If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode.

10.6.2 Stop Mode

When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 89 Chapter 11 Oscillator Module (OSC)

11.1 Introduction

The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system integration module (SIM) and the computer operating properly module (COP). The BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller. Therefore the bus frequency will be one forth of the BUSCLKX4 frequency.

11.2 Features

The oscillator has these four clock source options available: 1. Internal oscillator: An internally generated, fix ed frequency clock, trimmable to ±5%. This is the default option out of reset. 2. External oscillator: An external clock that can be driven directly into OSC1. 3. External RC: A built-in oscillator module (RC os cillator) that requires an external R connection only. The capacitor is internal to the chip. 4. External crystal: A built-in oscillator module (XTA L oscillator) that requires an external crystal or ceramic-resonator.

11.3 Functional Description

The oscillator contains these major subsystems:  Internal oscillator circuit  Internal or external clock switch control  External clock circuit  External crystal circuit  External RC clock circuit

11.3.1 Internal Oscillator

The internal oscillator circuit is designed for use with no external components to provide a clock source with tolerance less than ±25% untrimmed. An 8-bit trimming register allows adjustment to a tolerance of less than ±5%. The internal oscillator will generate a clock of 4.0 MHz typical (INTCLK) resulting in a bus speed (internal clock ÷ 4) of 1.0 MHz. Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register. See Chapter 12 Input/Output Ports (PORTS).

Oscillator Module (OSC) MC68HLC908QY/QT Family Data Sheet, Rev. 3

90 Freescale Semiconductor

Figure 11-1. Block Diagram Highlighting OSC Block and Pins PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 91

11.3.1.1 Internal Oscillator Trimming

The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to 4.0 MHz ±5%. All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be copied from the FLASH to the OSCTRIM register ($0038) during reset initialization. Reset loads OSCTRIM with a default value of $80. WARNING Bulk FLASH erasure will set location $FFC0 to $FF and the factory programmed value will be lost.

11.3.1.2 Internal to External Clock Switching

When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following steps: 1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the crystal circuit start more robustly. 2. Set CONFIG2 bits OSCOPT[1:0] according to . Th e oscillator module control logic will then set OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be set as the clock output. 3. Create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait approximately 1 msec. 4. After the manufacturer’s recommended delay has elapsed, the ECGON bit in the OSC status register (OSCSTAT) needs to be set by the user software. 5. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external clock rising edges. 6. The OSC module then switches to the external clock. Logic provides a glitch free transition. 7. The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal oscillator. NOTE Once transition to the external clock is done, the internal oscillator will only be reactivated with reset. No post-switch clock monitor feature is implemented (clock does not switch back to internal if external clock dies).

11.3.2 External Oscillator

The external clock option is designed for use when a clock signal is available in the application to provide a clock source to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I/O functions on the pin.

Oscillator Module (OSC) MC68HLC908QY/QT Family Data Sheet, Rev. 3

92 Freescale Semiconductor

11.3.3 XTAL Oscillator

The XTAL oscillator circuit is designed for use with an external low-frequency crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: C r y s t a l , X1  Fixed capacitor, C 1  Tuning capacitor, C 2 (can also be a fixed capacitor)  Feedback resistor, R B  Series resistor, R S Figure 11-2. XTAL Oscillator External Connections

11.3.4 RC Oscillator

The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3. The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of 1% or less to minimize its effect on the frequency. In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the OSC2EN bit in the port A pullup enable register can be set to enable the OSC2 output function on the pin. Enabling the OSC2 output slightly increases the external RC oscillator frequency, f RCCLK. C1 C2 SIMOSCEN XTALCLK RB RS MCU FROM SIM OSC2OSC1 ÷ 2 BUSCLKX2BUSCLKX4 TO SIMTO SIM

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 93 Figure 11-3. RC Oscillator External Connections

11.4 Oscillator Module Signals

The following paragraphs describe the signals that are inputs to and outputs from the oscillator module.

11.4.1 Crystal Amplifier Input Pin (OSC1)

The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or an external clock source. For the internal oscillator configuration, the OSC1 pin can assume other functions according to Table 1-3. Function Priority in Shared Pins.

11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)

For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output. For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has no effect. For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to Table 1-3. Function Priority in Shared Pins, or the output of the oscillator clock (BUSCLKX4). Table 11-1. OSC2 Pin Function Option OSC2 Pin Function XTAL oscillator Inverting OSC1 External clock PTA4 I/O Internal oscillator or RC oscillator Controlled by OSC2EN bit in PTAPUE register OSC2EN = 0: PTA4 I/O OSC2EN = 1: BUSCLKX4 output MCU REXT SIMOSCEN OSC1 EXTERNAL RC OSCILLATOR EN RCCLK ÷ 2 BUSCLKX2BUSCLKX4 TO SIMFROM SIM VDD PTA4 I/O

0 PTA4

PTA4/BUSCLKX4 (OSC2) TO SIM See Chapter 16 Electrical Specifications for component value requirements. INTCLK OSCRCOPT

Oscillator Module (OSC) MC68HLC908QY/QT Family Data Sheet, Rev. 3

94 Freescale Semiconductor

11.4.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables either the XTAL oscillator circuit, the RC oscillator, or the internal oscillator.

11.4.4 XTAL Oscillator Clock (XTALCLK)

XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start up.

11.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of external R and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.

11.4.6 Internal Oscillator Clock (INTCLK)

INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 4.0 MHz, but it can be also trimmed using the oscillator trimming feature of the OSCTRIM register (see 11.3.1.1 Internal Oscillator Trimming).

11.4.7 Oscillator Out 2 (BUSCLKX4)

BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the SIM module and is used to determine the COP cycles.

11.4.8 Oscillator Out (BUSCLKX2)

The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK frequency.

11.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.

11.5.1 Wait Mode

The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module.

11.5.2 Stop Mode

The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4.

Oscillator During Break Mode MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 95

11.6 Oscillator During Break Mode

The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break state.

11.7 CONFIG2 Options

Two CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default configuration. Refer to Chapter 5 Configuration Register (CONFIG) for more information on how the CONFIG2 register is used. Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock source.

11.8 Input/Output (I/O) Registers

The oscillator module contains these two registers: 1. Oscillator status register (OSCSTAT) 2. Oscillator trim register (OSCTRIM)

11.8.1 Oscillator Status Register

The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources. ECGON — External Clock Generator On Bit This read/write bit enables external clock generator, so that the switching process can be initiated. This bit is forced low during reset. This bit is ignored in monitor mode with the internal oscillator bypassed. 1 = External clock generator enabled 0 = External clock generator disabled ECGST — External Clock Status Bit This read-only bit indicates whether or not an external clock source is engaged to drive the system clock. 1 = An external clock source engaged 0 = An external clock source disengaged Table 11-2. Oscillator Modes OSCOPT1 OSCOPT0 Oscillator Modes 0 0 Internal Oscillator 0 1 External Oscillator

10 E x t e r n a l R C

Address: $0036 B i t 7 654321 B i t 0 Read: RRRRRR E C G O N ECGST Write: R e s e t : 00000000 R =R e s e r v e d = Unimplemented Figure 11-4. Oscillator Status Register (OSCSTAT)

Oscillator Module (OSC) MC68HLC908QY/QT Family Data Sheet, Rev. 3

96 Freescale Semiconductor

11.8.2 Oscillator Trim Register (OSCTRIM)

TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits These read/write bits change the size of the internal capacitor used by the internal oscillator. By measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed period (the period for TRIM = $80). The trimmed frequency is guaranteed not to vary by more than ±5% over the full specified range of temperature and voltage. The reset value is $80, which sets the frequency to 4.0 MHz (1.0 MHz bus speed) ±25%. Address: $0038 B i t 7 654321 B i t 0 Read: TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0 Write: R e s e t : 10000000 Figure 11-5. Oscillator Trim Register (OSCTRIM)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 97 Chapter 12 Input/Output Ports (PORTS)

12.1 Introduction

The MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 have five bidirectional input-output (I/O) pins and one input only pin. The MC68HLC908QY1, MC68HLC908QY2, and MC68HLC908QY4 have thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. 8-pin devices have non-bonded pins. These pins should be configured either as outputs driving low or high, or as inputs with internal pullups enabled. Configuring these non-bonded pins in this manner will prevent any excess current consumption caused by floating inputs.

12.2 Port A

Port A is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module (see Chapter 9 Keyboard Interrupt Module (KBI)). Each port A pin also has a software configurable pullup device if the corresponding port pin is configured as an input port. NOTE PTA2 is input only. When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2 of the port A data register (PTA) will always read a 0. In this case, the BIH and BIL instructions can be used to read the logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin.

Input/Output Ports (PORTS) MC68HLC908QY/QT Family Data Sheet, Rev. 3

98 Freescale Semiconductor

12.2.1 Port A Data Register

The port A data register (PTA) contains a data latch for each of the six port A pins. PTA[5:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. AWUL — Auto Wakeup Latch Data Bit This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6 port nor any of the associated bits such as PTA6 data register, pullup enable or direction. KBI[5:0] — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard interrupt control enable register (KBIER) enable the port A pins as external interrupt pins (see Chapter 9 Keyboard Interrupt Module (KBI)).

12.2.2 Data Direction Register A

Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer. DDRA[5:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Address: $0000 B i t 7 654321 B i t 0 Read: R AWUL PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Reset: Unaffected by reset Additional Functions: KBI5 KBI4 KBI3 KBI2 KBI1 KBI0 R= R e s e r v e d = Unimplemented Figure 12-1. Port A Data Register (PTA) Address: $0004 B i t 7 654321 B i t 0 Read: R R DDRA5 DDRA4 DDRA3 DDRA1 DDRA0 Write: R e s e t : 00000000 R = Reserved = Unimplemented Figure 12-2. Data Direction Register A (DDRA)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 99 Figure 12-3 shows the port A I/O logic. Figure 12-3. Port A I/O Circuit NOTE Figure 12-3 does not apply to PTA2 When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.

12.2.3 Port A Input Pullup Enable Register

The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each if the six port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output. OSC2EN — Enable PTA4 on OSC2 Pin This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options. 1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4) 0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions Address: $000B B i t 7 654321 B i t 0 Read: OSC2EN PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Write: R e s e t : 00000000 = Unimplemented Figure 12-4. Port A Input Pullup Enable Register (PTAPUE) READ DDRA ($0004) WRITE DDRA ($0004) RESET WRITE PTA ($0000) READ PTA ($0000) PTAx DDRAx PTAx INTERNAL DATA BUS 30 k PTAPUEx TO KEYBOARD INTERRUPT CIRCUIT

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PTAPUE[5:0] — Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins. 1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0 0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Table 12-1 summarizes the operation of the port A pins.

12.3 Port B

Port B is an 8-bit general purpose I/O port. Port B is only available on the MC68HLC908QY1, MC68HLC908QY2, and MC68HLC908QY4.

12.3.1 Port B Data Register

The port B data register (PTB) contains a data latch for each of the eight port B pins. PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. Table 12-1. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write

10 X(1)

1. X = don’t care Input, VDD (2) 2. I/O pin pulled to VDD by internal pullup. DDRA5–DDRA0 Pin PTA5–PTA0(3) 3. Writing affects data register, but does not affect input.

00 X Input, Hi-Z(4)

1. Hi-Z = high impedance DDRA5–DDRA0 Pin PTA5–PTA0(3) X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5) 5. Output does not apply to PTA2 Address: $0001 B i t 7 654321 B i t 0 Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write: Reset: Unaffected by reset Figure 12-5. Port B Data Register (PTB)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 101

12.3.2 Data Direction Register B

Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 12-7 shows the port B I/O logic. Figure 12-7. Port B I/O Circuit When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port B pins. Address: $0005 B i t 7 654321 B i t 0 Read: DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Write: R e s e t : 00000000 Figure 12-6. Data Direction Register B (DDRB) Table 12-2. Port B Pin Functions DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB Read/Write Read Write

0 X(1)

1. X = don’t care Input, Hi-Z(2) 2. Hi-Z = high impedance DDRB7–DDRB0 Pin PTB7–PTB0(3) 3. Writing affects data register, but does not affect the input.

1 X Output DDRB7–DDRB0 Pin PTB7–PTB0

READ DDRB ($0005) WRITE DDRB ($0005) RESET WRITE PTB ($0001) READ PTB ($0001) PTBx DDRBx PTBx INTERNAL DATA BUS 30 k PTBPUEx

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12.3.3 Port B Input Pullup Enable Register

The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output. PTBPUE[7:0] — Port B Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port B pins 1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0 0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit. Table 12-3 summarizes the operation of the port B pins. Address: $000C B i t 7 654321 B i t 0 Read: PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0 Write: Reset: 00000000 Figure 12-8. Port B Input Pullup Enable Register (PTBPUE) Table 12-3. Port B Pin Functions PTBPUE Bit DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Accesses to PTB Read/Write Read Write

1. X = don’t care Input, VDD (2) 2. I/O pin pulled to VDD by internal pullup. DDRB7–DDRB0 Pin PTB7–PTB0(3) 3. Writing affects data register, but does not affect input.
2. Hi-Z = high impedance DDRB7–DDRB0 Pin PTB7–PTB0(3) X 1 X Output DDRB7–DDRB0 PTB7–PTB0 PTB7–PTB0

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 103 Chapter 13 System Integration Module (SIM)

13.1 Introduction

This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for:  Bus clock generation and control for CPU and peripherals – Stop/wait/reset/break entry and recovery – Internal clock control  Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout  Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation  CPU enable/disable timing

13.2 RST and IRQ Pins Initialization

RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG). Table 13-1. Signal Name Conventions Signal Name Description BUSCLKX4 Buffered clock from the internal, RC or XTAL oscillator circuit. BUSCLKX2 The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4). Address bus Internal address bus Data bus Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal

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Figure 13-1. SIM Block Diagram

13.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2. Figure 13-2. SIM Clock Signals STOP/WAIT CLOCK CONTROL CLOCK GENERATORS POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) INTERNAL CLOCKS MASTER RESET CONTROL RESET PIN LOGIC ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE RESET CONTROL SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) LVI RESET (FROM LVI MODULE) VDD INTERNAL PULL-UP FORCED MON MODE ENTRY (FROM MENRST MODULE) ÷ 2 BUS CLOCK GENERATORS SIM SIM COUNTERFROM OSCILLATOR FROM OSCILLATOR BUSCLKX2 BUSCLKX4

Reset and System Initialization MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 105

13.3.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.

13.3.2 Clock Start-Up from POR

When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon completion of the time out.

13.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4 cycles. See 13.7.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

13.4 Reset and System Initialization

The MCU has these reset sources:  Power-on reset module (POR)  External reset pin (RST )  Computer operating properly module (COP)  Low-voltage inhibit module (LVI)  Illegal opcode  Illegal address All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers.

13.4.1 External Pin Reset

The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at least the minimum tRL time. Figure 13-3 shows the relative timing. The RST pin function is only available if the RSTEN bit is set in the CONFIG2 register. Figure 13-3. External Reset Timing RST ADDRESS BUS PC VECT H VECT L BUSCLKX2

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13.4.2 Active Resets from Internal Sources

The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when describing activity on the RST pin. All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out, LVI, or POR (see Figure 13-5). NOTE For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 13-4. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. Figure 13-4. Internal Reset Timing Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) IRST RST RST PULLED LOW BY MCU ADDRESS

32 CYCLES 32 CYCLES

Reset and System Initialization MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 107

13.4.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power on, the following events occur:  A POR pulse is generated.  The internal reset signal is asserted.  The SIM enables the oscillator to drive BUSCLKX4.  Internal clocks to the CPU and modules are hel d inactive for 4096 BUSCLKX4 cycles to allow stabilization of the oscillator.  The POR bit of the SIM reset status register (SRSR) is set. See Figure 13-6. Figure 13-6. POR Recovery

13.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least every 4080 BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR). PORRST OSC1 BUSCLKX4 BUSCLKX2 RST ADDRESS BUS 4096 CYCLES CYCLES CYCLES $FFFE $FFFF (RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)

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13.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources.

13.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.

13.4.2.5 Low-Voltage Inhibit (LVI) Reset

The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset sources.

13.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of BUSCLKX4.

13.5.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.

13.5.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1).

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 109

13.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.

13.6 Exception Control

Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts

13.6.1 Interrupts

An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 13-7 flow charts the handling of system interrupts. Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 13-8 shows interrupt entry timing. Figure 13-9 shows interrupt recovery timing.

13.6.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.

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Figure 13-7. Interrupt Processing NO NO NO YES NO NO YES NO YES YES (AS MANY INTERRUPTS AS EXIST ON CHIP) I BIT SET? FROM RESET BREAK INTERRUPT? I BIT SET? IRQ INTERRUPT? TIMER INTERRUPT? SWI INSTRUCTION? RTI INSTRUCTION? FETCH NEXT INSTRUCTION UNSTACK CPU REGISTERS EXECUTE INSTRUCTION YES YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR

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The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.

13.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does.

13.6.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging.

13.6.2.1 Interrupt Status Register 1

Table 13-3. Interrupt Sources Priority Source Flag Mask(1) 1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. INT Register Flag Vector Address Highest Lowest SWI instruction — — — $FFFC–$FFFD IRQ pin IRQF IMASK IF1 $FFFA–$FFFB Timer channel 0 interrupt CH0F CH0IE IF3 $FFF6–$FFF7 Timer channel 1 interrupt CH1F CH1IE IF4 $FFF4–$FFF5 Timer overflow interrupt TOF TOIE IF5 $FFF2–$FFF3 Keyboard interrupt KEYF IMASKK IF14 $FFE0–$FFE1 ADC conversion complete interrupt COCO AIEN IF15 $FFDE–$FFDF Address: $FE04 B i t 7 654321 B i t 0 Read: 0 IF5 IF4 IF3 0 IF1 0 0 W r i t e : RRRRRRRR R e s e t : 00000000 R= R e s e r v e d Figure 13-11. Interrupt Status Register 1 (INT1)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 113 IF1 and IF3–IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3, and 7 — Always read 0

13.6.2.2 Interrupt Status Register 2

IF14 — Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0–6 — Always read 0

13.6.2.3 Interrupt Status Register 3

IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1–7 — Always read 0

13.6.3 Reset

All reset sources always have equal and highest priority and cannot be arbitrated.

13.6.4 Break Interrupts

The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break Address: $FE05 B i t 7 654321 B i t 0 R e a d : I F 1 4 0000000 W r i t e : RRRRRRRR R e s e t : 00000000 R= R e s e r v e d Figure 13-12. Interrupt Status Register 2 (INT2) Address: $FE06 B i t 7 654321 B i t 0 R e a d : 0000000 I F 1 5 W r i t e : RRRRRRRR R e s e t : 00000000 R= R e s e r v e d Figure 13-13. Interrupt Status Register 3 (INT3)

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state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.

13.6.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.

13.7 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.

13.7.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-14 shows the timing for wait mode entry. Figure 13-14. Wait Mode Entry Timing A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the configuration register is 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. WAIT ADDR + 1 SAME SAMEADDRESS BUS DATA BUS PREVIOUS DATA NEXT OPCODE SAME WAIT ADDR SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 115 Figure 13-15 and Figure 13-16 show the timing for wait recovery. Figure 13-15. Wait Recovery from Interrupt Figure 13-16. Wait Recovery from Internal Reset

13.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. NOTE External crystal applications should use the full stop recovery time by clearing the SSREC bit. $6E0C$6E0B $00FF $00FE $00FD $00FC ADDRESS BUS DATA BUS EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt ADDRESS BUS DATA BUS RST(1) $A6 $A6 $6E0B RST VCT H RST VCT L $A6 BUSCLKX4 CYCLES CYCLES 1. RST is only available if the RSTEN bit in the CONFIG1 register is set.

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The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and Figure 13-18 shows the stop mode recovery time from interrupt or break NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. Figure 13-17. Stop Mode Entry Timing Figure 13-18. Stop Mode Recovery from Interrupt

13.8 SIM Registers

The SIM has three memory mapped registers. Table 13-4 shows the mapping of these registers. Table 13-4. SIM Registers Address Register Access Mode $FE00 BSR User $FE01 SRSR User $FE03 BFCR User STOP ADDR + 1 SAME SAMEADDRESS BUS DATA BUS PREVIOUS DATA NEXT OPCODE SAME STOP ADDR SAME R/W CPUSTOP NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. BUSCLKX4 INTERRUPT ADDRESS BUS STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3STOP +1 STOP RECOVERY PERIOD

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 117

13.8.1 SIM Reset Status Register

The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time. POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ ≠ VTST 0 = POR or read of SRSR LVI — Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR Address: $FE01 B i t 7 654321 B i t 0 Read: POR PIN COP ILOP ILAD MODRST LVI 0 Write: P O R : 10000000 = Unimplemented Figure 13-19. SIM Reset Status Register (SRSR)

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13.8.2 Break Flag Control Register

The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break Address: $FE03 B i t 7 654321 B i t 0 Read: B C F E RRRRRRR Write: Reset: 0 R = Reserved Figure 13-20. Break Flag Control Register (BFCR)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 119 Chapter 14 Timer Interface Module (TIM)

14.1 Introduction

This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 14-2 is a block diagram of the TIM.

14.2 Features

Features of the TIM include the following:  Two input capture/output compare channels – Rising-edge, falling-edge, or any-edge input capture trigger – Set, clear, or toggle output compare action  Buffered and unbuffered pulse width modulation (PWM) signal generation  Programmable TIM clock input – 7-frequency internal bus clock prescaler selection – External TIM clock input  Free-running or modulo up-count operation  Toggle any channel pin on overflow  TIM counter stop and reset bits

14.3 Pin Name Conventions

The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in Table 14-1. The generic pin name appear in the text that follows. Table 14-1. Pin Name Conventions TIM Generic Pin Names: TCH0 TCH1 TCLK Full TIM Pin Names: PTA0/TCH0 PTA1/TCH1 PTA2/TCLK

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Figure 14-1. Block Diagram Highlighting TIM Block and Pins PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1

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14.4 Functional Description

Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels. Figure 14-2. TIM Block Diagram PRESCALER PRESCALER SELECT 16-BIT COMPARATOR PS2 PS1 PS0 16-BIT COMPARATOR 16-BIT LATCH TCH0H:TCH0L MS0A ELS0B ELS0A TOF TOIE 16-BIT COMPARATOR 16-BIT LATCH TCH1H:TCH1L CHANNEL 0 CHANNEL 1 TMODH:TMODL TRST TSTOP TOV0 CH0IE CH0F ELS1B ELS1A TOV1 CH1IE CH1MAX CH1F CH0MAX MS0B 16-BIT COUNTER INTERNAL BUS MS1A INTERNAL BUS CLOCK TCH1 TCH0 INTERRUPT LOGIC PORT LOGIC INTERRUPT LOGIC INTERRUPT LOGIC PORT LOGIC PTA2/IRQ/KBI2/TCLK

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14.4.1 TIM Counter Prescaler

The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.

14.4.2 Input Capture

With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM central processor unit (CPU) interrupt requests.

14.4.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests.

14.4.3.1 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare pulses as described in 14.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x:  When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.  When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.

14.4.3.2 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 123 control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.

14.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 14-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program the TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1). The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See 14.9.1 TIM Status and Control Register. The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. Figure 14-3. PWM Period and Pulse Width TCHx PERIOD PULSE WIDTH OVERFLOW OVERFLOW OVERFLOW OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE TCHx POLARITY = 1 (ELSxA = 0) POLARITY = 0 (ELSxA = 1)

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14.4.4.1 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as described in 14.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:  When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value.  When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

14.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.

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14.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 14-3. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 14-3. NOTE In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 14.9.4 TIM Channel Status and Control Registers.

14.5 Interrupts

The following TIM sources can generate interrupt requests:  TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register.  TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TIM channel x status and control register.

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14.6 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode. The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.

14.7 TIM During Break Interrupts

A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 13.8.2 Break Flag Control Register. To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the second step clears the status bit.

14.8 Input/Output Signals

Port A shares three of its pins with the TIM. Two TIM channel I/O pins are PTA0/TCH0 and PTA1/TCH1 and an alternate clock source is PTA2/TCLK.

14.8.1 TIM Clock Pin (PTA2/TCLK)

PTA2/TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock. Select the PTA2/TCLK input by writing 1s to the three prescaler select bits, PS[2–0]. (See 14.9.1 TIM Status and Control Register.) When the PTA2/TCLK pin is the TIM clock input, it is an input regardless of port pin initialization.

14.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1)

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTA0/TCH0 can be configured as a buffered output compare or buffered PWM pin.

14.9 Input/Output Registers

The following I/O registers control and monitor operation of the TIM:  TIM status and control register (TSC)  TIM counter registers (TCNTH:TCNTL)  TIM counter modulo registers (TMODH:TMODL)  TIM channel status and control registers (TSC0 and TSC1)  TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)

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14.9.1 TIM Status and Control Register

The TIM status and control register (TSC) does the following:  Enables TIM overflow interrupts  Flags TIM overflows  Stops the TIM counter  Resets the TIM counter  Prescales the TIM counter clock TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. When the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until the TSTOP bit is cleared. When using TSTOP to stop the timer counter, see if any timer flags are set. If a timer flag is set, it must be cleared by clearing TSTOP, then clearing the flag, then setting TSTOP again. Address: $0020 B i t 7 654321 B i t 0 Read: TOF TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST R e s e t : 00100000 = Unimplemented Figure 14-4. TIM Status and Control Register (TSC)

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TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as a 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 14-2 shows. Reset clears the PS[2:0] bits.

14.9.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. Table 14-2. Prescaler Selection PS2 PS1 PS0 TIM Clock Source 0 0 0 Internal bus clock ÷ 1 0 0 1 Internal bus clock ÷ 2 0 1 0 Internal bus clock ÷ 4 0 1 1 Internal bus clock ÷ 8 1 0 0 Internal bus clock ÷ 16 1 0 1 Internal bus clock ÷ 32 1 1 0 Internal bus clock ÷ 64

111 P T A 2 / T C L K

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14.9.3 TIM Counter Modulo Registers

The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers. NOTE Reset the TIM counter before writing to the TIM counter modulo registers. Address: $0021 TCNTH B i t 7 654321 B i t 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: R e s e t : 00000000 Address: $0022 TCNTL B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: R e s e t : 00000000 = Unimplemented Figure 14-5. TIM Counter Registers (TCNTH:TCNTL) Address: $0023 TMODH B i t 7 654321 B i t 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8Write: R e s e t : 11111111 Address: $0024 TMODL B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Write: R e s e t : 11111111 Figure 14-6. TIM Counter Modulo Registers (TMODH:TMODL)

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14.9.4 TIM Channel Status and Control Registers

Each of the TIM channel status and control registers does the following:  Flags input captures and output compares  Enables input capture and output compare interrupts  Selects input capture, output compare, or PWM operation  Selects high, low, or toggling output on output compare  Selects rising edge, falling edge, or any edge as the active input capture trigger  Selects output toggling on TIM overflow  Selects 0% and 100% PWM duty cycle  Selects buffered or unbuffered output compare/PWM operation CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Address: $0025 TSC0 B i t 7 654321 B i t 0 Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAXWrite: 0 R e s e t : 00000000 Address: $0028 TSC1 B i t 7 654321 B i t 0 Read: CH1F CH1IE 0 MS1A ELS1B ELS1A TOV1 CH1MAXWrite: 0 R e s e t : 00000000 = Unimplemented Figure 14-7. TIM Channel Status and Control Registers (TSC0:TSC1)

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 131 Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 14-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-3). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. Table 14-3. Mode, Edge, and Level Selection MSxB MSxA ELSxB ELSxA Mode Configuration X0 0 0 Output preset Pin under port control; initial output level high X 1 0 0 Pin under port control; initial output level low 00 0 1 Input capture Capture on rising edge only 0 0 1 0 Capture on falling edge only 0 0 1 1 Capture on rising or falling edge 01 0 0 Output compare or PWM Software compare only 0 1 0 1 Toggle output on compare 0 1 1 0 Clear output on compare 0 1 1 1 Set output on compare 1X 0 1 Buffered output compare or buffered PWM Toggle output on compare

1 X 1 0 Clear output on compare

1 X 1 1 Set output on compare

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When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 14-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. NOTE After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags. TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 14-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. Figure 14-8. CHxMAX Latency

14.9.5 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. OUTPUT OVERFLOW TCHx PERIOD CHxMAX OVERFLOW OVERFLOW OVERFLOW OVERFLOW COMPARE OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 133 Address: $0026 TCH0H B i t 7 654321 B i t 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Indeterminate after reset Address: $0027 TCH0L B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: Reset: Indeterminate after reset Address: $0029 TCH1H B i t 7 654321 B i t 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Indeterminate after reset Address: $02A TCH1L B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: Reset: Indeterminate after reset Figure 14-9. TIM Channel Registers (TCH0H/L:TCH1H/L)

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 135 Chapter 15 Development Support

15.1 Introduction

This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods.

15.2 Break Module (BRK)

The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include:  Accessible input/output (I/O) registers during the break Interrupt  Central processor unit (CPU) generated break interrupts  Software-generated break interrupts  Computer operating properly (COP ) disabling during break interrupts

15.2.1 Functional Description

When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur:  A CPU generated address (the address in the program counter) matches the contents of the break address registers.  Software writes a 1 to the BRKA bit in the break status and control register. When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 15-2 shows the structure of the break module.

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Figure 15-1. Block Diagram Highlighting BRK and MON Blocks Figure 15-2. Break Module Block Diagram PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 KEYBOARD INTERRUPT MODULE CLOCK GENERATOR (OSCILLATOR) SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE 16-BIT TIMER MODULE COP MODULE MONITOR ROM PTB0 PTB DDRB M68HC08 CPU PTA DDRA PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC MC68HLC908QY4 AND MC68HLC908QT4 MC68HLC908QY2, MC68HLC908QY1, MC68HLC908QT2, AND MC68HLC908QT1: RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices – MC68HLC908QT1, MC68HLC908QT2, and MC68HLC908QT4 (see note in ADC: Not available on the MC68HLC908QY1 and MC68HC9L08QT1 ADDRESS BUS[15:8] ADDRESS BUS[7:0] 8-BIT COMPARATOR 8-BIT COMPARATOR CONTROL BREAK ADDRESS REGISTER LOW BREAK ADDRESS REGISTER HIGH ADDRESS BUS[15:0] BKPT (TO SIM)

Break Module (BRK) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 137 When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:  Loading the instruction register with the SWI instruction  Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is:  When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine.  When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt.  When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed. By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously. CAUTION A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers.

15.2.1.1 Flag Protection During Break Interrupts

The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection for each module.

15.2.1.2 TIM During Break Interrupts

A break interrupt stops the timer counter.

15.2.1.3 COP During Break Interrupts

The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR).

15.2.2 Break Module Registers

These registers control and monitor operation of the break module:  Break status and control register (BRKSCR)  Break address register high (BRKH)  Break address register low (BRKL)  Break status register (BSR)  Break flag control register (BFCR)

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15.2.2.1 Break Status and Control Register

The break status and control register (BRKSCR) contains break module enable and status bits. BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match

15.2.2.2 Break Address Registers

The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE0B B i t 7 654321 B i t 0 Read: BRKE BRKA 000000 Write: R e s e t : 00000000 = Unimplemented Figure 15-3. Break Status and Control Register (BRKSCR) Address: $FE09 B i t 7 654321 B i t 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: R e s e t : 00000000 Figure 15-4. Break Address Register High (BRKH) Address: $FE0A B i t 7 654321 B i t 0 Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write: R e s e t : 00000000 Figure 15-5. Break Address Register Low (BRKL)

Break Module (BRK) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 139

15.2.2.3 Break Auxiliary Register

The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit. 1 = COP disabled during break interrupt 0 = COP enabled during break interrupt.

15.2.2.4 Break Status Register

The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt

15.2.2.5 Break Flag Control Register

The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE02 B i t 7 654321 B i t 0 R e a d : 0000000 BDCOP Write: R e s e t : 00000000 = Unimplemented Figure 15-6. Break Auxiliary Register (BRKAR) Address: $FE00 B i t 7 654321 B i t 0 Read: RRRRRR SBSW RWrite: Note (1) Reset: 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 15-7. Break Status Register (BSR) Address: $FE03 B i t 7 654321 B i t 0 Read: B C F E RRRRRRRWrite: Reset: 0 R = Reserved Figure 15-8. Break Flag Control Register (BFCR)

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BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break

15.2.3 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered.

15.3 Monitor Module (MON)

This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features include:  Normal user-mode pin functionality on most pins  One pin dedicated to serial communi cation between MCU and host computer  Standard non-return-to-zero (NRZ) communication with host computer  Execution of code in random-a ccess memory (RAM) or FLASH  FLASH memory security feature (1)  FLASH memory programming interface  Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz  Simple internal oscillator mode of operat ion (no external clock or high voltage)  Monitor mode entry without high voltage, V TST, if reset vector is blank ($FFFE and $FFFF contain $FF)  Standard monitor mode entry if high voltage is applied to IRQ

15.3.1 Functional Description

Figure 15-9 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. Figure 15-10, Figure 15-11, and Figure 15-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.

Monitor Module (MON) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 141 Figure 15-9. Simplified Monitor Mode Entry Flowchart MONITOR MODE ENTRY POR RESET PTA0 = 1, PTA1 = 1, AND PTA4 = 0? IRQ = VTST? YES NO YESNO FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE NO NO HOST SENDS

8 SECURITY BYTES

POR? YES YES YES NO ARE ALL SECURITY BYTES CORRECT? NOYES ENABLE FLASH DISABLE FLASH EXECUTE MONITOR CODE DOES RESET OCCUR? CONDITIONS FROM Table 15-1 DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) PTA0 = 1, RESET VECTOR BLANK?

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Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage) Figure 15-11. Monitor Mode Circuit (External Clock, No High Voltage)

9.8304 MHz CLOCK

10 kΩ* VDD 10 kΩ* RST (PTA3) IRQ (PTA2) PTA0 OSC1 (PTA5) DB9 VDD MAX232 1 µF + 2 3 4 74HC125 74HC125 10 kΩ PTA1 PTA4 VSS 0.1 µF VDD 1 kΩ 9.1 V C1+ C1– 1 µF C2+ C2– 1 µF + 1 µF VDD 1 µF VTST * Value not critical VDDVDD 10 kΩ* RST (PTA3) IRQ (PTA2) PTA0 OSC1 (PTA5) DB9 VDD 1 µF MAX232 VDD 1 µF + 2 3 4 74HC125 74HC125 10 kΩ N.C.PTA1 N.C.PTA4 VSS 0.1 µF VDD

9.8304 MHz CLOCK C1+

C1– 1 µF C2+ C2– 1 µF + + 1 µF VDD 10 kΩ* * Value not critical N.C.

Monitor Module (MON) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 143 Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage) The monitor code has been updated from previous versions of the monitor code to allow enabling the internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out of reset, is intended to support serial communication/programming at 4800 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if programmed) to generate the desired internal frequency (1.0 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must remain low during this monitor session in order to maintain communication. Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met:  If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 9.8304 MHz –I R Q = VTST  If $FFFE and $FFFF contain $FF (erased state): – The external clock is 9.8304 MHz –I R Q = VDD (this can be implemented through the internal IRQ pullup)  If $FFFE and $FFFF contain $FF (erased state): –I R Q = VSS (internal oscillator is selected, no external clock required) The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the values on PTA1 and PTA4 pins can be changed. RST (PTA3) IRQ (PTA2) PTA0 10 kΩ* OSC1 (PTA5)N.C. DB9 VDD 1 µF MAX232 C1+ C1– V–5 1 µF C2+ C2– VDD 1 µF + 2 3 4 74HC125 74HC125 10 kΩ N.C.PTA1 N.C.PTA4 VSS 0.1 µF VDD 1 µF + + 1 µF VDD * Value not critical N.C.

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Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command.

15.3.1.1 Normal Monitor Mode

RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in monitor mode, but the pin functions will be determined by the settings in the configuration registers (see Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register. If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ. Table 15-1. Monitor Mode Signal Requirements and Options Mode IRQ (PTA2) RST (PTA3) Reset Vector Serial Communi- cation Mode Selection COP Communication Speed Comments PTA0 PTA1 PTA4 External Clock Bus Frequency Baud Rate Normal Monitor VTST VDD X1 1 0 D i s a b l e d 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. Forced Monitor VDD X $FFFF (blank) 1X X D i s a b l e d 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. V SS X $FFFF (blank) 1X X D i s a b l e d X 1.0 MHz (Trimmed) 4800 Internal clock is active. User X X Not $FFFF X X X Enabled X X X MON08 Function [Pin No.] V TST [6] RST [4] — COM [8] MOD0 [12] MOD1 [10] — OSC1 [13] —— 1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256 and baud rate using internal oscillator is bus frequency / 206. 3. External clock is a 9.8304 MHz oscillator on OSC1. 4. X = don’t care 5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector. NC 1 2 GND NC 3 4 RST NC 5 6 IRQ NC 7 8 PTA0 NC 9 10 PTA4 NC 11 12 PTA1 OSC1 13 14 NC V DD 15 16 NC

Monitor Module (MON) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 145

15.3.1.2 Forced Monitor Mode

If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, V TST, to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled regardless of the state of IRQ. If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at its default frequency. If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will operate as a serial communication port and OSC1 input respectively (refer to Figure 15-11). That will allow the clock to be driven from an external source through OSC1 pin. If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as serial communication port. Refer to Figure 15-12. Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register (CONFIG). The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will automatically force the MCU to come back to the forced monitor mode.

15.3.1.3 Monitor Vectors

In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST (when RST pin available) low will not exit monitor mode in this situation. Table 15-2 summarizes the differences between user mode and monitor mode regarding vectors. Table 15-2. Mode Difference Modes Functions Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD

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15.3.1.4 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. Figure 15-13. Monitor Data Format

15.3.1.5 Break Signal

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal. Figure 15-14. Break Transaction

15.3.1.6 Baud Rate

The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in Table 15-1. Table 15-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 206.

15.3.1.7 Commands

The monitor ROM firmware uses these commands:  READ (read memory)  WRITE (write memory)  IREAD (indexed read)  IWRITE (indexed write)  READSP (read stack pointer)  RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte. BIT 5 START BIT BIT 1 NEXT STOP BIT START BITBIT 2 BIT 3 BIT 4 BIT 7BIT 0 BIT 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO

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A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 15-4. WRITE (Write Memory) Command Description Write byte to memory Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte Data Returned None Opcode $49 Command Sequence Table 15-5. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand None Data Returned Returns contents of next two addresses Opcode $1A Command Sequence Table 15-6. IWRITE (Indexed Write) Command Description Write to last address accessed + 1 Operand Single data byte Data Returned None Opcode $19 Command Sequence WRITEWRITE ECHO FROM HOST ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA IREADIREAD ECHO DATA RETURN DATA FROM HOST IWRITEIWRITE ECHO FROM HOST DATA DATA

Monitor Module (MON) MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 149 The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6. Figure 15-17. Stack Pointer at Monitor Mode Entry Table 15-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order Opcode $0C Command Sequence Table 15-8. RUN (Run User Program) Command Description Executes PULH and RTI instructions Operand None Data Returned None Opcode $28 Command Sequence READSPREADSP ECHO FROM HOST SP RETURN SP HIGH LOW RUNRUN ECHO FROM HOST CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP SP + 6 HIGH BYTE OF INDEX REGISTER SP + 7

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15.3.2 Security

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 15-18. Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE The MCU does not transmit a break character until after the host sends the eight security bytes. To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Figure 15-18. Monitor Mode Entry Timing BYTE 1 BYTE 1 ECHO BYTE 2 BYTE 2 ECHO BYTE 8 BYTE 8 ECHO COMMAND COMMAND ECHO PA0 RST VDD 4096 + 32 CGMXCLK CYCLES 1 3 1 1 2 1 BREAKNotes: 2 = Data return delay, approximately 2 bit times 3 = Wait 1 bit time before sending next byte FROM HOST FROM MCU 1 = Echo delay, approximately 2 bit times 4 = Wait until clock is stable and monitor runs

MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 151 Chapter 16 Electrical Specifications

16.1 Introduction

This section contains electrical and timing specifications.

16.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 DC Electrical Characteristics for guaranteed operating conditions. NOTE This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that V IN and VOUT be constrained to the range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.) Characteristic(1) 1. Voltages references to VSS. Symbol Value Unit Supply voltage VDD –0.3 to +6.0 V Input voltage VIN VSS –0.3 to VDD +0.3 V Mode entry voltage, IRQ pin VTST VSS –0.3 to +9.1 V Maximum current per pin excluding PTA0–PTA5, VDD, and VSS I± 1 5 m A Maximum current for pins PTA0–PTA5 IPTA0— IPTA5 ±25 mA Storage temperature TSTG –55 to +150 °C Maximum current out of VSS IMVSS 100 mA Maximum current into VDD IMVDD 100 mA

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16.3 Functional Operating Range

16.4 Thermal Characteristics

Characteristic Symbol Value Unit Temp Code Operating temperature range (TL to TH)T A –40 to 85 0 to 70 °C C Operating voltage range(1) (VDDMIN to VDDMAX) –40 to 85°C 0 to 70°C 1. VDD must be above VTRIPR upon power on. VDD 2.4 to 3.6 2.2 to 3.6 VC Characteristic Symbol Value Unit Thermal resistance 8-pin PDIP 8-pin SOIC 8-pin DFN 16-pin PDIP 16-pin SOIC 16-pin TSSOP θ JA 105 142 173 133 °C/W I/O pin power dissipation P I/O User determined W Power dissipation(1) 1. Power dissipation is a function of temperature. PD PD = (IDD x VDD) + PI/O = K/(TJ + 273°C) W Constant(2) 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. K PD x (TA + 273°C) + PD x θJA W/°C Average junction temperature TJ TA + (PD x θJA) °C Maximum junction temperature TJM 150 °C

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16.5 DC Electrical Characteristics

Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (for VDD > 2.7 V) ILoad = –4 mA ILoad = –10 mA, PTA0, PTA1, PTA3–PTA5 only VOH VDD–0.8 VDD–0.8 V Output high voltage (for VDDMIN < VDD < VDDMAX) ILoad = –2 mA ILoad = –5 mA, PTA0, PTA1, PTA3–PTA5 only VOH VDD–0.8 VDD–0.8 V Output low voltage (for VDD > 2.7 V) ILoad = 4 mA ILoad = 10 mA, PTA0, PTA1, PTA3–PTA5 only VOL — 0.8 0.8 V Output low voltage (for VDDMIN < VDD < VDDMAX) ILoad = 2 mA ILoad = 5 mA, PTA0, PTA1, PTA3–PTA5 only VOL — 0.8 0.8 V Maximum combined IOH (all I/O pins) I OHT —— 5 0 m A Maximum combined IOL (all I/O pins) I OLT —— 5 0 m A Input high voltage PTA0–PTA5, PTB0–PTB7 VIH 0.7 x VDD — VDD V Input low voltage PTA0–PTA5, PTB0–PTB7 VIL VSS — 0.3 x VDD V Input hysteresis VHYS 0.06 x VDD —— V DC injection current, all ports IINJ –2 — +2 mA Total dc current injection (sum of all I/O) IINJTOT –25 — +25 mA Digital I/O ports Hi-Z leakage current Typical at 25°C IIL ±0.1 — µA Digital input only ports leakage current (PA2/IRQ/KBI2) IIN –1 — +1 µA Capacitance Ports (as input) Ports (as output) CIN COUT 8 pF POR rearm voltage(3) VPOR 0— 1 0 0 m V POR rise time ramp rate(4) RPOR 0.035 — — V/ms Monitor mode entry voltage VTST VDD + 2.5 —9 . 1 V Pullup resistors(5) PTA0–PTA5, PTB0–PTB7 RPU 16 26 36 k Ω — Continued on next page

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16.6 Control Timing

Figure 16-1. RST and IRQ Timing Low-voltage inhibit reset, trip falling voltage (LVR) VTRIPF 2.00 2.12 2.24 V Low-voltage inhibit reset, trip rising voltage (LVR) VTRIPR 2.04 2.18 2.30 V Low-voltage inhibit reset/recover hysteresis VHYS —6 0 — m V Low-voltage detect, trip falling voltage (LVD) VDTRIPF 2.20 2.32 2.44 V Low-voltage detect, trip rising voltage (LVD) VDTRIPR 2.21 2.33 2.45 V Low-voltage detect reset/recover hysteresis VDHYS —1 0 — m V 1. VDD = VDDMIN to VDDMAX, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at VDD = 3.0 V, 25°C only. 3. Maximum is highest voltage that POR is guaranteed. 4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 5. RPU is measured at VDD = 3.0 V. Characteristic(1) 1. VDD >= 2.2 V, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted. Symbol Min Max Unit Internal operating frequency fOP (fBus) —2 M H z Internal clock period (1/fOP)t cyc 500 — ns RST input pulse width low tRL 400 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 400 — ns IRQ interrupt pulse period tILIL Note(2) 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. — tcyc Characteristic(1) Symbol Min Typ(2) Max Unit RST IRQ tRL tILIH tILIL

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16.8 Oscillator Characteristics

Figure 16-4. Typical RC Oscillator Frequency versus REXT (25°C) Characteristic Symbol Min Typ Max Unit Internal oscillator frequency(1) 1. Bus frequency, fOP, is oscillator frequency divided by 4. fINTCLK —4 . 0— M H z Crystal frequency, XTALCLK(1) fOSCXCLK 30 32.768 100 kHz External RC oscillator frequency, RCCLK(1) fRCCLK 2—8 M H z External clock reference frequency(1), (2) 2. No more than 10% duty cycle deviation from 50%. fOSCXCLK dc — 8 MHz Crystal load capacitance(3) 3. Consult crystal vendor data sheet. CL —1 2 . 5— p F Crystal fixed capacitance(3) C1 — 2 x CL —— Crystal tuning capacitance(3) C2 — 2 x CL —— Feedback bias resistor RB 11 0 2 2 M Ω Series resistor RS 100 330 470 k Ω RC oscillator external resistor REXT See Figure 16-4 — REXT OSC1 VDD MCU 0 1 02 03 04 05 06 0 REXT (KΩ) fRCCLK (MHz) 3V 2.3V

Supply Current Characteristics MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 157

16.9 Supply Current Characteristics

Figure 16-5. Typical Run Current versus VDD (25°C) (fBus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator) Characteristic Voltage Bus Freq. (MHz) Symbol Typ Max Unit Run mode VDD supply current(1) 100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled. 3.0 2.2

1 RIDD

1.5 1.0 2.5 1.5 mA WAIT mode VDD supply current(2) 100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled. 3.0 2.2

1 WIDD

1.2 1.0 2.0 1.0 mA Stop mode VDD supply current(3) 3. Stop IDD measured with all ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as inputs with pullups enabled. 25°C 0 to 70°C –40 to 85°C 25°C with auto wake-up enabled Incremental current with LVI enabled at 25°C 3.0 SIDD 0.006 0.08 0.12 5.70 110 2.0 µA 25°C 0 to 70°C –40 to 85°C 25°C with auto wake-up enabled Incremental current with LVI enabled at 25°C 2.2 0.005 0.08 0.12 1.30 100 1.0 µA 0.5 1.5 2.5 22 . 533 . 54 VDD (V) Run I DD (mA) INT OSC w/ ADC INT OSC w/o ADC 32K CRYSTAL w/ ADC 32K CRYSTAL w/o ADC

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Figure 16-6. Typical Wait Current versus VDD (25°C) fBus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator) Figure 16-7. Typical Stop Current versus VDD (25°C) 0.2 0.4 0.6 0.8 2 2.5 3 3.5 4 VDD (V) Wait I DD (mA) INT OSC w/ ADC INT OSC w/o ADC 32K CRYSTAL w/ ADC 32K CRYSTAL w/o ADC VDD (V) Stop I DD (nA)

Analog-to-Digital (ADC) Converter Characteristics MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 159

16.10 Analog-to-Digital (ADC) Converter Characteristics

16.10.1 ADC Electrical Operating Conditions

The ADC accuracy characteristics below are guaranteed over two operating conditions as stated here.

16.10.2 ADC Performance Characteristics

Characteristic Symbol Min Max Unit Condition A ATD supply VDD 2.7 3.6 V ADC internal clock fADIC 0.008 1 MHz Ambient temperature TA TL TH °C Condition B ATD supply VDD 2.3 2.7 V ADC internal clock fADIC 86 3 k H z Ambient temperature TA 0 TH °C Characteristic Symbol Min Max Unit Comments Input voltages VADIN VSS VDD V— Resolution (1 LSB) Condition A Condition B RES 10.5 8.99 14.1 10.5 mV — Absolute accuracy Condition A (Total unadjusted error) Condition B ETUE ± 1.5 ± 2.0 LSB Includes quantization Conversion range VAIN VSS VDD V— Power-up time tADPU 16 — tADIC cycles t ADIC = 1/fADIC Conversion time tADC 16 17 tADIC cycles t ADIC = 1/fADIC Sample time(1) 1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling. tADS 5— tADIC cycles t ADIC = 1/fADIC Zero input reading(2) 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. ZADI 00 01 Hex VIN = VSS Full-scale reading(3) FADI FE FF Hex VIN = VDD Input capacitance CADI — 8 pF Not tested Input leakage(3) 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current. IIL —± 1 µA— ADC supply current (VDD = 3 V) I ADAD Typical = 0.45 mA Enabled

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16.11 Timer Interface Module Characteristics

Figure 16-8. Timer Input Timing Characteristic Symbol Min Max Unit Timer input capture pulse width tTH, tTL 2— tcyc Timer input capture period tTLTL Note(1) 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc. — tcyc Timer input clock pulse width tTCL, tTCH tcyc + 5 —n s INPUT CAPTURE RISING EDGE INPUT CAPTURE FALLING EDGE INPUT CAPTURE BOTH EDGES tTH tTL tTLTL tTLTL tTLTL tTLtTH TCLK tTCL tTCH

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16.12 Memory Characteristics

Characteristic Symbol Min Typ Max Unit RAM data retention voltage VRDR 1.3 — — V FLASH program bus clock frequency — 1 — — MHz FLASH PGM/ERASE supply voltage (VDD)V PGM/ERASE 2.7 — 3.6 V FLASH read bus clock frequency fRead (1) 1. fRead is defined as the frequency range for which the FLASH memory can be read. 0—2 M H z FLASH page erase time <1 k cycles >1 k cycles tErase 0.9 3.6 1.1 5.5 ms FLASH mass erase time tMErase 4— — m s FLASH PGM/ERASE to HVEN setup time tNVS 10 — — µs FLASH high-voltage hold time tNVH 5— — µs FLASH high-voltage hold time (mass erase) tNVHL 100 — — µs FLASH program setup time tPGS 5— — µs FLASH program time tPROG 30 — 40 µs FLASH return to read time tRCV (2) 2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 1— — m s FLASH cumulative program hv period tHV (3) 3. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum. —— 4 m s FLASH endurance(4) 4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. — 10 k 100 k — Cycles FLASH data retention time(5) 5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. — 15 100 — Y ears

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MC68HLC908QY/QT Family Data Sheet, Rev. 3 Freescale Semiconductor 163 Chapter 17 Ordering Information and Mechanical Specifications

17.1 Introduction

This section contains ordering numbers for MC68HLC908QY1, MC68HLC908QY2, MC68HLC908QY4, MC68HLC908QT1, MC68HLC908QT2, and MC69HLC908QT4. Refer to Figure 17-1 for an example of the device numbering system. In addition, this section gives the package dimensions for:  8-pin plastic dual in-line package (PDIP)  8-pin small outline integrated circuit (SOIC) package  8-pin dual flat no lead (DFN) package  16-pin PDIP  16-pin SOIC  16-pin thin shrink small outline package (TSSOP)

17.2 MC Order Numbers

Figure 17-1. Device Numbering System

17.3 Package Dimensions

Refer to the following pages for detailed package dimensions. Table 17-1. MC Order Numbers MC Order Number ADC FLASH Memory Package MCL908QY1 — 1536 bytes 16-pins PDIP , SOIC, and TSSOP MCL908QY2 Y es 1536 bytes MCL908QY4 Y es 4096 bytes MCL908QT1 — 1536 bytes 8-pins PDIP , SOIC, and DFN MCL908QT2 Y es 1536 bytes MCL908QT4 Y es 4096 bytes Temperature and package designators: Blank = 0°C to 70°C C = –40°C to 85°C P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) DT = Thin shrink small outline package (TSSOP) FQ = Dual flat no lead (DFN) M C L 9 0 8 Q Y 4 X X X E FAMILY PACKAGE DESIGNATOR TEMPERATURE RANGE Pb FREE

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