MCIMX31C_09 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005–2008. All rights reserved. Freescale Semiconductor Data Sheet: Technical Data This document contains information on a new product. Specifications and information herein are subject to change without notice. Document Number: MCIMX31C Rev. 4.2, 12/2009 MCIMX31C and MCIMX31LC
Package Information
Case 1931 19 x 19 mm, 0.8 mm Pitch
Ordering Information
See Ta ble 1 on page 3 for ordering information.
1 Introduction
The MCIMX31C and MCIMX31LC multimedia applications processors represent the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the MCIMX31C and MCIMX31LC processors and referred to singularly throughout this document as MCIMX31C. The MCIMX31LC does not include a graphics processing unit (GPU). Based on an ARM11™ microprocessor core, the MCIMX31C provides the performance with low power consumption required by modern digital devices such as: Automotive infotainment and navigation Industrial control (human interface) The MCIMX31C takes advantage of the ARM1136JF-S™ core running at 400 MHz, and is optimized for minimal power consumption using the most advanced techniques for power saving (DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the MCIMX31C and MCIMX31LC Multimedia Applications Processors for Industrial and Automotive Products
Contents
Functional Description and Application Information 4 Supply Power-Up/Power-Down Requirements and MAPBGA Production Package 473 19 x 19 mm, Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2
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MCIMX31C provides the optimal performance versus leakage current balance. The performance of the MCIMX31C is boosted by a multi-level cache system, and features peripheral devices such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a V ector Floating Point (VFP11) co-processor, and a RISC-based SDMA controller. The MCIMX31C supports connections to various types of external memories, such as DDR, NAND Flash, NOR Flash, SDRAM, and SRAM. The MCIMX31C can be connected to a variety of external devices using technology, such as high-speed USB2.0 OTG , ATA, MMC/SDIO, and compact flash.
1.1 Features
The MCIMX31C is designed for automotive and industrial markets where extended operating temperature is required. They provide low-power solutions for high-performance demanding multimedia and graphics applications. The MCIMX31C is built around the ARM11 MCU core and implemented in the 90 nm technology. The systems include the following features: Multimedia and floating-point hardware acceleration supporting: — MPEG-4 real-time encode of up to VGA at 30 fps — MPEG-4 real-time video post-processing of up to VGA at 30 fps — Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps — Video streaming (playback) of up to VGA-30 fps, 384 kbps — 3D graphics and other applications acceleration with the ARM ® tightly-coupled Vector Floating Point co-processor — On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the ARM CPU) Advanced power management — Dynamic voltage and frequency scaling — Multiple clock and power domains — Independent gating of power domains Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors) Security Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
1.2 Ordering Information
Table 1 provides the ordering information for the MCIMX31C. Revision 2.0.1 - iROM updated to support boot from USB HS and SD/MMC. Table 1. MCIMX31C and MCIMX31LC Ordering Information 1 2 Case 1931 is RoHS compliant, lead-free, MSL = 3.
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1.3 Block Diagram
Figure 1 shows the MCIMX31C simplified interface block diagram. Figure 1. MCIMX31C Simplified Interface Block Diagram
2 Functional Description and Application Information
2.1 ARM11 Microprocessor Core
codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
2.1.1 Memory System
(bi-directional), and 64-bit data write interfaces. bootstrap code and other frequently-used code and data. by overriding the boot reset sequence by a jump to a configurable address. Table 2 shows information about the MCIMX31C core in tabular form. Table 2. MCIMX31C Core Vector Floating Processor (VFP). power management capabilities.
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2.2 Module Inventory
electrical specifications and timing information for each module with external signal connections. Table 3. Digital and Analog Modules the ARM11 core and external 1-Wire devices. interface with IDE hard disc drives and AT API optical disc drives. point-to-multipoint configurations. square wave. The output of CAMP feeds the predivider. interfacing to both SPI master and slave devices. frequency and phase jitters. Note: External clock sources provide the reference frequencies. multi-peripheral debug strategy. interrupts at regular intervals with minimal processor intervention. tracing by way of ETM auxiliary I/O port.
signals that can be configured as either inputs or outputs. and interfaces to video, still image sensors, and displays. the device's external connections. from stored sample audio images. It can also generate tones. standards for randomness and non-determinism. programming. The RTC supports dates from the year 1980 to 2050. and assists with boot authentication. Table 3. Digital and Analog Modules (continued)
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provides a way of securely storing sensitive information. performing data accesses to and from the cards. to memory or between memory and on-chip peripherals. communication for e-commerce applications. inter-IC sound bus standard (I2S) and Intel AC97 standard. transmission) to provide low speed IrDA compatibility.
2 Host
1 OTG
the Cellular Modem Baseband Processor. between the Host 1 Port and the OTG transceiver.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 9
3 Signal Descriptions
Signal descriptions are in the reference manual. Special signal considerations are listed following this paragraph. The BGA ball assignment is in Section 5, “Package Information and Pinout,” on page 99. Special Signal Considerations:
- Tamper detect (GPIO1_6) Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input is asserted. The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable it until the next reset. The GPR[16] bit functions as the tamper detect enable bit. GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the tamper detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO capabilities, such as sampling through PSR or generating interrupts.) Power ready (GPIO1_5) The power ready input, GPIO1_5, should be connected to an external power management IC power ready output signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b) a no connect, internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated input and cannot be used as a general-purpose input/output. SJC_MOD SJC_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 kΩ) is allowed, but the value should be much smaller than the on-chip 100 kΩ pull-up. CE_CONTROL CE_CONTROL is a reserved input and must be externally tied to GND through a 1 kΩ resistor. M_REQUEST and M_GRANT These two signals are not utilized internally. The user should make no connection to these signals. Clock Source Select (CLKSS) The CLKSS is the input that selects the default reference clock source providing input to the DPLL. To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the reference clock source can be changed (initial setting is overwritten) by programming the PRCS bits in the CCMR.
4 Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the MCIMX31C.
4.1 Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 4 for a quick reference to the individual tables and sections. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2
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Electrical Characteristics
Stresses beyond those listed under Table 5, "Absolute Maximum Ratings," on page 10 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 7, "Operating Ranges," on page 12 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Table 6 provides the thermal resistance data for the 19 × 19 mm, 0.8 mm pitch package. Table 4. MCIMX31C Chip-Level Conditions Table 5. Absolute Maximum Ratings 1 HBM ESD classification level according to the AEC-Q100-002-Rev-D standard. 2 Integrated circuit CDM ESD classification level according to the AEC-Q100-011-Rev-B standard. 3 The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4. Table 6. Thermal Resistance Data—19 × 19 mm Package
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 11 NOTES 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Junction-to-Ambient Thermal Resistance de termined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3. Junction-to-Board thermal resistance determin ed per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 5. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Junction to Ambient (@200 ft/min) Four layer board (2s2p) R θJMA 25 °C/W 1, 2, 3 Junction to Board — RθJB 19 °C/W 1, 3 Junction to Case (Top) — RθJCtop 10 °C/W 1, 4 Junction to Package T op (natural convection) — ΨJT 2° C / W 1 , 5 Table 6. Thermal Resistance Data—19 × 19 mm Package (continued)
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Table 7 provides the operating ranges. NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. Table 7. Operating Ranges 1 Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively). is operational in State Retention (SR) mode . methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. Specifications," on page 31, are guaranteed over the entire specified voltage range. 6 In read mode, FUSE_VDD can be floated or grounded. 7 Fuses might be inadvertently blown if written to while the voltage is below this minimum. Table 8. Specific Operating Ranges for Silicon Revision 2.0 and 2.0.1
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 13 Table 9 provides information for interface frequency limits. For more details about clocks characteristics, see Section 4.3.8, “DPLL Electrical Specifications” on page 31 and Section 4.3.3, “Clock Amplifier Module (CAMP) Electrical Characteristics” on page 19. Table 10 shows the fusebox supply current parameters. 1 In read mode, FUSE_VDD should be floated or grounded. 2 Fuses might be inadvertently blown if written to while the voltage is below the minimum. Table 9. Interface Frequency
1 JT AG TCK Frequency fJTAG DC 5 10 MHz
2 CKIL Frequency 1
the internal reset synchronizer, the watchdog, and the real-time clock.
3 CKIH Frequency 2
supported for fARM ≤ 400MHz. Table 10. Fusebox Supply Current Parameters 1 The current Iprogram is during program time (tprogram).
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4.1.1 Supply Current Specifications
Table 11 shows the core current consumption for –40°C to 85°C for Silicon Revision 2.0 and 2.0.1 for the MCIMX31C. Table 11. Current Consumption for –40 °C to 85°C1, 2 for Silicon Revision 2.0 and 2.0.1
1 Typical column: TA = 25°C
2 Maximum column: TA = 85°C
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4.2 Supply Power-Up/Power-Down Requirements and Restrictions
Any MCIMX31C board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in any or all of the following situations: Cause excessive current during power-up phase Prevent the device from booting Cause irreversible damage to the MCIMX31C (worst-case scenario)
4.2.1 Powering Up
The Power On Reset (POR) pin must be kept asserted (low) throughout the power-up sequence. Power-up logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of POR. Figure 2 and Figure 3 show two options of the power-up sequence. NOTE Stages need to be performed in the order shown; however, within each stage, supplies can be powered up in any order. For example, supplies IOQVDD, NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown. CAUTION NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. Figure 2. Option 1 Power-Up Sequence for Silicon Revision 2.0 and 2.0.1
1 The board design must guarantee that supplies reach 90% level before
3 The parallel paths in the flow indicate that supply group NVCC2,
UVCC ramp-ups are independent. and should not be driven upon boot-up.
5 Raising IOQVDD before NVCC21 produces a slight increase in current
not damage the IC. Refer to Errata ID TLSbo91750 for details.
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Figure 3. Option 2 Power-Up Sequence (Silicon Revision 2.0 and 2.0.1)
4.2.2 Powering Down
- Lower the FUSE_VDD supply (when in write mode).
- Lower the remaining supplies.
4.3 Module-Level Electrical Specifications
alphabetical order by module name.
4.3.1 I/O Pad (PADIO) Electrical Specifications
main types of I/O: regular and DDR. In this document, the “Regular” type is referred to as GPIO.
4.3.1.1 DC Electrical Characteristics
12 for temperature and supply voltage ranges.
1 The board design must guarantee that supplies reach
Management IC or other means.
2 The NVCC1 supply must not precede IOQVDD by more
is powered up first, there are no restrictions.
3 Raising NVCC2, NVCC21, and NVCC22 at the same
4 FUSE_VDD should not be driven on power-up for Silicon
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 17 NOTE The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual. NVCC for Table 12 refers to NVCC1 and NVCC3–10; QVCC refers to QVCC, QVCC1, and QVCC4. Table 12. GPIO DC Electrical Parameters 1 Not a precise value. Measurements made on small sample size have shown variations of ±50% or more.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2
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The MCIMX31C I/O parameters appear in Table 13 for DDR (Double Data Rate). See Table 7, "Operating Ranges," on page 12 for temperature and supply voltage ranges. NOTE NVCC for Table 13 refers to NVCC2, NVCC21, and NVCC22.
4.3.2 AC Electrical Characteristics
Figure 4 depicts the load circuit for outputs. Figure 5 depicts the output transition time waveform. The range of operating conditions appears in Table 14 for slow general I/O, Table 15 for fast general I/O, and Table 16 for DDR I/O (unless otherwise noted). Figure 4. Load Circuit for Output Figure 5. Output Transition Time Waveform Table 13. DDR (Double Data Rate) I/O DC Electrical Parameters 1 Use of DDR Drive can result in excessive overshoot and ringing.
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4.3.3 Clock Amplifier Module (CAMP) Electrical Characteristics
This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics. Table 17 shows clock amplifier electrical characteristics. Table 14. AC Electrical Characteristics of Slow 1 General I/O 1 Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual. Table 15. AC Electrical Characteristics of Fast 1 General I/O 2 1 Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual. 2 Use of GPIO in fast mode with the associated NVCC > 1.95 V can result in excessive overshoot and ringing. Table 16. AC Electrical Characteristics of DDR I/O 1 Use of DDR Drive can result in excessive overshoot and ringing.
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4.3.4 1-Wire Electrical Specifications Figure 6 depicts the RPP timing, and Table 18 lists the RPP timing parameters. Figure 6. Reset and Presence Pulses (RPP) Timing Diagram Figure 7 depicts Write 0 Sequence timing, and Table 19 lists the timing parameters. Figure 7. Write 0 Sequence Timing Diagram Table 17. Clock Amplifier Electrical Characteristics for CKIH Input 1 VDD is the supply voltage of CAMP . See reference manual. 2 This value of the sinusoidal input will be measured through characterization. Table 18. RPP Sequence Delay Comparisons Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 21 Figure 8 depicts Write 1 Sequence timing, Figure 9 depicts the Read Sequence timing, and Table 20 lists the timing parameters. Figure 8. Write 1 Sequence Timing Diagram Figure 9. Read Sequence Timing Diagram
4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses A TA parameters. For a detailed description, refer to the ATA specification. The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface. UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. Table 19. WR0 Sequence Timing Parameters Table 20. WR1/RD Timing Parameters
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When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.
4.3.5.1 Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation of the A TA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 21 shows ATA timing parameters. Table 21. ATA Timing Parameters
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4.3.5.2 PIO Mode Timing
Figure 10 shows timing for PIO read, and Table 22 lists the timing parameters for PIO read. Figure 10. PIO Read Timing Diagram Figure 11 shows timing for PIO write, and Table 23 lists the timing parameters for PIO write. 1 Values provided where applicable. Table 22. PIO Read Timing Parameters Table 21. ATA Timing Parameters (continued)
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Figure 11. Multiword DMA (MDMA) Timing timing parameters for MDMA read and write. Table 23. PIO Write Timing Parameters
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4.3.5.3 UDMA In Timing
Figure 14 shows timing when the UDMA in transfer starts, Figure 15 shows timing when the UDMA in host terminates transfer, Figure 16 shows timing when the UDMA in device terminates transfer, and Table 25 lists the timing parameters for UDMA in burst. Figure 14. UDMA In Transfer Starts Timing Diagram Figure 15. UDMA In Host Terminates Transfer Timing Diagram
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4.3.5.4 UDMA Out Timing
Figure 17 shows timing when the UDMA out transfer starts, Figure 18 shows timing when the UDMA out host terminates transfer, Figure 19 shows timing when the UDMA out device terminates transfer, and Table 26 lists the timing parameters for UDMA out burst. Figure 17. UDMA Out Transfer Starts Timing Diagram Figure 18. UDMA Out Host Terminates Transfer Timing Diagram
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4.3.6 AUDMUX Electrical Specifications
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications.
4.3.7 CSPI Electrical Specifications
This section describes the electrical information of the CSPI.
4.3.7.1 CSPI Timing
Figure 20 and Figure 21 depict the master mode and slave mode timings of CSPI, and Table 27 lists the timing parameters. Figure 20. CSPI Master Mode Timing Diagram Figure 21. CSPI Slave Mode Timing Diagram
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4.3.8 DPLL Electrical Specifications
The three PLL’s of the MCIMX31C (MCU, USB, and Serial PLL) are all based on same DPLL design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics are provided based on measurements done for both sources—external clock source (CKIH), and FPM (Frequency Pre-Multiplier) source.
4.3.8.1 Electrical Specifications
Table 28 lists the DPLL specification. Table 27. CSPI Interface Timing Parameters 1 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. Table 28. DPLL Specifications — — 398 — Cycles of divided reference clock.
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4.3.9 EMI Electrical Specifications
This section provides electrical parametrics and timings for EMI module.
4.3.9.1 NAND Flash Controller Interface (NFC)
The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 22, Figure 23, Figure 24, and Figure 25 depict the relative timing requirements among different signals of the NFC at module level, for normal mode, and Table 29 lists the timing parameters. Figure 22. Command Latch Cycle Timing DIagram the DPTC–DVFS table, which is incorporated into operating system code. description, see the reference manual. Table 28. DPLL Specifications (continued)
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Figure 25. Read Data Latch Cycle Timing DIagram Table 29. NFC Timing Parameters1 1 The flash clock maximum frequency is 50 MHz. 2 Subject to DPLL jitter specification on T able 28, "DPLL Specifications," on page 31.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 35 NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. NOTE Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related.
4.3.9.2 Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. Input data, ECB and DTACK all captured according to BCLK rising edge time. Figure 26 depicts the timing of the WEIM module, and Table 30 lists the timing parameters. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
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Figure 26. WEIM Bus Timing Diagram Table 30. WEIM Bus Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 37 NOTE High is defined as 80% of signal value and low is defined as 20% of signal value. Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, and Figure 32 depict some examples of basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 30 for specific control parameter settings. WE8 Clock rise/fall to OE Invalid –3 3 ns WE9 Clock rise/fall to EB [x] Valid –3 3 ns WE10 Clock rise/fall to EB [x] Invalid –3 3 ns WE11 Clock rise/fall to LBA Valid –3 3 ns WE12 Clock rise/fall to LBA Invalid –3 3 ns WE13 Clock rise/fall to Output Data Valid –2.5 4 ns WE14 Clock rise to Output Data Invalid –2.5 4 ns WE15 Input Data Valid to Clock rise, FCE=0 FCE=1 2.5 — ns WE16 Clock rise to Input Data Invalid, FCE=0 FCE=1 — ns WE17 ECB setup time, FCE=0 FCE=1 6.5 3.5 — ns WE18 ECB hold time, FCE=0 FCE=1 — ns WE19 DTACK setup time1 0— n s WE20 DTACK hold time1 4.5 — ns WE21 BCLK High Level Width 2, 3 —T / 2 – 3 n s WE22 BCLK Low Level Width 2, 3 —T / 2 – 3 n s WE23 BCLK Cycle time 2 15 — ns
1 Applies to rising edge timing
2 BCLK parameters are being measured from the 50% VDD. 3 The actual cycle time is derived from the AHB bus clock frequency. Table 30. WEIM Bus Timing Parameters (continued)
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Figure 27. Asynchronous Memory Timing Diagram for Read Access—WSC=1 Figure 28. Asynchronous Memory Timing Diagram for Write Access—
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Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Write Access— Figure 32. Muxed A/D Mode Timing Diagram for Asynchronous Read Access—
4.3.9.3 ESDCTL Electrical Specifications
Table 35, and Table 36 list the timing parameters.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 41 Figure 33. SDRAM Read Cycle Timing Diagram Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters Note: CKE is high during the read/write cycle.
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SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz. NOTE The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 31 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. SD9 Data out hold time 1 tOH 1.8 — ns SD10 Active to read/write command period tRC 10 — clock 1 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see Ta ble 3 5 and Ta ble 3 6. Table 31. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 43 Figure 34. SDR SDRAM Write Cycle Timing Diagram Table 32. SDR SDRAM Write Timing Parameters
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SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 32 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. Figure 35. SDRAM Refresh Timing Diagram 1 SD11 and SD12 are determined by SDRAM controller register settings. Table 32. SDR SDRAM Write Timing Parameters (continued)
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 45 NOTE SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value. NOTE The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 33 indicates SDRAM requirements. All output signals are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. Table 33. SDRAM Refresh Timing Parameters 1 SD10 and SD11 are determined by SDRAM controller register settings.
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Figure 36. SDRAM Self-Refresh Cycle Timing Diagram will be stopped in low state. Table 34. SDRAM Self-Refresh Cycle Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 47 Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram defined as 50% of signal value. parameters are measured at maximum memory frequency. Table 35. Mobile DDR SDRAM Write Cycle Timing Parameters 1 1 T est condition: Measured using delay line 5 programmed as follows: ESDCDL Y5[15:0] = 0x0703.
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Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram defined as 50% of signal value. parameters are measured at maximum memory frequency.
4.3.10 ETM Electrical Specifications
supports TRACECLK frequencies up to 133 MHz. Figure 39 depicts the TRACECLK timings of ETM, and Table 37 lists the timing parameters. Figure 39. ETM TRACECLK Timing Diagram Table 36. Mobile DDR SDRAM Read Cycle Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 49 Figure 40 depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and Table 38 lists the timing parameters. Figure 40. Trace Data Timing Diagram
4.3.10.1 Half-Rate Clocking Mode
falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in Figure 40.
4.3.11 FIR Electrical Specifications
Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.
4.3.12 Fusebox Electrical Specifications
Table 37. ETM TRACECLK Timing Parameters Table 38. ETM Trace Data Timing Parameters Table 39. Fusebox Timing Characteristics
1 Program time for eFuse1
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4.3.13 I 2C Electrical Specifications
This section describes the electrical information of the I2C Module.
4.3.13.1 I 2C Module Timing
Figure 41 depicts the timing of I2C module. Table 40 lists the I2C module timing parameters where the I/O supply is 2.7 V . 1 Figure 41. I2C Bus Timing Diagram Table 40. I2C Module Timing Parameters—I 2C Pin I/O Supply=2.7 V 2 The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal. 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal. before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF .
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 51
4.3.14 IPU—Sensor Interfaces
4.3.14.1 Supported Camera Sensors
Table 41 lists the known supported camera sensors at the time of publication.
4.3.14.2 Functional Description
There are three timing modes supported by the IPU. Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard. This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SA V code and ends with a EA V code. In some cases, digital blanking is inserted in between EA V and SA V code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. Table 41. Supported Camera Sensors 1 2 These sensors not validated at time of publication.
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4.3.14.2.2 Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 42. Figure 42. Gated Clock Mode Timing Diagram valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
4.3.14.2.3 Non-Gated Clock Mode
inactive (states low) until valid data is going to be transmitted over the bus. Figure 43. Non-Gated Clock Mode Timing Diagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 53 The timing described in Figure 43 is that of a Motorola sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.3.14.3 Electrical Characteristics
Figure 44 depicts the sensor interface timing, and Table 42 lists the timing parameters. Figure 44. Sensor Interface Timing Diagram
4.3.15 IPU — Display Interfaces
4.3.15.1 Supported Display Components
Table 43 lists the known supported display components at the time of publication. Table 42. Sensor Interface Timing Parameters 1
1 The timing specifications for Figure 43 are referenced to the rising edge of SENS_PIX_CLK when the
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4.3.15.2 Synchronous Interfaces
4.3.15.2.1 Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 45 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously. DISPB_D3_HSYNC causes the panel to start a new line. DISPB_D3_VSYNC causes the panel to start a ne w frame. It always encompasses at least one HSYNC pulse. Table 43. Supported Display Components 1 display component suppliers. 2 These display components not validated at time of publication.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 55 DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels
4.3.15.2.2 Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse
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Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse Table 44 shows timing parameters of signals presented in Figure 46 and Figure 47. Table 44. Synchronous Display Interface Timing Parameters—Pixel Level 1 Display interface clock period immediate value. Display interface clock period average value.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 57 NOTE HSP_CLK is the High-Speed Port Clock, which is the input to the Image Processing Unit (IPU). Its frequency is controlled by the Clock Control Module (CCM) settings. The HSP_CLK frequency must be greater than or equal to the AHB clock frequency. The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF, SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC Registers. Figure 48 depicts the synchronous display interface timing for access level, and Table 45 lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the DI_DISP3_TIME_CONF Register. Figure 48. Synchronous Display Interface Timing Diagram—Access Level Table 45. Synchronous Display Interface Timing Parameters—Access Level conditions may be device specific.
2 Display interface clock down time
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4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49 depicts the Sharp HR-TFT panel interface timing, and Table 46 lists the timing parameters. The CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY , REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to The timing images correspond to straight polarity of the Sharp signals. Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
3 Display interface clock up time
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
1 DISPB_D3_CLK period
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines. SPL pulse width is fixed and aligned to the first data of the line. REV toggles every HSYNC period.
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 59
4.3.15.4 Synchronous Interface to Dual-Port Smart Displays
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are TFT LCD Panels, Electrical Characteristics” on page 55.
4.3.15.4.1 Interface to a TV Encoder, Functional Description
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 50 depicts the interface timing, The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%). The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low. The transition to the next row is marked by th e negative edge of the DISPB_D3_HSYNC signal. It remains low for a single clock cycle. The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle. — At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. — At a transition to an even field (of the same frame), they do not coincide. The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. Table 46. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
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Figure 50. TV Encoder Interface Timing Diagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 61
4.3.15.4.2 Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display Characteristics” on page 55.
4.3.15.5 Asynchronous Interfaces
4.3.15.5.1 Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces: System 80 interface — Type 1 (sampling with the chip select signal) with and without byte enable signals. — Type 2 (sampling with the read and write si gnals) with and without byte enable signals. System 68k interface — Type 1 (sampling with the chip select signal) with or without byte enable signals. — Type 2 (sampling with the read and write si gnals) with or without byte enable signals. For each of four system interfaces, there are three burst modes: 1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) of by the HBURST signal (when the MCU directly accesses the display via the slave AHB bus). For system 80 and system 68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole burst. 2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed. 3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode. Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 51, Figure 52, Figure 53, and Figure 54. These timing images correspond to active-low DISPB_D#_CS, DISPB_D#_WR and DISPB_D#_RD signals. Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
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Figure 51. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 63 Figure 52. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram
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Figure 53. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram
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Figure 55. Parallel Interface Timing Diagram—Read Wait States
4.3.15.5.2 Parallel Interfaces, Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 67 Figure 56. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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Figure 57. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 69 Figure 58. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Table 47. Asynchronous Parallel Interface Timing Parameters—Access Level
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 71 IP36 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP37 Slave device data delay 8 T racc 0 — Tdrp 9–Tlbd10–Tdicur–1.5 ns IP38 Slave device data hold time 8 T roh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP39 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns IP40 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP41 Read period 2 Tdicpr Tdicpr–1.5 Tdicpr Tdicpr+1.5 ns IP42 Write period 3 Tdicpw Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns IP43 Read down time 4 Tdicdr Tdicdr–1.5 Tdicdr Tdicdr+1.5 ns IP44 Read up time 5 Tdicur Tdicur–1.5 Tdicur Tdicur+1.5 ns IP45 Write down time 6 Tdicdw Tdicdw–1.5 Tdicdw Tdicdw+1.5 ns IP46 Write up time 7 Tdicuw Tdicuw–1.5 Tdicuw Tdicuw+1.5 ns IP47 Read time point 9 Tdrp Tdrp–1.5 Tdrp Tdrp+1.5 ns 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific.
2 Display interface clock period value for read:
3 Display interface clock period value for write:
4 Display interface clock down time for read:
5 Display interface clock up time for read:
6 Display interface clock down time for write:
7 Display interface clock up time for write:
8 This parameter is a requirement to the display connected to the IPU
9 Data read point
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Table 47. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers. 4.3.15.5.3 Serial Interfaces, Functional Description The IPU supports the following types of asynchronous serial interfaces: 3-wire (with bidirectional data line) 4-wire (with separate data input and output lines) 5-wire type 1 (with sampling RS by the serial clock) 5-wire type 2 (with sampling RS by the chip select signal) Figure 60 depicts timing of the 3-wire serial interface. The timing images correspond to active-low DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal. For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU. Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF Registers. Figure 60. 3-Wire Serial Interface Timing Diagram data lines both inside and outside the device.
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Figure 62. 5-Wire Serial Interface (Type 1) Timing Diagram
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4.3.15.5.4 Serial Interfaces, Electrical Characteristics
Figure 64 depicts timing of the serial interface. Table 48 lists the timing parameters at display access level. Figure 64. Asynchronous Serial Interface Timing Diagram Table 48. Asynchronous Serial Interface Timing Parameters—Access Level
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 77 IP56 Controls setup time for write Tdcsw Tdicuw–1.5 Tdicuw — ns IP57 Controls hold time for write Tdchw Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP58 Slave device data delay 8 Tracc 0 — Tdrp 9–Tlbd10–Tdicur–1.5 ns IP59 Slave device data hold time 8 Troh Tdrp–Tlbd–Tdicdr+1.5 — Tdicpr–Tdicdr–1.5 ns IP60 Write data setup time Tds Tdicdw–1.5 Tdicdw — ns IP61 Write data hold time Tdh Tdicpw–Tdicdw–1.5 Tdicpw–Tdicdw — ns IP62 Read period 2 Tdicpr Tdicpr–1.5 Tdicpr Tdicpr+1.5 ns IP63 Write period 3 Tdicpw Tdicpw–1.5 Tdicpw Tdicpw+1.5 ns IP64 Read down time 4 Tdicdr Tdicdr–1.5 Tdicdr Tdicdr+1.5 ns IP65 Read up time 5 Tdicur Tdicur–1.5 Tdicur Tdicur+1.5 ns IP66 Write down time 6 Tdicdw Tdicdw–1.5 Tdicdw Tdicdw+1.5 ns IP67 Write up time 7 Tdicuw Tdicuw–1.5 Tdicuw Tdicuw+1.5 ns IP68 Read time point 9 Tdrp Tdrp–1.5 Tdrp Tdrp+1.5 ns 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. 8 This parameter is a requirement to the display connected to the IPU.
9 Data read point:
10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Table 48. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
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The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD, DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.
4.3.16 Memory Stick Host Controller (MSHC)
Figure 65, Figure 66, and Figure 67 depict the MSHC timings, and Table 49 and Table 50 list the timing parameters. Figure 65. MSHC_CLK Timing Diagram Figure 66. Transfer Operation Timing Diagram (Serial)
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 79 Figure 67. Transfer Operation Timing Diagram (Parallel) parallel and serial modes, and not the MCIMX31C timing. Table 49. Serial Interface Timing Parameters 1
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4.3.17 Personal Computer Memory Card International Association
(PCMCIA) Figure 68 and Figure 69 depict the timings pertaining to the PCMCIA module, each of which is an example of one clock of strobe set-up time and one clock of strobe hold time. Table 51 lists the timing parameters. Table 50. Parallel Interface Timing Parameters 1
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 81 Figure 68. Write Accesses Timing Diagram—PSHT=1, PSST=1
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Figure 69. Read Accesses Timing Diagram—PSHT=1, PSST=1
4.3.18 PWM Electrical Specifications
Table 51. PCMCIA Write and Read Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 83
4.3.18.1 PWM Timing
Figure 70 depicts the timing of the PWM, and Table 52 lists the PWM timing characteristics. Figure 70. PWM Timing
4.3.19 SDHC Electrical Specifications
This section describes the electrical information of the SDHC.
4.3.19.1 SDHC Timing
Figure 71 depicts the timings of the SDHC, and Table 53 lists the timing parameters. Table 52. PWM Output Timing Parameters
1 System CLK frequency 1
1 CL of PWMO = 30 pF
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Figure 71. SDHC Timing Diagram
4.3.20 SIM Electrical Specifications
Table 53. SDHC Interface Timing Parameters 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 V–3.3 V. 2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 MHz–25 MHz. 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 MHz–20 MHz. 4 In card identification mode, card clock must be 100 kHz–400 kHz, voltage ranges from 2.7 V–3.3 V .
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 85 The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART. All six (or 5 in case bi directional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other. There are no required timing relationships between the signals in normal mode, but there are some in two specific cases: reset and power down sequences.
4.3.20.1 General Timing Requirements
Figure 72 shows the timing of the SIM module, and Figure 54 lists the timing parameters. Figure 72. SIM Clock Timing Diagram
4.3.20.2 Reset Sequence
4.3.20.2.1 Cards with Internal Reset
After 200 clock cycles, RX must be high. Table 54. SIM Timing Specification—High Drive Strength
1 SIM Clock Frequency (CLK) 1
2 SIM CLK Rise Time 2
2 With C = 50pF
3 SIM CLK Fall Time 3
3 With C = 50pF
4 SIM Input Transition Time (RX, SIMPD) Strans —2 5 n s
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Figure 73. Internal-Reset Card Reset Sequence
4.3.20.2.2 Cards with Active Low Reset
- After powerup, the clock signal is enabled on CLK (time T0)
- After 200 clock cycles, RX must be high.
- RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on
- RST is set High (time T1)
- RST must remain High for at least 40000 clock cycles after T1 and a response must be received
on RX between 400 and 40000 clock cycles after T1. Figure 74. Active-Low-Reset Card Reset Sequence
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 87
4.3.20.3 Power Down Sequence
Power down sequence for SIM interface is as follows: 1. SIMPD port detects the removal of the SIM Card 2. RST goes Low 3. CLK goes Low 4. TX goes Low 5. VEN goes Low Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a SIM Card removal detection or launched by the processor. Figure 75 and Table 55 show the usual timing requirements for this sequence, with Fckil = CKIL frequency value. Figure 75. SmartCard Interface Power Down AC Timing Table 55. Timing Requirements for Power Down Sequence
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4.3.21 SJC Electrical Specifications
This section details the electrical characteristics for the SJC module. Figure 76 depicts the SJC test clock input timing. Figure 77 depicts the SJC boundary scan timing, Figure 78 depicts the SJC test access port, Figure 79 depicts the SJC TRST timing, and Table 56 lists the SJC timing parameters. Figure 76. Test Clock Input Timing Diagram Figure 77. Boundary Scan (JTAG) Timing Diagram
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4.3.22 SSI Electrical Specifications
This section describes the electrical information of SSI. Note the following pertaining to timing information: All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on AUDMUX signals when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx Data (for example, during AC97 mode of operation).
4.3.22.1 SSI Transmitter Timing with Internal Clock
Figure 80 depicts the SSI transmitter timing with internal clock, and Table 57 lists the timing parameters. SJ11 TCK low to TDO high impedance — 44 ns SJ12 TRST assert time 100 — ns SJ13 TRST set-up time to TCK low 40 — ns 1 On cases where SDMA T AP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2 VM - mid point voltage
Table 56. SJC Timing Parameters (continued)
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 91 Figure 80. SSI Transmitter with Internal Clock Timing Diagram
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Table 57. SSI Transmitter with Internal Clock Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 93
4.3.22.2 SSI Receiver Timing with Internal Clock
Figure 81 depicts the SSI receiver timing with internal clock, and Table 58 lists the timing parameters. Figure 81. SSI Receiver with Internal Clock Timing Diagram
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Table 58. SSI Receiver with Internal Clock Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 95
4.3.22.3 SSI Transmitter Timing with External Clock
Figure 82 depicts the SSI transmitter timing with external clock, and Table 59 lists the timing parameters. Figure 82. SSI Transmitter with External Clock Timing Diagram
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Table 59. SSI Transmitter with External Clock Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 97
4.3.22.4 SSI Receiver Timing with External Clock
Figure 83 depicts the SSI receiver timing with external clock, and Table 60 lists the timing parameters. Figure 83. SSI Receiver with External Clock Timing Diagram Table 60. SSI Receiver with External Clock Timing Parameters
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2
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4.3.23 USB Electrical Specifications
This section describes the electrical information of the USBOTG port. The OTG port supports both serial and parallel interfaces. The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface). Figure 84 depicts the USB ULPI timing diagram, and Table 61 lists the timing parameters. Figure 84. USB ULPI Interface Timing Diagram Table 61. USB ULPI Interface Timing Specification 1 1 Timing parameters are given as viewed by transceiver side. Table 60. SSI Receiver with External Clock Timing Parameters (continued)
Package Information and Pinout MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 99
5 Package Information and Pinout
This section includes the contact assignment information and mechanical package drawing for the MCIMX31C. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX31CVMN4D, MCIMX31LCVMN4D, MCIMX31CVMN4C
100 Freescale Semiconductor
grid location for the 473 19 x 19 mm, 0.8 mm pitch package. Figure 85. Production Package: Case 1931—0.8 mm Pitch
Figure 86. Ball Map—0.8 mm Pitch
0 HSYNC L
1 These contacts are not used and must be floated by the user.
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page 103 which shows the no-connects. Table 64 on page 103 shows the device connection list for signals. Table 62. 19 x 19 BGA Ground/Power ID by Ball Grid Location
Table 63. 19 x 19 BGA No Connects 1 1 These contacts are not used and must be floated by the user. Table 64. 19 x 19 BGA Signal ID by Ball Grid Location
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Table 64. 19 x 19 BGA Signal ID by Ball Grid Location (continued)
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6 Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com.
Revision History
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.2 Freescale Semiconductor 107 MCIMX31 Chip Errata (order number MCIMX31CE) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web
7 Revision History
Table 65 summarizes revisions to the MCIMX31C/MCIMX31LC Data Sheet since the release of Rev. 3. Table 65. Revision History of the MCIMX31C/MCIMX31LC Data Sheet
4 T able 7, "Operating Ranges," on page 12 Operating Junction T emperature Range Max: changed from 100
4.1 T able 1, "MCIMX31C and MCIMX31LC Ordering
4.2 T able 1, "MCIMX31C and MCIMX31LC Ordering
MCIMX31LCJMN4D and a footnote.
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