MCIMX287CVM4B

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Technical content

Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: IMX28CEC Rev. 4, 10/2018 i.MX28

Package Information

Case MAPBGA-289, 14 x 14 mm, 0.8 mm pitch

Ordering Information

See Table on page 3 for ordering information.

1 Introduction

The i.MX28 is a low-power, high-performance applications processor optimized for the general embedded industrial and consumer markets. The core of the i.MX28 is NXP's fast, power-efficient implementation of the ARM926EJ-S™ core, with speeds of up to 454 MHz. The device is suitable for a wide range of applications, including the following:

• Human-machine interface (HMI) panels: industrial, home
• Industrial drive, PLC, I/O control display, factory robotics display, graphical remote controls
• Handheld scanners and printers
• Patient-monitoring, portable medical devices
• Smart energy meters, energy gateways
• Media phones, media gateways The integrated power management unit (PMU) on the i.MX28 is composed of a triple output DC-DC switching converter and multiple linear regulators. These provide i.MX28 Applications Processors for Consumer Products

1.2 Ordering Information and Functional

4.1 Case MAPBGA-289, 14 x 14 mm, 0.8 mm Pitch. . 59

4.2 Ground, Power, Sense, and Reference Contact

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors2 power sequencing for the device and its I/O peripherals such as memories and SD cards, as well as provide battery charging capability for Li-Ion batteries. The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for eliminating external RAM in applications with small footprint RTOS. The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and LV-DDR2, SLC and MLC NAND Flash. The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN, 10/100 Ethernet, and SD/SDIO/MMC.

1.1 Device Features

The following lists the features of the i.MX28:

• ARM926EJ-S CPU running at 454 MHz: — 16-Kbyte instruction cache and 32-Kbyte data cache — Arm embedded trace macrocell (CoreSight™ ETM9™) — Parallel JTAG interface
• 128 KBytes of integrate d low-power on-chip SRAM
• 128 KBytes of integrated mas k-programmable on-chip ROM
• 1280 bits of on-chip one-time-p rogrammable (OCOTP) ROM
• 16-bit mobile DDR (mDDR) (1.8 V) , DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR clock frequency with voltage overdrive
• Support for up to eight NAND Flas h memory devices with up to 20-bit BCH ECC
• Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI: SSP0, SSP1, SSP2, and SSP3. SSP0 and SSP1 can support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only 1-bit and 4-bit modes.
• 10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™: — Single 10/100 Ethernet with GMII/RMII or Dual 10/100 Ethernet with RMII interface — Supporting IEEE Std 1588™-compatible hardware timestamp — Supporting 50-MHz/25-MHz clock output for external Ethernet PHY
• Two 2.0B protocol-compatible Cont roller Area Network (CAN) interfaces
• One USB2.0 OTG device/ host controller and PHY
• One USB2.0 host c ontroller and PHY
• LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode
• Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access.
• SPDIF transmitter
• Dual serial audio interface (SAI F) to support full-duplex transmit and receive operations; each SAIF supports three stereo pairs

• Five application Universal As ynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with hardware flow control
• One debug UART operating at up t o 115 Kb/s using programmed I/O
• Two I 2C master/slave interfaces, up to 400 kbps
• Four 32-bit timers a nd a rotary decoder
• Eight Pulse Width Modulators (PWMs)
• Real-time clock (RTC)
• GPIO with interrupt capability
• Power Management Unit (PMU) s upports a triple output DC-DC switching converter, multiple linear regulators, battery charger, and detector.
• 16-channel Low-Resolution A/D Converter (LRADC). There are 16 physical channels but they can only be mapped to 8 virtual channels at a time.
• Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate
• 4/5-wire touchscreen controller
• Up to 8X8 keypad matrix wit h button-detect circuit
• Security features: — Read-only unique ID for Digital Rights Management (DRM) algorithms — Secure boot using 128-bit AES hardware decryption — SHA-1 and SHA256 hashing hardware — High assurance boot (HAB4)
• Offered in 289-pin Ball Grid Array (BGA)

1.2 Ordering Inform ation and Functional Part Differences

Table 1 provides the ordering information for the i.MX28. Table 1. Ordering Information

Table 2. i.MX28 Functional Differences 1 There are 16 physical channels but they can only be mapped to 8 virtual channels at a time. support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only 1-bit and 4-bit modes. Table 1. Ordering Information (continued)

1.3 Block Diagram

Figure 1 shows the simplified interface block diagram. Figure 1. i.MX28 Simplified Interface Block Diagram

Features

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors6 2F e a t u r e s Table 3 shows the device functions. Table 3. i.MX28 Functions

• NAND data width
• Number of external NANDs supported 8-bit 4 dedicated / 8 with muxing Pulse Width Modulator (PWM) 5 dedicated / 8 with muxing Application UART (AUART): Interfaces supported 4 dedicated / 5 with muxing Synchronous Serial Port (SSP): Supported through dedicated pins 3 dedicated / 4 with muxing I 2C 1 dedicated / 2 with muxing SPDIF 1 SAIF 2 FlexCAN 2 LCD interface 24 bits High-speed ADC Yes LRADC (touchscreen, keypad...) Yes Ethernet MAC and switch Up to 2 MACs with switch Universal Serial Bus (USB) 2

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 7 Table 4 describes the digital and analog modules of the device. Table 4. i.MX28 Digital and Analog Modules and from each peripheral on APBH bridge. and from each peripheral on APBX bridge. 32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.

• 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none)
• Programmable baud rates up to 3.25 MHz. This is a higher maximum baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard and previous NXP UART modules. 16-byte FIFO on Tx and 16-byte FIFO on Rx supporting auto-baud detection BCH Bit-correcting ECC accelerator Connectivity peripherals The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern NAND Flash devices. BSI Boundary Scan Interface Connectivity peripherals The boundary scan interface is provided to enable board level testing. There are five pins on the device which is used to implement the IEEE Std 1149.1™ boundary scan protocol. CLKCTRL Clock control module Clocks The clock control module, or CLKCTRL, generates the clock domains for all components in the i.MX28 system. The crystal clock or PLL clock are the two fundamental sources used to produce most of the clock domains. For lower performance and reduced power consumption, the crystal clock is selected. The PLL is selected for higher performance requirements but requires increased power consumption. In most cases, when the PLL is used as the source, a Phase Fractional Divider (PFD) can be programmed to reduce the PLL clock frequency by up to a factor of 2. DCP Data co-processor Security This module provides support for general encryption and hashing functions typically used for security functions. Because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the DMA-based approach.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors8 DFLPT Default first-level page table System control The DFLPT provides a unique method of implementing the Arm MMU first-level page table (L1PT) using a hardware-based approach. DIGCTL Digital control and on-chip RAM System control The digital control module includes sections for controlling the SRAM, the performance monitors, high-entropy pseudo-random number seed, free-running microseconds counter, and other chip control functions. DUART Debug UART Connectivity peripherals The Debug UART performs the following data conversions:

• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device EMI External memory interface Connectivity peripherals The i.MX28 supports off-chip DRAM storage through the EMI controller, which is connected to the four internal AHB/AXI busses. The EMI supports multiple external memory types, including:
• 1.8-V Mobile DDR1 (LP-DDR1)
• Standard 1.8-V DDR2
• Low Voltage 1.5-V DDR2 (LV-DDR2) ENET Ethernet MAC Controller Connectivity peripherals Ethernet MAC controller connected to the uDMA (unified DMA). Supports 10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also supports RMII or MII connectivity. FlexCAN(2) Controller area network module Connectivity peripherals The Controller Area Network (CAN) protocol is a message based protocol used for serial data. It was designed specifically for automotive but is also used in industrial control and medical applications. The serial data bus runs at 1 Mbps. GPMI General-pur- pose media interface Connectivity peripherals The General-Purpose Media Interface (GPMI) controller is a flexible NAND Flash controller with 8-bit data width, up to 50-MBps I/O speed and individual chip-select and DMA channels for up to 8 NAND devices. It also provides a interface to 20-bit BCH for ECC. HSADC High-speed ADC Connectivity peripherals The high-speed ADC block is designed to sample an analog input with 12-bit resolution and a sample rate of up to 2 Msps. The output of the HSADC block can be moved to the external memory through APBH-DMA. A typical user case of the HSADC is to work with the PWM block to drive an external linear image scanner sensor. I 2C(2) I 2C module Connectivity peripherals The I2C is a standard two-wire serial interface used to connect the chip with peripherals or host controllers. The I2C operates up to 400 kbps in either I2C master or I2C slave mode. Each I2C has a dedicated DMA channel and can also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and 10-bit device address in master mode, and has programmable 7-bit address in slave mode. ICOLL Interrupt Collector System control The Arm9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or IRQ line of the Arm9 CPU. L2 Switch 3-Port L2 Switch Network Control Programmable 3-Port Ethernet Switch with QOS

Table 4. i.MX28 Digital and Analog Modules (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 9 LCDIF LCD Interface Multimedia peripherals The LCDIF provides display data for external LCD panels from simple text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time. The LCDIF supports RGB (DOTCLK) modes as well as system mode including both VSYNC and WSYNC modes. LRADC Low resolution ADC module Connectivity peripherals The sixteen-channel 12-bit low-resolution ADC (LRADC) block is used for voltage measurement. Channels 0 – 6 measure the voltage on the seven application-dependent LRADC pins. The auxiliary channels can be used for a variety of uses, including a resistor-divider-based wired remote control, external temperature sensing, touch-screen, and other measurement functions. OCOTP Controller On-chip OTP controller Security The on-chip one-time-programmable (OCOTP) ROM serves th e functions of hardware and software capability bits, NXP operations and unique-ID, the customer-programmable cryptography key, and storage of various ROM configuration bits. PINCTRL Pin control and GPIO System control peripherals Used for general purpose input/output to external ICs. Each GPIO bank supports 32 bits of I/O. PMU Power management Unit (DC-DC) Power management system The i.MX28 integrates a comprehensive power supply subsystem, including the following features:

• One integrated DC-DC converter that supports Li-Ion battery.
• Four linear regulators directly power the supply rails from 5-V.
• Linear battery charger for Li-Ion cells.
• Battery voltage and brownout detection monitoring for VDDD, VDDA, VDDIO, VDD4P2 and 5-V supplies.
• Integrated current limiter from 5-V power source.
• Reset controller.
• System monitors for temperature and speed.
• Generates USB-Host 5-V from Li-Ion battery (using PWM).
• Support for on-the-fly transitioning between 5-V and battery power.
• VDD4P2, a nominal 4.2-V supply, is available when the i.MX28 is connected to a 5-V source and allows the DCDC to run from a 5-V source with a depleted battery.
• The 4.2-V regulated output also allows for programmable current limits: – Battery Charge current + DCDC input current < the 5-V current limit – DCDC input current (which ultimately provides current to the on-chip and off-chip loads) as the priority and battery charge current is automatically reduced if the 5-V current limit is reached PWM(8) Pulse width modulation Connectivity peripherals There are eight PWM output controllers that can be used in place of GPIO pins. Applications include HSADC driving signals and LED & backlight brightness control. Independent output control of each phase allows 0, 1, or high-impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. PXP Pixel Pipeline Multimedia The pixel pipeline (PXP) is used to perform alpha blending of graphic or video buffers with graphics data before sending to an LCD display. The PXP also supports image rotation for hand-held devices that require both portrait and landscape image support.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors10 RTC Real-time clock, alarm, watchdog Clocks The real-time clock (RTC) and alarm share a one-second pu lse time domain. The watchdog reset and millisecond counter run on a one-millisecond time domain. The RTC, alarm, and persistent bits reside in a special power domain (crystal domain) that remains powered up even when the rest of the chip is in its powered-down state. SAIF(2) Serial audio interface Connectivity peripherals SAIF provides a half-duplex serial port for communication with a variety of serial devices, including industry-standard codecs and DSPs. It supports a continuous range of sample rates from 8 kHz–192 kHz using a high-resolution fractional divider driven by the PLL. Samples are transferred to/from the FIFO through the APBX DMA interface, a FIFO service interrupt, or software polling. SPDIF SPDIF Connectivity peripherals The Sony-Philips Digital Interface Format (SPDIF) transmitter module transmits data according to the SPDIF digital audio interface standard (IEC-60958). SSP(4) Synchronous serial port Connectivity peripherals The synchronous serial port is a flexible interface for inter-IC and removable media control and communication. The SSP supports master operation of SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit and 4-bit MS modes. The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP also supports slave operation for the SPI and SSI modes. The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by the CPU through PIO registers. Each of the four SSP modules is independent of the other and can have separate SSPCLK frequencies. TIMROT Timers and Rotary Decoder Timer peripherals This module implements four timers and a rotary decoder. The timers and decoder can take their inputs from any of the pins defined for PWM, rotary encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM pins can be inputs or outputs, depending on the application. USBOTG USBHOST High-speed USB on-the-go Connectivity peripherals The USB module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification and the OTG supplement. The module has DMA capabilities for handling data transfer between internal buffers and system memory. When the OTG controller works in device mode, it can only work in FS or HS mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another for the host port.) USBPHY Integrated USB PHY Connectivity peripherals The integrated USB 2.0 PHY macrocells are capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed (FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps. The integrated PHYs provide a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB connector.

Electrical Characteristics

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2.1 Special Signal Considerations

Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4, “Package Information and Contact Assignments.” Signal descriptions are provided in the reference manual.

3 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the i.MX28. 3.1 i.MX28 Device-Level Conditions This section provides the device-level electrical characteristics for the IC.

3.1.1 DC Absolute Maximum Ratings

Table 6 provides the DC absolute maximum operating conditions. CAUTION

• Stresses beyond those listed under Table 6 may cause permanent damage to the device.

Table 5. Signal Considerations prevents the actual voltage on the pin from exceeding acceptable levels. not supply external power to this pin. See the “Power Supply” section of the reference manual for details. clock source for on-chip PLLs. provides clock source to the on-chip real-time counter circuits. RESETN This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kΩ resistor. No external pull up resistors are needed. DEBUG This pin is used for JTAG interface. DEBUG=0: JTAG interface works for boundary scan. DEBUG=1: JTAG interface works for Arm debugging. TESTMODE For NXP factory use only . Must be externally connected to GND for normal operation.

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• Exposure to absolute-maximum- rated conditions for extended periods may affect device reliability.
• Table 6 gives stress ratings only—functional operation of the device is not implied beyond the conditions indicated in Table 8. Table 7 shows the electrostatic discharge immunity.

3.1.2 DC Operating Conditions

Table 8 provides the DC recommended operating conditions. Table 6. DC Absolute Maximum Ratings 1 Application should include a Schottky diode between BATT and VDD4P2. Table 7. Electrostatic Discharge Immunity 1 HBM and CDM pass ESD testing per AEC-Q100. Table 8. Recommended Power Supply Operating Conditions

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 13 Table 9 provides the DC operating temperature conditions. Digital Supply Voltages:

• VDDIO33/VDDIO33_EMI
• VDDIO18 VDDIO33/VDDIO33_EMI/VDDIO18 3.0 1.7 3.6 1.9 V EMI Digital I/O Supply Voltage:
• DDR2/mDDR
• LVDDR2 V DDIO.EMI/VDDIO_EMIQ 1.7 1.425 1.8 1.5 1.9 1.625 V Battery / DCDC Input Voltage—BATT, DCDC_BATT BATT DCDC_BATT 3.10 3 — 4.242 V VDD5V Supply Voltage — 4.75 5.00 5.25 V Offstate Current:4
• 32-kHz RTC off, BATT = 4.2 V — — 21 47 µA
• 32-kHz RTC on, BATT = 4.2 V — — 23 51 µA 1 For optimum USB jitter performance, VDDD = 1.35 V or greater. 2 VDDD supply minimum voltage includes 75 mV guardband. 3 Tested with only the i.MX28 processor loading the MX28 PMU output rails during start up. With external loadings (for example, one DDR2 device and SD Card/NAND Flash), MX28 PMU was tested at BATT/DCDC_BATT > 3.30 V. 4 When the real-time clock is enabled, the chip consumes additional current in the OFF state to keep the crystal oscillator and the real-time clock running.

Table 9. Operating Temperature Conditions system ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC6 pin on the i.MX28. On-chip Power Dissipation based on the equations specified in note 3 below. Table 8. Recommended Power Supply Operating Conditions (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors14 Table 10 provides the recommended analog operating conditions. Table 11 shows the PSWITCH input characteristics. See the reference schematics for the recommended PSWITCH button circuitry. Table 12 shows a test case example for Run IDD. 3 Maximum Ambient Operating Temperature may be limited due to on-chip power dissipation. TA (MAX) ≤ TJ - (ΘJA x PD) where: TJ = Maximum Junction Temperature ΘJA = Package Thermal Resistance. See Section 3.2, “Thermal Characteristics.” PD = Total On-chip Power Dissipation =PVDD4P2 + PBatteryCharger + PDCDC + PLinearRegulators + PInternal. Depending on the application, some of these power dissipation terms may not apply. PVDD4P2 = VDD4P2 On-Chip Power Dissipation = (VDD5V - VDD4P2) x IDD4P2 PBatteryCharger = Battery Charger On-Chip Power Dissipation = (VDD5V - BATT) x ICHARGE PDCDC = DC-DC Converter On-Chip Power Dissipation = (BATT x DCDC Input Current) x (1 - efficiency) PLinearRegulators = Linear Regulator On-Chip Power Dissipation = (VDD5V - VDDIO) x (IDDIO + IDDA + IDDD + IDD1P5) + (VDDIO - VDDA) x (IDDA + IDDD) + (VDDA - VDDD) x IDDD + (VDDA - VDD1P5) x IDD1P5 PInternal = Internal Digital On-Chip Power Dissipation = ~VDDD x IDDD Table 10. Recommended Analog Operating Conditions Table 11. PSWITCH Input Characteristics resistor in series to limit the current). Table 12. Run IDD Test Case1,2 1 CPUCLK = 300 MHz, AHBCLK = 150 MHz. 2 Continuous read / write to the cache memory.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 15 Table 13 illustrates the power supply characteristics. Table 13. Power Supply Characteristics 4 DCDC Double FETs Enabled, Inductor Value = 15μH. higher than that specified by ensuring the load on the other outputs is well below the maximum. 6 Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V.

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3.1.2.1 Recommended Operating Conditions for S pecific Clock Targets

Table 14 through Table 17 provide the recommended operating conditions for specific clock targets. Table 14. Recommended Operating States—289-Pin BGA Package 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 15. Recommended Operating Conditions—CPU Clock (clk_p) 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 16. Recommended Operating Conditions—AHB Clock (clk_h) 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.

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3.1.3 Fusebox Supply Current Parameters

Table 18 lists the fusebox supply current parameters.

3.1.4 Interface Frequency Limits

Table 19 provides information for interface frequency limits.

3.1.5 Power Modes

Table 20 describes the core, clock, and module settings for the different power modes of the processor. Table 17. Frequency vs. Voltage for EMICLK—289-Pin BGA Package Table 18. Fusebox Supply Current Parameters 1 The current Iprogram is during program time. 2 The current Iread is present for approximately 10 ns of the read access to the 8-bit word. Table 19. Interface Frequency Limits Table 20. Power Mode Settings

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3.1.6 Supply Power-Up/Power-Down Requirements

There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power supplies are internally generated and automatically come up in a safe way. There is no special power-down sequence. 5 V or the battery can be removed at any time.

3.1.7 Reset Timing

Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing requirement on external pins. The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting RESETN. If the reset occurs while the device is only powered by the battery, then the reset kills all of the power supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the system reboots immediately. If the chip is powered by 5 V , then the reset serves to reset the digital sections of the chip. If the DCDC is operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V . Figure 2. RESETN Timing

3.2 Thermal Characteristics

• Two layer Substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.160 mm
• Core via I.D: 0.068 mm, C ore via plating 0.016 mm
• Flag: trace style with ground ba lls under the die connected to the flag OSC32K On On On DCDC Off On On RTC On On On Other Modules Off On/Off On/Off

Table 20. Power Mode Settings (continued)

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• Die Attach: 0.033 mm non-conductiv e die attach, k = 0.3 W/m K
• Mold Compound: generic mold compound, k = 0.9 W/m K

3.3 I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• DDR I/O: Mobile DDR (LPDDR1), standard 1.8 V DDR2, and low-volt age 1.5 V DDR2 (LVDDR2)
• General purpose I/O (GPIO)

3.3.1 DDR I/O DC Parameters

Table 22 shows the EMI digital pin DC characteristics. NOTE The current values and the I-V curves of the I/O DC characteristics are estimated based on an overly conservative device model. They are updated upon the measurement results of the first silicon. Table 21. Thermal Resistance Data JEDEC specification for this package. used for the case temperature. Reported value includes the thermal resistance of the interface layer. Table 22. EMI Digital Pin DC Characteristics

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors20 Table 23 shows the ON impedance of EMI drivers for different drive strengths. Table 24 shows the external devices supported by the EMI. Output voltage low (dc) VOL — 0.2 * VDDIO_EMI V Output source current (dc) LVDDR2 Mode IOH1—Low -6.2 — mA IOH—Medium -7.2 — mA IOH—High -9.7 — mA Output sink current (dc) LVDDR2 Mode IOL2—Low 5.7 — mA IOL—Medium 7.3 — mA IOL—High 10.0 — mA Output source current (dc) mDDR, DDR2 Mode IOH—Low -5.7 — mA IOH—High -7.5 — mA Output sink current (dc) mDDR, DDR2 Mode IOL—Low 5.4 — mA IOL—High 8.8 — mA 1 IOH is the output current at which the VOH specification is met. 2 IOL is the output current at which the VOL specification is met. Table 23. ON Impedance of EMI Drivers for Different Drive Strengths1 1 ON impedance of the EMI drivers are guaranteed by design and are not tested during production. Table 24. External Devices Supported by the EMI 1 Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. Table 22. EMI Digital Pin DC Characteristics (continued)

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3.3.2 GPIO I/O DC Parameters

Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. For the internal pull up setting of each pad, see the “Pin Control and GPIO” section of the reference manual. Table 25 shows the digital pin DC characteristics for GPIO in 3.3-V mode. Measurements are valid for eight pins loaded using the 4mA driver, four pins loaded using the 8mA driver, and two pins loaded using either the 12mA or 16mA driver. 2 Setting is for worst case. NXP’s EMI interface uses less powerful drivers than those typically used in mDDR devices. A possible transmission-line effect on the PC board must be suppressed by minimizing the trace length combined with NXP’s slower edge-rate drivers. The i.MX28 provides up to 16 mA programmable drive strength. However, the 16-mA mode is an experimental mode. With the 16-mA mode, the EMI function may be impaired by Simultaneous Switching Output (SSO) noise. In general, the stronger the driver mode, the noisier the on-chip power supply. NXP recommends not using a stronger driver mode than is required. Because on-chip power and ground noise is proportional to the inductance of its return path, users should make their best effort to reduce inductance between the EMI power and ground balls and the PC board power and ground planes. Table 25. Digital Pin DC Characteristics for GPIO in 3.3-V Mode

1 The conditions of the current measurements for all different drives are as follows:

Maximum corner for 3.3 V mode: 3.6 V, -40°C, fast process. Minimum corner for 3.3 V mode: 3.0 V, 105°C, slow process.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors22 Table 26 shows the digital pin DC characteristics for GPIO in 1.8 V mode.

3.4 I/O AC Timing and Parameters

Figure 3 and Figure 4 show the Driver Used for AC Simulation Testpoint and the Output Pad Transition Waveform. Figure 3. Driver Used for AC Simulation Testpoint 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O. Table 26. Digital Pin DC Characteristics for GPIO in 1.8 V Mode

1 The condition of the current measurements for all different drives are as follows:

Maximum corner for 1.8 V mode: 1.9 V, -40°C, Fast process. Minimum corner for 1.8 V mode: 1.7 V, 105°C, Slow process. 1 gpio pin (GPMI_D0) and 1 gpio_clk pin (GPMI_WRN) simultaneously loaded. 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 23 Figure 4. Output Pad Transition Waveform Table 27 shows the base GPIO AC timing and parameters. Table 27. Base GPIO

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors24 Table 28 shows the F-type GPIO AC timing and parameters. Output pad slew rate (maximum drive) Output pad slew rate (medium drive) Output pad slew rate (low drive) Input pad average hysteresis tih 1.7 V–1.9 V — 100 75 mV — 3.0 V–3.6 V — 100 50 — Table 28. F-type GPIO Table 27. Base GPIO (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 25 Output pad transition times (medium drive) Output pad transition times (low drive) Output pad slew rate (maximum drive) Output pad slew rate (medium drive) Output pad slew rate (low drive) Input pad average hysteresis tih 1.7 V–1.9 V — 100 75 mV — 3.0 V–3.6 V — 100 50 — Table 28. F-type GPIO (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors26 Table 29 shows the CLK-type GPIO AC timing and parameters. Table 29. CLK-Type GPIO

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 27

3.5 Module Timing and Electrical Parameters

3.5.1 ADC Electrical Specifications

This section describes the electrical specifications, including DC and AC information, of Low-Resolution ADC (LRADC) and High-Speed ADC (HSADC).

3.5.1.1 LRADC Electrical Specifications

Table 30 shows the electrical specifications for the LRADC.

3.5.1.2 HSADC Electrical Specification

Table 31 shows the electrical specifications for the HSADC Table 30. LRADC Electrical Specifications 1 There is no sample and hold circuit in LRADC, so it is only for DC input voltage or ones with very small slope. 2 This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time. touchscreen plate. For example, if the plate resistance is 200 ohm, the total current consumption is about 11 mA. Table 31. HSADC Electrical Specification

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors28 Maximum sampling rate (fs) —— — 2 MHz Power-up time — 1 sample cycles DC input voltage — 0.5 — VDDA-0.5 V Current Consumption VDDA —— 10 — μA DNL fin = 1 kHz — 0.5 1.2 LSB INL fin = 1kHz — 0.5 1.2 LSB Table 31. HSADC Electrical Specification (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 29

3.5.2 DPLL Electrical Specifications

This section includes descriptions of the USB PLL electrical specifications and Ethernet PLL electrical specifications.

3.5.2.1 USB PLL Electrical Specifications

The i.MX28 integrates a high-frequency USB PLL that provides the 480-MHz clock for the USB and other system blocks. Table 32 lists the USB PLL output electrical specifications.

3.5.2.2 Ethernet PLL Electrical Specifications

i.MX28 provides a 50-MHz/25-MHz output clock, called the Ethernet PLL output. Table 33 lists the Ethernet PLL output electrical specifications. Table 32. USB PLL Specifications Table 33. Ethernet PLL Specifications for the total Ethernet clock output frequency tolerance.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors30

3.5.3 EMI AC Timing

This section includes descriptions of the electrical specifications of EMI module which interfaces external DDR2 and Mobile-DDR1 (LP-DDR1) memory devices.

3.5.3.1 EMI Command and Address AC Timing

Figure 5 and Table 34 specify the timing related to the address and command pins that interfaces DDR2 and Mobile-DDR1 memory devices. Figure 5. EMI Command/Address AC Timing Table 34. EMI Command/Address AC Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 31

3.5.3.2 DDR Output AC Timing

Figure 6 and Table 35 show the DDR output AC timing defined for all DDR types: LPDDR1, standard DDR2 (1.8 V), and LVDDR2 (1.5 V). Figure 6. DDR Output AC Timing Table 35. DDR Output AC Timing Table 34. EMI Command/Address AC Timing (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors32

3.5.3.3 DDR2 Input AC Timing

Figure 7 and Table 36 show input AC timing for standard DDR2 and LVDDR2. Figure 7. DDR2 Input AC Timing Table 36. DDR2 Input AC Timing Table 35. DDR Output AC Timing (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 33

3.5.3.4 LPDDR1 Input AC Timing

Figure 8 and Table 37 show input AC timing for LPDDR1. Figure 8. LPDDR1 Input AC Timing

3.5.4 Ethernet MAC Cont roller (ENET) Timing

The ENET is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3. with transceivers operating at a voltage of 3.3 V . The following subsections describe the timing for MII and RMII modes. Table 37. LPDDR1 Input AC Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors34

3.5.4.1 ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.

3.5.4.1.1 MII Receive S ignal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,

and ENET0_RX_CLK) The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET0_RX_CLK frequency. Figure 9 shows MII receive signal timings. Table 38 describes the timing parameters (M1–M4) shown in the figure. Figure 9. MII Receive Signal Timing Diagram 1 ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

3.5.4.1.2 MII Transmit Signal Timi ng (ENET0_TXD[3:0], ENET0_TX_EN, ENET0_TX_ER,

The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%. twice the ENET0_TX_CLK frequency. Table 38. MII Receive Signal Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 35 Figure 10 shows MII transmit signal timings. Table 39 describes the timing parameters (M5–M8) shown in the figure. Figure 10. MII Transmit Signal Timing Diagram 1 ENET0_TX_EN, ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.5.4.1.3 MII Asynchronous Inputs Si gnal Timing (ENET0_CRS and ENET0_COL)

Figure 11. MII Async Inputs Timing Diagram 1 ENET0_COL has the same timing in 10-Mbit 7-wire interface mode. Table 39. MII Transmit Signal Timing Table 40. MII Asynchronous Inputs Signal Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors36

3.5.4.1.4 MII Serial Management Ch annel Timing (ENET0_MDIO and ENET0_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 12 shows MII asynchronous input timings. Table 41 describes the timing parameters (M10–M15) shown in the figure. Figure 12. MII Serial Management Channel Timing Diagram

3.5.4.2 RMII Mode Timing

ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER. Table 41. MII Serial Management Channel Timing M10 ENET0_MDC falling edge to ENET 0_MDIO output invalid (min. M11 ENET0_MDC falling edge to ENE T0_MDIO output valid (max.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 37 Figure 13 shows RMII mode timings. Table 42 describes the timing parameters (M16–M21) shown in the figure. Figure 13. RMII Mode Signal Timing Diagram

3.5.5 Coresight ETM9 AC Interface Timing

functional by using some IOMUX configurations. See the reference manual for detailed information.

3.5.5.1 TRACECLK Timing

This section describes TRACECLK timings. Table 42. RMII Signal Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors38 Figure 14 shows TRACECLK signal timings. Table 43 describes the timing parameters shown in the figure. Figure 14. TRACECLK Signal Timing Diagram

3.5.5.2 Trace Data Signal Timing

Figure 15 shows the setup and hold requirements of the trace data pins with respect to TRACECLK. Table 44 describes the timing parameters shown in the figure. Figure 15. Trace Data Signal Timing Diagram Table 43. TRACECLK Signal Timing Table 44. Trace Data Signal Timing

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 39

3.5.6 FlexCAN AC Timing

Table 45 and Table 46 show voltage requirements for the FlexCAN transceiver Tx and Rx pins. Figure 16 through Figure 19 show the FlexCAN timing, including timing of the standby and shutdown signals. Figure 16. FlexCAN Timing Diagram Table 45. Tx Pin Characteristics Table 46. Rx Pin Characteristics

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3.5.7 General-Purpose Media Interface (GPMI) Timing

The i.MX28 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 50MB/s I/O speed and individual chip-select. It supports normal timing mode, using two Flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 20, Figure 21, Figure 22 and Figure 23 depict the relative timing between GPMI signals at the module level for different operations under normal mode. Table 47 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 20. Command Latch Cycle Timing Diagram Figure 21. Address Latch Cycle Timing Diagram

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 43 Table 47. NFC Timing Parameters1 1 The Flash clock maximum frequency is 100 MHz. timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each. 3)AS minimum value could be 0, while DS/DH minimum value is 1.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors44

3.5.8 LCD AC Output El ectrical Specifications

Figure 24 depicts the AC output timing for the LCD module. Table 48 lists the LCD module timing parameters. Figure 24. LCD AC Output Timing Diagram Table 48. LCD AC Output Timing Parameters

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3.5.9 Inter IC (I 2C) Timing

The I2C module is designed to support up to 400-Kbps I2C connection compliant with I2C bus protocol. The following section describes I2C SDA and SCL signal timings. Figure 25 shows the timing of the I2C module. Table 49 describes the I2C module timing parameters (IC1– IC11) shown in the figure. Figure 25. I2C Module Timing Diagram Table 49. I2C Module Timing Parameters: 1.8 V – 3.6 V of the falling edge of I2C_SCL. 2 The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal. of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. specification) before the I2C_SCL line is released. 4 Cb = total capacitance of one bus line in pF.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors46

3.5.10 JTAG Interface Timing

Figure 26 through Figure 29 show respectively the test clock input, boundary scan, test access port, and TRST timings for the SJC. Table 50 describes the SJC timing parameters (SJ1–SJ13) indicated in the figures. Figure 26. Test Clock Input Timing Diagram Figure 27. Boundary Scan (JTAG) Timing Diagram

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors48

3.5.11 Pulse Width Modulator (PWM) Timing

Figure 30 depicts the timing of the PWM, and Table 51 lists the PWM timing characteristics. The PWM can be programmed to select one of two clock signals as its source frequency: xtal clock or hsadc clock. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin. PWM also supports MATT mode. In this mode, it can be programmed to select one of two clock signals as its source frequency, 24-MHz or 32-kHz crystal clock. For a 32-kHz source clock input, the PWM outputs the 32-kHz clock directly to PAD. Figure 30. PWM Timing Table 51. PWM Output Timing Parameter: Xtal clock

1 System CLK frequency1

Table 50. SJC Timing Parameters (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 49 Figure 31. PWM Timing Figure 32. PWM Timing Table 52. PWM Output Timing Parameter: HSADC clock Table 53. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock

1 System CLK frequency1 24 24 MHz

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors50

3.5.12 Serial Audio Interface (SAIF) AC Timing

The following subsections describe SAIF timing in two cases:

• Transmitter
• Receiver

3.5.12.1 SAIF Transmitter Timing

Figure 33 shows the timing for SAIF transmitter with internal clock, and Table 54 describes the timing parameters (SS1–SS13). Figure 33. SAIF Transmitter Timing Diagram

1 CL of PWMO = 30 pF

Table 54. SAIF Transmitter Timing Table 53. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock (continued)

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3.5.12.2 SAIF Receiver Timing

Figure 34 shows the timing for the SAIF receiver with internal clock. Table 55 describes the timing parameters (SS1–SS17) shown in the figure. Figure 34. SAIF Receiver Timing Diagram Table 55. SAIF Receiver Timing with Internal Clock Table 54. SAIF Transmitter Timing (continued)

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3.5.13 SPDIF AC Timing

SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. The following Table 56 shows SPDIF timing parameters, including the timing of the modulating Tx clock (spdif_clk) in SPDIF transmitter as shown in the Figure 35. Figure 35. spdif_clk Timing

3.5.14 Synchronous Serial Port (SSP) AC Timing

Rate) timing, MMC4.4 (Dual Date Rate) timing, MS (Memory Stick) timing, and SPI timing. Table 56. SPDIF Timing

• Skew
• Transition Rising
• Transition Falling 1.5 13.6 18.0 ns Modulating Tx clock (spdif_clk) period spclkp 81.4 — ns spdif_clk high period spclkph 65.1 — ns spdif_clk low period spclkpl 65.1 — nsspdif_clk (Input) spclkp spclkphspclkpl

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors54 3.5.14.2 MMC4.4 (Dual Data Rate) AC Timing Figure 37 depicts the timing of MMC4.4, and Table 58 lists the MMC4.4 timing characteristics. Be aware that only DATA0–DATA7 are sampled on both edges of the clock (not applicable to CMD). Figure 37. MMC4.4 Timing

3.5.14.3 MS (Memory Stick) AC Timing

Sony Memory Stick version 1.x and Memory Stick PRO. Table 58. MMC4.4 Interface Timing Specification

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors56 Figure 40. MS Parallel Transfer Mode Timing Diagram Table 59. MS Serial Transfer Timing Parameters Table 60. MS Parallel Transfer Timing Parameters

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 57

3.5.14.4 SPI AC Timing

Figure 41 depicts the master mode and slave mode timings of the SPI, and Table 61 lists the timing parameters. Figure 41. SPI Interface Timing Diagram Table 61. SPI Interface Timing Parameters Table 60. MS Parallel Transfer Timing Parameters (continued)

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors58

3.5.15 UART (UARTAPP an d DebugUART) AC Timing

This section describes the UART module AC timing which is applicable to both UARTAPP and DebugUART.

3.5.15.1 UART Transmit Timing

Figure 39 shows the UART transmit timing, showing only eight data bits and one stop bit. Table 62 describes the timing parameter (UA1) shown in the figure. Figure 42. UART Transmit Timing Diagram

3.5.15.2 UART Receive Timing

describes the timing parameter (UA2) shown in the figure. Figure 43. UART Receive Timing Diagram Table 62. UART Transmit Timing Parameters 2 Tref_clk: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz).

4 Package Information and Contact Assignments

• All dimensions are in millimeters.
• Dimensioning and toleran cing per ASME Y14.5M-1994.
• Maximum solder bump diameter measured parallel to datum A.
• Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.
• Parallelism measurement excludes any effect of mark on top sur face of package.

Table 63. UART Receive Timing Parameters

Figure 44 shows the i.MX28 production package. Figure 44. i.MX28 Production Package

4.2 Ground, Power, Sense, and R eference Contact Assignments

Table 64 shows power and ground contact assignments for the MAPBGA package. Table 64. MAPBGA Power and Ground Contact Assignments

4.3 Signal Contact Assignments

Table 65 lists the i.MX287 MAPBGA package signal contact assignments. Table 65. i.MX287 MAPBGA Contact Assignments Table 64. MAPBGA Power and Ground Contact Assignments (continued)

Table 65. i.MX287 MAPBGA Contact Assignments (continued)

Table 66 shows the i.MX280 MAPBGA ball map. Table 66. 289-Pin i.MX280 MAPBGA Ball Map

Table 66. 289-Pin i.MX280 MAPBGA Ball Map (continued)

Table 67 shows the i.MX283 MAPBGA ball map. Table 67. 289-Pin i.MX283 MAPBGA Ball Map

Table 67. 289-Pin i.MX283 MAPBGA Ball Map (continued)

Table 68 shows the i.MX286 MAPBGA ball map. Table 68. 289-Pin i.MX286 MAPBGA Ball Map

Table 68. 289-Pin i.MX286 MAPBGA Ball Map (continued)

Table 69 shows the i.MX287 MAPBGA Ball Map. Table 69. 289-Pin i.MX287 MAPBGA Ball Map

Table 69. 289-Pin i.MX287 MAPBGA Ball Map (continued)

Revision History

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors72

5 Revision History

Table 70 summarizes revisions to this document. Table 70. Document Revision History Rev. 4 10/2018 • Table 1, "Ordering Information," on page 3”: Added “C” suffix part numbers.

• Table 37, "LPDDR1 Input AC Timing," on page 33: Corrected table tile from “DDR2” to “LPDDR1” Input AC Timing. Rev. 3 07/2012 • Removed the Power Consumption table, and added Table 12, "Run IDD Test Case,," on page 14.
• Updated Table 23, "ON Impedance of EMI Drivers for Different Drive Strengths," on page 20. Rev. 2 03/2012 • In Section 1.1, “Device Features:” —Updated synchronous serial ports (SSP) support for the i.MX28 —Updated Ethernet support for the i.MX28 —Updated Low-Resolution A/D Converter (LRADC) support for the i.MX28
• Updated Table 2, "i.MX28 Functional Differences," on page 4.
• In Table 6, "DC Absolute Maximum Ratings," on page 12, removed the PSWITCH parameter as this parameter is explained in detail in Table 11.
• In Table 8, "Recommended Power Supply Operating Conditions," on page 12: —Updated two parameters: “VDD5V Supply Voltage” and “Offstate Current” —Updated the third footnote
• In Table 9, "Operating Temperature Conditions," on page 13, added a new footnote in the “Parameter” column.
• In Table 13, "Power Supply Characteristics," on page 15, updated the “VDD4P2 Output Current Limit Accuracy” parameter.
• In Section 3.1.2.1, “Recommended Operating Conditions for Specific Clock Targets:” —Removed the “System Clocks” table —Updated two TBD values in the first row of Table 14 —Removed the first row in Table 15 —Removed the first row in Table 16
• In Table 20, "Power Mode Settings," on page 17, changed the second column name from “Deep Sleep” to “Offstate.”
• Updated Table 22, "EMI Digital Pin DC Characteristics," on page 19.
• In Table 30, "LRADC Electrical Specifications," on page 27, updated the “DC Electrical Specification” section.
• In Table 31, "HSADC Electrical Specification," on page 27, updated the “DC Electrical Specification” section.
• In Section 3.5.5, “Coresight ETM9 AC Interface Timing,” updated the first paragraph.
• In Section 3.5.5.1, “TRACECLK Timing,” corrected the title of Table 43.
• In Section 3.5.5.2, “Trace Data Signal Timing,” corrected the titles of Figure 15 and Table 44.

i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018 NXP Semiconductors 73 Rev. 1 04/2011 • Updated Section 1.1, “Device Features.”

• Added Section 3.2, “Thermal Characteristics.”
• In Table 1, "Ordering Information," on page 3, added two rows.
• Updated Table 2, "i.MX28 Functional Differences," on page 4.
• Updated Table 4, "i.MX28 Digital and Analog Modules," on page 7.
• In Table 8, "Recommended Power Supply Operating Conditions," on page 12, updated BATT row.
• Updated Table 9, "Operating Temperature Conditions," on page 13.
• Replaced the term “DC Characteristics” with “Power Consumption” in the title and introduction of the Power Consumption table. Also changed Dissipation to Consumption in first row.
• Updated Table 25, "Digital Pin DC Characteristics for GPIO in 3.3-V Mode," on page 21.
• Updated Table 26, "Digital Pin DC Characteristics for GPIO in 1.8 V Mode," on page 22.
• Updated and added a footnote to Table 33, "Ethernet PLL Specifications," on page 29.
• Updated DDR1 row of Table 34, "EMI Command/Address AC Timing," on page 30.
• Added Section 4.4, “i.MX280 Ball Map.”
• In Section 4.5, “i.MX283 Ball Map,” updated Figure 67. Rev. 0 09/2010 Initial release.

Table 70. Document Revision History (continued)

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