MCIMX283DVM4B

IMX28CEC FREESCALE | Alldatasheet

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Technical content

Data Sheet: Technical Data Document Number: IMX28CEC Rev. 1, 04/2011 i.MX28

Package Information

Case 5284 14 x 14 mm, 0.8 mm Pitch

Ordering Information

See Table 1 on page 3 for ordering information. © Freescale Semiconductor, Inc., 2011. All rights reserved.

1 Introduction

The i.MX28 is a low-power, high-performance applications processor optimized for the general embedded industrial and consumer markets.The core of the i.MX28 is Freescale's fast, power-efficient implementation of the ARM926EJ-S™ core, with speeds of up to 454 MHz. The device is suitable for a wide range of applications, including the following:

• Human-machine interface (HMI) panels: industrial, home
• Industrial drive, PLC, I/O control display, factory robotics display, graphical remote controls
• Handheld scanners and printers
• Patient-monitoring, portable medical devices
• Smart energy meters, energy gateways
• Media phones, media gateways The integrated power management unit (PMU) on the i.MX28 is composed of a triple output DC-DC switching converter and multiple linear regulators. These provide power sequencing for the device and its I/O peripherals such as memories and SD cards, as well as provide battery charging capability for Li-Ion batteries. i.MX28 Applications Processors Data Sheet for Consumer Products Silicon Version 1.2

Contents

1.2. Ordering Information & Functional Part Differences 3 4.1. 289-Ball MAPBGA—Case 14 x 14 mm, 4.2. Ground, Power, Sense, and Reference Contact

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

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The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for eliminating external RAM in applications with small footprint RTOS. The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and LV-DDR2, SLC and MLC NAND Flash. The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG , CAN, 10/100 Ethernet, and SD/SDIO/MMC.

1.1 Device Features

The following lists the features of the i.MX28:

• ARM926EJ-S CPU running at 454 MHz: — 16-Kbyte instruction cache and 32-Kbyte data cache — ARM embedded trace macr ocell (CoreSight™ ETM9™) — Parallel JTAG interface
• 128 KBytes of integrated low-power on-chip SRAM
• 128 KBytes of integrated ma sk-programmable on-chip ROM
• 1280 bits of on-chip one-ti me-programmable (OCOTP) ROM
• 16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR clock frequency with voltage overdrive
• Support for up to eight NAND flash memory devices with up to 20-bit BCH ECC
• Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI. Two can be used for SDIO/MMC/MS interfaces (supports SD2.0, eMMC4.4 and MSPro), and all can be used for the SPI interface.
• 10/100-Mbps Ethernet MAC compat ible with IEEE Std 802.3™, supporting IEEE Std 1588™-compatible hardware timestam p. Also supports 50-MHz/25-MHz clock output for external Ethernet PHY .
• Two 2.0B protocol-compatible Contro ller Area Network (CAN) interfaces
• One USB2.0 OTG device/ host controller and PHY
• One USB2.0 host controller and PHY
• LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode
• Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access.
• SPDIF transmitter
• Dual serial audio interface (SAI F) to support full-duplex transmit and receive operations; each SAIF supports three stereo pairs
• Five application Universal Asynchronous Receiver -Transmitters (UARTs), up to 3.25 Mbps with hardware flow control
• One debug UART operating at up to 115 Kb/s using programmed I/O
• T w o I 2C master/slave interfaces, up to 400 kbps
• Four 32-bit timers and a rotary decoder

• Eight Pulse Width Modulators (PWMs)
• Real-time clock (RTC)
• GPIO with interrupt capability
• Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple linear regulators, battery charger, and detector.
• 16-channel Low-Resolution A/D Converter (LRADC)
• 4/5-wire touchs creen controller
• Up to 8X8 keypad matrix wi th button-detect circuit
• Single channel High Speed A/D Convert er (HSADC), up to 2 Msps data rate
• Security features: — Read-only unique ID for Digital Rights Management (DRM) algorithms — Secure boot using 128-bit AES hardware decryption — SHA-1 and SHA256 hashing hardware — High assurance boot (HAB4)
• Offered in 289-pin Ball Grid Array (BGA)

1.2 Ordering Information & F unctional Part Differences

Table 1 provides the ordering information for the i.MX28. Table 1. Ordering Information Table 2. i.MX28 Functional Differences

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Table 2. i.MX28 Functional Differences (continued)

1.3 Block Diagram

Figure 1 shows the simplified interface block diagram. Figure 1. i.MX28 Simplified Interface Block Diagram Table 3 shows the device functions. Table 3. i.MX28 Functions

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Table 4 describes the digital and analog modules of the device. Table 4. i.MX28 Digital and Analog Modules and from each peripheral on APBX bridge. 32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM. Table 3. i.MX28 Functions (continued)

as protecting data and resources stored on modern NAND flash devices. The boundary scan interface is provided to enable board level testing. 1149.1™ boundary scan protocol. performance and reduced power consumption, the crystal clock is selected. PLL clock frequency by up to a factor of 2. between memory blocks than the DMA-based approach. first-level page table (L1PT) using a hardware-based approach. free-running microseconds counter, and other chip control functions. supports RMII or MII connectivity. interface to 20-bit BCH for ECC. Table 4. i.MX28 Digital and Analog Modules (continued)

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mode including both VSYNC and WSYNC modes.

 One integrated DC-DC converter that supports Li-Ion battery.  Four linear regulators directly power the supply rails from 5-V.  Linear battery charger for Li-Ion cells. VDDIO, VDD4P2 and 5-V supplies.  Integrated current limiter from 5-V power source.  System monitors for temperature and speed.  Generates USB-Host 5-V from Li-Ion battery (using PWM).  Support for on-the-fly transitioning between 5-V and battery power. non-overlapping portions for differential drive applications. Clocks The real-time clock (RTC) and alarm share a one-second pulse time domain. chip is in its powered-down state.

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2.1 Special Signal Considerations

independent of the other and can have separate SSPCLK frequencies. pins can be inputs or outputs, depending on the application. data transfer between internal buffers and system memory. (FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps. USB_DN pins connect directly to a USB connector. Table 5. Signal Considerations circuitry prevents the actual voltage on the pin from exceeding acceptable levels. should not supply external power to this pin. See the “Power Supply” section of the reference manual for details.

3 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the i.MX28. This section provides the device-level electrical characteristics for the IC.

3.1.1 DC Absolute Maximum Ratings

Table 7 provides the DC absolute maximum operating conditions.

• Stresses beyond those listed under Table 7 may cause permanent damage to the device.
• Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
• Table 6 gives stress ratings only—functi onal operation of the device is not implied beyond the conditions indicated in Table 8. DCDC_BATTERY This pin is an input of i.MX28 that provides supply to the DCDC converter. It should be connected to the battery with minimal resistance. See the “Power Supply” section of the reference manual for details. XTALI XTALO These analog pins are connected to an external 24MHz crystal circuit. This crystal provides the clock source for on-chip PLLs. RTC_XTALO RTC_XTALI These analog pins are connected to an external 32.768/32.0 kHz crystal circuit. This crystal provides clock source to the on-chip real-time counter circuits. RESETN This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kohm resistor. No external pull up resistors are needed. DEBUG This pin is used for JTAG interface. DEBUG=0: JTAG interface works for boundary scan. DEBUG=1: JTAG interface works for ARM debugging. TESTMODE For Freescale factory use only. Must be ex ternally connected to GND for normal operation.

Table 6. DC Absolute Maximum Ratings Table 5. Signal Considerations (continued)

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Table 7 shows the electrostatic discharge immunity. Note that HBM and CDM pass ESD testing per AEC-Q100. 2 Application should include a Schottky diode between BATT and VDD4P2. Table 7. Electrostatic Discharge Immunity Table 6. DC Absolute Maximum Ratings (continued)

3.1.2 DC Operating Conditions

Table 8 provides the DC recommended operating conditions. Table 9 provides the DC operating temperature conditions. Table 8. Recommended Power Supply Operating Conditions 1 For optimum USB jitter performance, VDDD = 1.35 V or greater. 2 VDDD supply minimum voltage includes 75 mV guardband. 3 Tested with only the i.MX28 processor loading the MX28 PMU output rails during start up. the real-time clock running. Table 9. Operating Temperature Conditions system ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC6 pin on the i.MX28.

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Table 10 provides the recommended analog operating conditions. Table 12 shows the power consumption. on the application, some of these power dissipation terms may not apply. Table 10. Recommended Analog Operating Conditions Table 11. PSWITCH Input Characteristics in series to limit the current). Table 12. Power Consumption

Table 13 illustrates the power supply characteristics. Table 13. Power Supply Characteristics 4 DCDC Double FETs Enabled, Inductor Value = 15μH. higher than that specified by ensuring the load on the other outputs is well below the maximum. 6 Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V.

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3.1.2.1 Recommended Operating Conditions for Specific Clock Targets

Table 14 through Table 18 provide the recommended operating conditions for specific clock targets. Table 14. System Clocks Table 15. Recommended Operating States—289-Pin BGA Package 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 16. Recommended Operating Conditions—CPU Clock (clk_p) 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.

3.1.3 Fusebox Supply Current Parameters

Table 19 lists the fusebox supply current parameters.

3.1.4 Interface Frequency Limits

Table 20 provides information for interface frequency limits. Table 17. Recommended Operating Conditions—AHB Clock (clk_h) 1 All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value. Table 18. Frequency vs. Voltage for EMICLK—289-Pin BGA Package Table 19. Fusebox Supply Current Parameters 1 The current Iprogram is during program time. 2 The current Iread is present for approximately 10 ns of the read access to the 8-bit word. Table 20. Interface Frequency Limits

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3.1.5 Power Modes

Table 21 describes the core, clock, and module settings for the different power modes of the processor.

3.1.6 Supply Power-Up/Power-Down Requirements

supplies are internally generated and automatically come up in a safe way. There is no special power-down sequence. 5 V or the battery can be removed at any time.

3.1.7 Reset Timing

requirement on external pins. operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V . Figure 2. RESETN Timing Table 21. Power Mode Settings

3.2 Thermal Characteristics

• Two layer Substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.160 mm
• Core via I.D: 0.068 mm, Core via plating 0.016 mm
• Flag: trace style with ground balls under the die connected to the flag
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold Compound: generic mold compound, k = 0.9 W/m K

3.3 I/O DC Parameters

• DDR I/O: Mobile DDR (LPDDR1), standa rd 1.8 V DDR2, and low-voltage 1.5 V DDR2 (LVDDR2)
• General purpose I/O (GPIO)

Table 22. Thermal Resistance Data JEDEC specification for this package. used for the case temperature. Reported value includes the thermal resistance of the interface layer.

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3.3.1 DDR I/O DC Parameters

Table 23 shows the EMI digital pin DC characteristics. upon the measurement results of the first silicon. Table 24 shows the ON impedance of EMI drivers for different drive strengths. Table 23. EMI Digital Pin DC Characteristics 1 IOH is the output current at which the VOH specification is met. 2 IOL is the output current at which the VOL specification is met. Table 24. ON Impedance of EMI Drivers for Different Drive Strengths

Table 25 shows the external devices supported by the EMI.

3.3.2 GPIO I/O DC Parameters

internal pull up setting of each pad, see the “Pin Control and GPIO” section of the reference manual. either the 12mA or 16mA driver. Table 25. External Devices Supported by the EMI 1 Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading. Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode Table 24. ON Impedance of EMI Drivers for Different Drive Strengths (continued)

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1 The conditions of the current measurements for all different drives are as follows:

Maximum corner for 3.3 V mode: 3.6 V, -40°C, fast process. 8 gpio pins (LCD_D0-D7) and 2 gpio_clk pins (LCD_DOTCLK and LCD_WR_RWN) simultaneously loaded. 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O. Table 26. Digital Pin DC Characteristics for GPIO in 3.3-V Mode (continued)

Table 27 shows the digital pin DC characteristics for GPIO in 1.8 V mode. Table 27. Digital Pin DC Characteristics for GPIO in 1.8 V Mode

1 The condition of the current measurements for all different drives are as follows:

Maximum corner for 1.8 V mode: 1.9 V, -40°C, Fast process. Minimum corner for 1.8 V mode: 1.7 V, 105°C, Slow process. 1 gpio pin (GPMI_D0) and 1 gpio_clk pin (GPMI_WRN) simultaneously loaded. 2 See the i.MX28 reference manual for detailed pull-up configuration of each I/O.

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3.4 I/O AC Timing and Parameters

Figure 3. Driver Used for AC Simulation Testpoint Figure 4. Output Pad Transition Waveform Table 28 shows the base GPIO AC timing and parameters. Table 28. Base GPIO

Table 28. Base GPIO (continued)

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Table 29 shows the F-type GPIO AC timing and parameters. Table 29. F-type GPIO

Table 30 shows the CLK-type GPIO AC timing and parameters. Table 30. CLK-Type GPIO Table 29. F-type GPIO (continued)

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3.5 Module Timing and Electrical Parameters

3.5.1 ADC Electrical Specifications

ADC (LRADC) and High-Speed ADC (HSADC).

3.5.1.1 LRADC Electrical Specifications

Table 31 shows the electrical specifications for the LRADC. Table 31. LRADC Electrical Specifications 1 There is no sample and hold circuit in LRADC, so it is only for DC input voltage or ones with very small slope. Table 30. CLK-Type GPIO (continued)

3.5.1.2 HSADC Electrical Specification

3.5.2 DPLL Electrical Specifications

3.5.2.1 USB PLL Electrical Specifications

Table 33 lists the USB PLL output electrical specifications. 2 This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time. touchscreen plate. For example, if the plate resistance is 200 ohm, the total current consumption is about 11 mA. Table 32. HSADC Electrical Specification Table 33. USB PLL Specifications

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3.5.2.2 Ethernet PLL Electrical Specifications

i.MX28 provides a 50-MHz/25-MHz output clock, called the Ethernet PLL output. Table 34 lists the Ethernet PLL output electrical specifications. Table 34. Ethernet PLL Specifications for the total Ethernet clock output frequency tolerance.

3.5.3 EMI AC Timing

DDR2 and Mobile-DDR1 (LP-DDR1) memory devices.

3.5.3.1 EMI Command & Address AC Timing

and Mobile-DDR1 memory devices. Figure 5. EMI Command/Address AC Timing Table 35. EMI Command/Address AC Timing

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3.5.3.2 DDR Output AC Timing

Figure 6. DDR Output AC Timing Table 36. DDR Output AC Timing Table 35. EMI Command/Address AC Timing (continued)

3.5.3.3 DDR2 Input AC Timing

Figure 7 and Table 37 show input AC timing for standard DDR2 and LVDDR2. Figure 7. DDR2 Input AC Timing Table 37. DDR2 Input AC Timing Table 36. DDR Output AC Timing (continued)

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3.5.3.4 LPDDR1 Input AC Timing

Figure 8 and Table 38 show input AC timing for LPDDR1. Figure 8. LPDDR1 Input AC Timing

3.5.4 Ethernet MAC Controller (ENET) Timing

The ENET is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3. with transceivers operating at a voltage of 3.3 V . The following subsections describe the timing for MII and RMII modes. Table 38. DDR2 Input AC Timing

3.5.4.1 ENET MII Mode Timing

3.5.4.1.1 MII Receive Sig nal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,

Figure 9. MII Receive Signal Timing Diagram 1 ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

3.5.4.1.2 MII Transmit Signal Timi ng (ENET0_TXD[3:0], ENET0_TX_EN,

The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%. twice the ENET0_TX_CLK frequency. Table 39. MII Receive Signal Timing

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Figure 10. MII Transmit Signal Timing Diagram 1 ENET0_TX_EN, ENET0_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.5.4.1.3 MII Asynchronous Inputs Signal Timing (ENET0_CRS and ENET0_COL)

Figure 11. MII Async Inputs Timing Diagram 1 ENET0_COL has the same timing in 10-Mbit 7-wire interface mode. Table 40. MII Transmit Signal Timing Table 41. MII Asynchronous Inputs Signal Timing

3.5.4.1.4 MII Serial M anagement Channel Timing (ENET0_MDIO and ENET0_MDC)

Figure 12. MII Serial Management Channel Timing Diagram

3.5.4.2 RMII Mode Timing

ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER. Table 42. MII Serial Management Channel Timing M10 ENET0_MDC falling edge to ENET0_MDIO output invalid (min. M11 ENET0_MDC falling edge to ENET0_MDIO output valid (max.

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Figure 13. RMII Mode Signal Timing Diagram

3.5.5 Coresight ETM9 AC Interface Timing

3.5.5.1 TRACECLK Timing

This section describes TRACECLK timings. Table 43. RMII Signal Timing

Figure 14. TRACECLK Signal Timing Diagram

3.5.5.2 Trace Data Signal Timing

Figure 15 shows the setup and hold requirements of the trace data pins with respect to TRACECLK. Table 45 describes the timing parameters shown in the figure. Figure 15. MII Transmit Signal Timing Diagram Table 44. MII Receive Signal Timing Table 45. MII Transmit Signal Timing

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3.5.6 FlexCAN AC Timing

Table 46 and Table 47 show voltage requirements for the FlexCAN transceiver Tx and Rx pins. Figure 16. FlexCAN Timing Diagram Table 46. Tx Pin Characteristics Table 47. Rx Pin Characteristics

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3.5.7 General-Purpose Media Interface (GPMI) Timing

50MB/s I/O speed and individual chip select. under normal mode. Table 48 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 20. Command Latch Cycle Timing Diagram Figure 21. Address Latch Cycle Timing Diagram

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Table 48. NFC Timing Parameters1 1 The Flash clock maximum frequency is 100 MHz. timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each. 3)AS minimum value could be 0, while DS/DH minimum value is 1.

3.5.8 LCD AC Output Electrical Specifications

Figure 24. LCD AC Output Timing Diagram Table 49. LCD AC Output Timing Parameters

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3.5.9 Inter IC (I 2C) Timing

The I2C module is designed to support up to 400-Kbps I2C connection compliant with I2C bus protocol. The following section describes I2C SDA and SCL signal timings. (IC1–IC11) shown in the figure. Figure 25. I2C Module Timing Diagram Table 50. I2C Module Timing Parameters: 1.8 V – 3.6 V of the falling edge of I2C_SCL. 2 The maximum IC4 has to be met only if the device does not stretch the LOW period (ID no IC5) of the I2C_SCL signal. of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. specification) before the I2C_SCL line is released. 4 Cb = total capacitance of one bus line in pF .

3.5.10 JTAG Interface Timing

Figure 26. Test Clock Input Timing Diagram Figure 27. Boundary Scan (JTAG) Timing Diagram

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Figure 28. Test Access Port Timing Diagram Figure 29. TRST Timing Diagram Table 51. SJC Timing Parameters

3.5.11 Pulse Width Modulator (PWM) Timing

Figure 30 depicts the timing of the PWM, and Table 52 lists the PWM timing characteristics. output is available at the pulse width modulator output (PWMO) external pin. outputs the 32-KHz clock directly to PAD. Figure 30. PWM Timing

1 VM – mid point voltage

Table 52. PWM Output Timing Parameter: Xtal clock

1 System CLK frequency 1

1 CL of PWMO = 30 pF

Table 51. SJC Timing Parameters (continued)

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Figure 31. PWM Timing Figure 32. PWM Timing Table 53. PWM Output Timing Parameter: HSADC clock

3.5.12 Serial Audio Interface (SAIF) AC Timing

• Transmitter
• Receiver

3.5.12.1 SAIF Transmitter Timing

Figure 33. SAIF Transmitter Timing Diagram Table 54. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock

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3.5.12.1.5 SAIF Receiver Timing

parameters (SS1–SS17) shown in the figure. Figure 34. SAIF Receiver Timing Diagram Table 55. SAIF Transmitter Timing

3.5.13 SPDIF AC Timing

a clock that is twice the bit rate of the data signal. (spdif_clk) in SPDIF transmitter as shown in the Figure 35. Figure 35. spdif_clk Timing Table 56. SAIF Receiver Timing with Internal Clock Table 57. SPDIF Timing

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3.5.14 Synchronous Serial Port (SSP) AC Timing

Rate) timing, MMC4.4 (Dual Date Rate) timing, MS (Memory Stick) timing, and SPI timing. Figure 36 depicts the timing of SD/MMC4.3, and Table 58 lists the SD/MMC4.3 timing characteristics. Figure 36. SD/MMC4.3 Timing Table 58. SD/MMC4.3 Interface Timing Specification

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3.5.14.3 MS (Memory Stick) AC Timing

Sony Memory Stick version 1.x and Memory Stick PRO. Memory Stick timing characteristics. Figure 38. MS Clock Time Waveforms Figure 39. MS Serial Transfer Mode Timing Diagram

Figure 40. MS Parallel Transfer Mode Timing Diagram Table 60. MS Serial Transfer Timing Parameters Table 61. MS Parallel Transfer Timing Parameters

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3.5.14.4 SPI AC Timing

Figure 41. SPI Interface Timing Diagram Table 62. SPI Interface Timing Parameters Table 61. MS Parallel Transfer Timing Parameters (continued)

3.5.15 UART (UARTAPP and DebugUART) AC Timing

3.5.15.1 UART Transmit Timing

describes the timing parameter (UA1) shown in the figure. Figure 42. UART Transmit Timing Diagram

3.5.15.2 UART Receive Timing

describes the timing parameter (UA2) shown in the figure. Figure 43. UART Receive Timing Diagram Table 63. UART Transmit Timing Parameters 2 Tref_clk: The period of UART reference clock ref_clk (which is APBX clock = 24 MHz).

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4 Package Information and Contact Assignments

• All dimensions are in millimeters.
• Dimensioning and toleranc ing per ASME Y14.5M-1994.
• Maximum solder bump diameter measured parallel to datum A.
• Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.
• Parallelism measurement excludes any eff ect of mark on top surface of package.

Table 64. UART Receive Timing Parameters

Figure 44 shows the i.MX28 production package. Figure 44. zzxzi.MX28 Production Package

4.2 Ground, Power, Sense, and Reference Contact Assignments

Table 65 shows power and ground contact assignments for the MAPBGA package. Table 65. MAPBGA Power and Ground Contact Assignments

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4.3 Signal Contact Assignments

Table 66 lists the i.MX287 MAPBGA package signal contact assignments. Table 66. MAPBGA Contact Assignments Table 65. MAPBGA Power and Ground Contact Assignments (continued)

Table 66. MAPBGA Contact Assignments (continued)

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Figure 45 shows the i.MX287 MAPBGA Ball Map. Figure 45. 289-pin i.MX287 MAPBGA Ball Map

2 VSS VSS VSS VDDD

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Figure 46 shows the i.MX286 MAPBGA ball map. Figure 46. 289-pin i.MX286 MAPBGA Ball Map

Figure 47 shows the i.MX283 MAPBGA ball map. Figure 47. 289-pin i.MX283 MAPBGA Ball Map

3 USB1DP VSS USB0D

3 VDD5V E

8 VDDD VDDD VDDD EMI_D1

8 VDDD VDDD VDDD VDDIO_

3 VSS VSS VSS VSS EMI_D1

9 VSS EMI_D1

3 VSS VSS VDDIO_

1 VSS EMI_D

5 LCD_RS NC LCD_RE

3 VSS NC GPMI_R

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Figure 48 shows the i.MX280 MAPBGA ball map. Figure 48. 289-pin i.MX280 MAPBGA Ball Map

2 RESETNBATTER

3 VSS NC GPMI_

5 Revision History

Table 67 summarizes revisions to this document. Table 67. Revision History I n Table 1, "Ordering Information," on page 3, added two rows.  Updated Table 2, "i.MX28 Functional Differences," on page 3.  Updated Table 4, "i.MX28 Digital and Analog Modules," on page 6. I n Table 8, "Recommended Power Supply Operating Conditions," on page 13, updated BATT row.  Updated Table 9, "Operating Temperature Conditions," on page 13. Table 12, "Power Consumption," on page 14. Also changed Dissipation to Consumption in first row.  Updated Table 26, "Digital Pin DC Characteristics for GPIO in 3.3-V Mode," on page 21.  Updated Table 27, "Digital Pin DC Characteristics for GPIO in 1.8 V Mode," on page 23.  Updated and added a footnote to Table 34, "Ethernet PLL Specifications," on page 30.  Updated DDR1 row of Table 35, "EMI Command/Address AC Timing," on page 31. I n Section 4.6, “i.MX283 Ball Map,” replaced Figure 47. Rev. 0 09/2010 Initial release.

Document Number: IMX28CEC Rev. 1 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

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