MCIMX257DJM4

MCIMX25_09 FREESCALE | Alldatasheet

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Technical content

Data Sheet: Advance Information Document Number: IMX25CEC Rev. 2, 12/2009 MCIMX25

Package Information

Case 5284 17 x 17 mm, 0.8 mm Pitch

Ordering Information

See T able 1 on page 3 for ordering information. © Freescale Semiconductor, Inc., 2009. All rights reserved.

1 Introduction

The i.MX25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets. At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds of up to 400 MHz. The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs. The device is suitable for a wide range of applications, including the following:

• Graphical remote controls  Human machine interface (HMI)  Residential and commercial control panels  Residential gateway (smart metering)  Handheld scanners and printers i.MX25 Applications Processor for Consumer and Industrial Products Silicon Version 1.1

3.2 Supply Power-Up/Power-Down Requirements and

4.1 400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch . 121

4.2 Ground, Power, Sense, and Reference Contact

4.3 Signal Contact Assignments—17x17mm,

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX253DVM4, MCIMX257DVM4, MCIMX253CVM4, MCIMX257CVM4, and MCIMX258CVM4.

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2

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 Electronic point-of-sale terminals  Patient-monitoring devices Features of the i.MX25 processor include the following:  Advanced power management—The heart of th e device is a level of power management throughout the IC that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-power modes. Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations.  Multimedia powerhouse—The multimedia performance of the i.MX25 processor is boosted by a

16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with

alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen controller), and a programmable smart DMA (SDMA) controller.  128 Kbytes on-chip SRAM—The additional 128 K byte on-chip SRAM makes the device ideal for eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh.  Interface flexibility—The device interface supports connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND.  Increased security—Because the need for advanc ed security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads.  On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY .  Fast Ethernet—For rapid external communication, a fast Ethernet controller (FEC) is included. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX253DVM4, MCIMX257DVM4, MCIMX253CVM4, MCIMX257CVM4, and MCIMX258CVM4.

1.1 Ordering Information

Table 1 provides ordering information for the i.MX25. Table 1. Ordering Information 1 MCIMX257CVM4, and MCIMX258CVM4.

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1.2 Block Diagram

Figure 1 shows the simplified interface block diagram. Figure 1. i.MX25 Simplified Interface Block Diagram MCIMX257CVM4, and MCIMX258CVM4.

Table 2 describes the digital and analog modules of the device. Table 2. i.MX25 Digital and Analog Modules smart battery interfaces, for example: Dallas DS2502. 16-Kbyte L1 data cache, 32-Kbyte ROM and 128-Kbyte RAM. with the ATA device over a number of ATA signals. disabling peripheral clocks appropriately for power conservation. that can be used in secure and non-secure applications. MCIMX257CVM4, and MCIMX258CVM4.

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sections, each section with its own clock generator. as a vehicle serial data bus running at 1 MBps. on an external clock or on an internal clock. Table 2. i.MX25 Digital and Analog Modules (continued) MCIMX257CVM4, and MCIMX258CVM4.

occasional communications over a short distance between many devices. The interface operates up to 100 kbps with maximum bus loading and timing. of end products through external connections to an assembly-line computer. signals requiring a fixed value. KPP can be used for either keypad matrix scanning or general purpose I/O. LCDC provides display data for external gray-scale or color LCD panels. occur from any master port to any slave port. module that implements 32 DMA channels. peripheral ownership and access rights to an owned peripheral. MCIMX257CVM4, and MCIMX258CVM4.

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2.1 Special Signal Considerations

“Package Information and Contact Assignment.” Signal descriptions are provided in the reference manual. interface to the AUDMUX for flexible audio routing. temperature, voltage, and other measurement functions. Table 3. Signal Considerations BAT_VDD DryIce backup power supply input. through CRM registers. This pin can also be configured (via muxing) to work as a normal GPIO. CLK_SEL should be connected to GND. can be left unconnected if the DryIce security features are not being used. MCIMX257CVM4, and MCIMX258CVM4.

external components (external tamper detect, wire-mesh tamper detect). OSC32K_EXTAL analog pin, and OSC32K_XTAL can be no connect (NC). generated 2.5 V reference supply. must either float this signal or tie it to GND. 33 Ω series resistors (close to the pins). Table 3. Signal Considerations (continued) MCIMX257CVM4, and MCIMX258CVM4.

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3 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the i.MX25. This section provides the chip-level electrical characteristics for the IC.

3.1.1 DC Absolute Maximum Ratings

Table 4 provides the DC absolute maximum operating conditions. may affect device reliability. not implied beyond the conditions indicated in Table 5.

3.1.2 DC Operating Conditions

Table 5 provides the DC recommended operating conditions. Table 4. DC Absolute Maximum Ratings Table 5. DC Operating Conditions MCIMX257CVM4, and MCIMX258CVM4.

1 VDD_BAT must always be powered by battery in security application. In non-security case, VDD_BAT can be connected to QVDD. 2 The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming. 3 NVCC_DRYICE is supply output. A 0.1- μF external capacitor should be connected to it. Table 5. DC Operating Conditions (continued) MCIMX257CVM4, and MCIMX258CVM4.

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3.1.3 Fusebox Supply Current Parameters

Table 6 lists the fusebox supply current parameters.

3.1.4 Interface Frequency Limits

Table 7 provides information for interface frequency limits.

3.1.5 USB_PHY Current Consumption

Table 8 provides information for USB_PHY current consumption. Table 6. Fusebox Supply Current Parameters 1 The current Iprogram is during program time (tprogram). 2 The current Iread is present for approximately 50 ns of the read access to the 8-bit word. Table 7. Interface Frequency Limits Table 8. USB PHY Current Consumption 1

1 Values must be verified

MCIMX257CVM4, and MCIMX258CVM4.

3.1.6 Power Modes

Table 9 describes the core, clock, and module settings for the different power modes of the processor. Table 9. i.MX25 Power Mode Settings 1 Sleep mode differs from stop mode in that the core voltage is reduced to 1 V.

266 MHz

400 MHz

MCIMX257CVM4, and MCIMX258CVM4.

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must be powered back up before it can detect any events. Table 10. i.MX25 Power Mode Current Consumption 1 Values are typical, under typical use conditions.

3.17 V 240 μA2 4 0 μΑ 241 μΑ 242 μΑ

3.17 V 201 μΑ 201 μΑ 191 μΑ 191 μΑ

Table 11. iMX25 Reduced Power Mode Current Consumption MCIMX257CVM4, and MCIMX258CVM4.

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2 Freescale Semiconductor 15

3.2 Supply Power-Up/Power-Down Requirements and Restrictions

Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in this section to ensure reliable operation of the device. Recommended power-up and power-down sequences are given in the following subsections. CAUTION Deviations from the guidelines in this section may result in the following situations:  Excessive current during power-up phase  Prevention of the device from booting  Irreversible damage to the i.MX25 (worst-case scenario) NOTE For security applications, the coin battery must be connected during both power-up and power-down sequences to ensure that security keys are not unintentionally erased.

3.2.1 Power-Up Sequence

The following power-up sequence is recommended: 1. Assert power on reset (POR). 2. Turn on digital logic domain and I/O power supplies VDD n and NVCCx. 3. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD, MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses are not being programmed). The minimum time between turning on each power supply is the time it takes for the previous supply to be stable. 4. Negate the POR signal. NOTE  The user is advised to connect FUSEVDD to GND except when fuses are being programmed, in order to prevent unintentional blowing of fuses.  Other power-up sequences may be possible; however, the above sequence has been verified and is recommended.  There is a 1-ms minimum time betw een supplies coming up, and a 1-ms minimum time between POR_B assert and deassert. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MCIMX253DVM4, MCIMX257DVM4, MCIMX253CVM4, MCIMX257CVM4, and MCIMX258CVM4.

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powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up. Figure 2. Power-Up Sequence Diagram

3.2.2 Power-Down Sequence

3.3 Thermal Characteristics

 Core via I.D: 0.118 mm, Core via plating 0.016 mm. Table 12. Thermal Resistance Data MCIMX257CVM4, and MCIMX258CVM4.

3.4 I/O DC Parameters

chapter of the reference manual.

3.4.1 DDR I/O DC Parameters

External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details). specification for this package. for the case temperature. Reported value includes the thermal resistance of the interface layer. Table 12. Thermal Resistance Data (continued) MCIMX257CVM4, and MCIMX258CVM4.

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3.4.1.1 DDR_TYPE = 00 Standard Setting DDR I/O DC Parameters

1. Simulation circuit for parameters Voh and Vol for I/O cells is below

Table 13. Mobile DDR I/O DC Electrical Characteristics MCIMX257CVM4, and MCIMX258CVM4.

3.4.1.2 DDR_TYPE = 01 SDRAM I/O DC Parameters

Table 14 shows the DC I/O parameters for SDRAM.

1. Simulation circuit for parameters Voh and Vol for I/O cells is below

Maximum condition: wcs model, OVDD = 3.0 V, and 105 °C.

3.4.1.3 DDR_TYPE = 10 Max Setting DDR I/O DC Parameters

Table 15 shows the I/O parameters for DDR2 (SSTL_18). Table 14. SDRAM DC Electrical Characteristics Table 15. DDR2 (SSTL_18) I/O DC Electrical Characteristics MCIMX257CVM4, and MCIMX258CVM4.

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1. OVDD = 1.7 V; Vout = 280 mV. Vout/IOL must be less than 21 W for values of Vout between 0 V and 280 mV. Simulation circuit
2. Vin(dc) specifies the allowable DC excursion of each differential input
3. Vid(dc) specifies the input differential voltage required for switching. The minimum value is equal to Vih(dc) - Vil(dc).
4. Vtt is expected to track OVDD/2.
5. The JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any specification in

3.4.2 GPIO I/O DC Parameters

Table 16 shows the I/O parameters for GPIO. Table 16. GPIO DC Electrical Characteristics Table 15. DDR2 (SSTL_18) I/O DC Electrical Characteristics (continued) MCIMX257CVM4, and MCIMX258CVM4.

Table 16. GPIO DC Electrical Characteristics (continued) MCIMX257CVM4, and MCIMX258CVM4.

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1. Simulation circuit for parameters Voh and Vol for I/O cells is below
2. Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

and 25 °C. Maximum condition: wcs model, OVDD = 3.0 V, and 105 °C.

3.5 AC Electrical Characteristics

This section provides the AC parameters for slow and fast I/O. Figure 3. Load Circuit for Output MCIMX257CVM4, and MCIMX258CVM4.

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3.5.1 Slow I/O AC Parameters

Table 17 shows the slow I/O AC parameters. Table 17. Slow I/O AC Parameters MCIMX257CVM4, and MCIMX258CVM4.

Table 17. Slow I/O AC Parameters (continued) MCIMX257CVM4, and MCIMX258CVM4.

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–40 °C. Input transition time from core is 1 ns (20%–80%). measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

1. Hysteresis mode is recommended for input with transition time greater than 25 ns.

MCIMX257CVM4, and MCIMX258CVM4.

3.5.2 Fast I/O AC Parameters

Table 18 shows the fast I/O AC parameters for OVDD = 1.65–1.95 V . Table 18. Fast I/O AC Parameters for OVDD = 1.65 –1.95 V Output pad propagation delay (max. Output pad propagation delay (max. Output enable to output valid delay (max. Output enable to output valid delay (max. MCIMX257CVM4, and MCIMX258CVM4.

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1. Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs

model, 1.3 V, I/O 1.95 V, and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V and –40 °C.

I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).

1. Hysteresis mode is recommended for input with transition time greater than 25 ns.

Table 18. Fast I/O AC Parameters for OVDD = 1.65 –1.95 V (continued) MCIMX257CVM4, and MCIMX258CVM4.

Table 19 shows the fast I/O AC parameters for OVDD = 3.0–3.6 V . Table 19. Fast I/O AC Parameters for OVDD = 3.0 –3.6 V MCIMX257CVM4, and MCIMX258CVM4.

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model, 1.3 V, IO 3.6 V and –40 °C. Input transition time from core is 1ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, IO 3.0 V and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, IO 3.6 V and –40 °C.

IO 3.6 V and –40 °C. Input transition time from pad is 5ns (20%–80%).

1. Hysteresis mode is recommended for input with transition time greater than 25 ns.

3.5.3 DDR I/O AC Parameters

Table 19. Fast I/O AC Parameters for OVDD = 3.0 –3.6 V (continued) MCIMX257CVM4, and MCIMX258CVM4.

3.5.3.1 DDR_TYPE = 00 Standard Setting I/O AC Parameters and Requirements

Table 20. AC Parameters for Mobile DDR I/O tput enable to output valid delay (max. Output enable to output valid delay (max. MCIMX257CVM4, and MCIMX258CVM4.

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1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:

bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.

I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 21 shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O. Table 21. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O Table 20. AC Parameters for Mobile DDR I/O (continued) MCIMX257CVM4, and MCIMX258CVM4.

Output enable to output valid delay (max. Output enable to output valid delay (max. Table 21. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued) MCIMX257CVM4, and MCIMX258CVM4.

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1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:

bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.

I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 22 shows the AC requirements for mobile DDR I/O.

3.5.3.2 DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements

Table 23 shows AC parameters for SDRAM I/O. Table 22. AC Requirements for Mobile DDR I/O Table 23. AC Parameters for SDRAM I/O MCIMX257CVM4, and MCIMX258CVM4.

Output enable to output valid delay (max. Output enable to output valid delay (max. Table 23. AC Parameters for SDRAM I/O (continued) MCIMX257CVM4, and MCIMX258CVM4.

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1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:

bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.

I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 24 shows AC parameters for SDRAM pbijtov18_33_ddr_clk I/O. Table 24. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O MCIMX257CVM4, and MCIMX258CVM4.

1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:

bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge. Output enable to output valid delay (max. Output enable to output valid delay (max. Table 24. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued) MCIMX257CVM4, and MCIMX258CVM4.

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1. Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.

I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).

3.5.3.3 DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements

Table 25 shows AC parameters for DDR2 I/O.

1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tp v:

bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.

I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 25. AC Parameters for DDR2 I/O MCIMX257CVM4, and MCIMX258CVM4.

Table 26 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.

1. Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv:

bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

1. Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and

between VIH to VIL for falling edge.

1. Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.

I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 27 shows the AC requirements for DDR2 I/O. Table 26. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O Table 27. AC Requirements for DDR2 I/O specification in this document. MCIMX257CVM4, and MCIMX258CVM4.

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3.6 Module Timing and Electrical Parameters

This section contains the timing and electrical parameters for i.MX25 modules. Figure 7. 1-Wire RPP Timing Diagram Figure 8. Write 0 Sequence Timing Diagram indicates the voltage at which differential input signal must cross. indicates the voltage at which differential output signal must cross. Cload = 25 pF. Table 28. RPP Sequence Delay Comparisons Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

parameters (OW7–OW8) that are shown in the figure. Figure 9. Write 1 Sequence Timing Diagram Figure 10. Read Sequence Timing Diagram

3.6.2 ATA Timing Parameters

implementation of the A TA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 29. WR0 Sequence Timing Parameters Table 30. WR1 /RD Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

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Table 31. Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

3.6.2.1 PIO Mode Timing Parameters

Figure 11 shows a timing diagram for PIO read mode. Figure 11. PIO Read Mode Timing Table 32. Timing Parameters for PIO Read Mode MCIMX257CVM4, and MCIMX258CVM4.

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Figure 12 gives timing waveforms for PIO write mode. Figure 12. PIO Write Mode Timing Table 33. Timing Parameters for PIO Write Mode MCIMX257CVM4, and MCIMX258CVM4.

3.6.2.2 Multiword DMA (MDMA) Mode Timing

Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively. Figure 13. MDMA Read Mode Timing Figure 14. MDMA Write Mode Timing on timing parameters for MDMA read and write modes. Table 34. Timing Parameters for MDMA Read and Write Modes MCIMX257CVM4, and MCIMX258CVM4.

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3.6.2.3 Ultra DMA (UDMA) Mode Timing

diagrams for UDMA in- and out-transfers are provided.

3.6.2.3.1 UDMA In-Transfer Timing

Figure 15 shows the timing for UDMA in-transfer start. Figure 15. Timing for UDMA In-Transfer Start 3 tk1 in the UDMA figures equals (tk –2 × T). Table 34. Timing Parameters for MDMA Read and Write Modes (continued) MCIMX257CVM4, and MCIMX258CVM4.

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Timing parameters for UDMA in-burst are listed in Table 35.

3.6.2.4 UDMA Out-Transfer Timing

Figure 18 shows the timing for start of UDMA out-transfer. Figure 18. Timing for UDMA Out-Transfer Start Table 35. Timing Parameters for UDMA In-Burst active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. Make ton and toff big enough to avoid bus contention. MCIMX257CVM4, and MCIMX258CVM4.

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3.6.3 Digital Audio Mux (AUDMUX) Timing

3.6.4 CMOS Sensor Interface (CSI) Timing

(HSYNC)) and output-only Bayer and statistics data. image (for example, image compression, image pre-filtering, and various data output formats). The following subsections describe the CSI timing in gated and ungated clock modes.

3.6.4.1 Gated Clock Mode Timing

HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted. Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge MCIMX257CVM4, and MCIMX258CVM4.

Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge Table 37. CSI Gated Clock Mode Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

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3.6.4.2 Ungated Clock Mode Timing

Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

3.6.5 Configurable Serial Peripheral Interface (CSPI) Timing

Table 38. CSI Ungated Clock Mode Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

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3.6.6 External Memory Interface (EMI) Timing

information for these submodules.

3.6.6.1 ESDCTL Electrical Specifications

3.6.6.1.1 SDRAM Memory Controller

1 The output SCLK transition time is tested with 25 pF drive.

2 Tsclk = CSPI clock period

3 Twait = Wait time, as specified in the sample period control register

4 Tper = CSPI reference baud rate clock period (PERCLK2)

5 Tipg = CSPI main clock IPG_CLOCK period

Table 39. CSPI Interface Timing Parameters (continued) MCIMX257CVM4, and MCIMX258CVM4.

Figure 25. SDRAM Read Cycle Timing Diagram Table 40. DDR/SDR SDRAM Read Cycle Timing Parameters Note: CKE is high during the read/write cycle. MCIMX257CVM4, and MCIMX258CVM4.

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Figure 26. SDR SDRAM Writ e Cycle Timing Diagram 1 SD1 + SD2 does not exceed 7.5 ns for 133 MHz. Table 40. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) MCIMX257CVM4, and MCIMX258CVM4.

Figure 27. SDRAM Refresh Timing Diagram Table 41. SDR SDRAM Write Timing Parameters 1 SD11 and SD12 are determined by SDRAM controller register settings. MCIMX257CVM4, and MCIMX258CVM4.

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Figure 28. SDRAM Self-Refr esh Cycle Timing Diagram Table 42. SDRAM Refresh Timing Parameters 1 SD10 and SD11 are determined by SDRAM controller register settings. MCIMX257CVM4, and MCIMX258CVM4.

3.6.6.1.2 Mobile DDR SDRAM–Specific Parameters

Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram Table 43. SDRAM Self-Refresh Cycle Timing Parameters Table 44. Mobile DDR SDRAM Write Cycle Timing Parameters 1 1 T est condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703. MCIMX257CVM4, and MCIMX258CVM4.

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Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

3.6.6.1.3 DDR2 SDRAM–Specific Parameters

Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

Figure 31. DDR2 SDRAM Basic Timing Parameters Table 46. DDR2 SDRAM Timing Parameter Table MCIMX257CVM4, and MCIMX258CVM4.

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slew rate of 2 V/ns. Table 47 shows additional values for DDR2-400 and DDR2-533. Table 47. tlS, tlH Derating Values for DDR2-400, DDR2-533 MCIMX257CVM4, and MCIMX258CVM4.

Figure 32. DDR2 SDRAM Write Cycle Timing Diagram Table 48. DDR2 SDRAM Write Cycle Parameter Table Table 49. ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533 1,2,3 MCIMX257CVM4, and MCIMX258CVM4.

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Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram SDCLK and SDCLK (inverted clock). Table 50. DDR2 SDRAM Read Cycle Parameter Table 1,2 Table 49. ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533 1,2,3 (continued) MCIMX257CVM4, and MCIMX258CVM4.

3.6.6.2 NAND Flash Controller (NFC) Timing

under normal mode. Table 51 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 34. Command Latch Cycle Timing Diagram Figure 35. Address Latch Cycle Timing Diagram SDCLK and SDCLK (inverted clock). MCIMX257CVM4, and MCIMX258CVM4.

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Figure 36. Write Data Latch Cycle Timing Diagram Figure 37. Read Data Latch Cycle Timing Diagram Table 51. NFC Timing Parameters 1 MCIMX257CVM4, and MCIMX258CVM4.

value; while signal low is defined as 20% of signal value. which are not related to the NFC clock.

3.6.6.3 Wireless External Interface Module (WEIM) Timing

(WE1–WE27) shown in the figure. and DTACK are all captured relative to BCLK rising edge. 1 The Flash clock maximum frequency is 50 MHz. Table 51. NFC Timing Parameters 1 (continued) MCIMX257CVM4, and MCIMX258CVM4.

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Figure 38. WEIM Bus Timing Diagram Table 52. WEIM Bus Timing Parameters 1 MCIMX257CVM4, and MCIMX258CVM4.

strength for all controls, address, and BCLK is maximum drive. 1 High is defined as 80% of signal value; low is defined as 20% of signal value. defined as 50% as signal value. Table 52. WEIM Bus Timing Parameters 1 (continued) MCIMX257CVM4, and MCIMX258CVM4.

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timing parameters described in Table 52 for specific control parameter settings. Figure 39. Synchronous Memory Timing Diagram for Read Access—WSC=1 Figure 40. Synchronous Memory Timing Diagram for Write Access— MCIMX257CVM4, and MCIMX258CVM4.

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Figure 43. Muxed A/D Mode Timing Diagram for Synchronous Write Access— Figure 44. Muxed A/D Mode Timing Diagram for Synchronous Read Access— MCIMX257CVM4, and MCIMX258CVM4.

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Figure 47. Asynchronous Memory Write Access Figure 48. Asynchronous A/D Mux Write Access MCIMX257CVM4, and MCIMX258CVM4.

Figure 49. DTACK Read Access Table 53. WEIM Asynchronous Timing Parameters Relative to Chip Select Table MCIMX257CVM4, and MCIMX258CVM4.

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Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units. 1 For the value of parameters WE4–WE21, see column BCD = 0 in Table 52. 2 CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles. 3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles. 4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles. 5 BE Negation. This bit field determines when the BE signal is negated during read cycles. 6 Output maximum delay from internal driving ADDR/control FFs to chip outputs. 7 Output maximum delay from CS[x] internal driving FFs to CS[x] out. 8 DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Table 53. WEIM Asynchronous Timing Parameters Relative to Chip Select Table (continued) MCIMX257CVM4, and MCIMX258CVM4.

3.6.7 Enhanced Serial Audio Interface (ESAI) Timing

Figure 50 shows the ESAI transmit timing diagram. Figure 50. ESAI Transmit Timing frame. In normal mode, the output flag state is asserted for the entire frame period. MCIMX257CVM4, and MCIMX258CVM4.

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Figure 51 shows the ESAI receive timing diagram. Figure 51. ESAI Receive Timing Diagram Figure 52 shows the ESAI HCKT timing diagram. Figure 52. ESAI HCKT Timing MCIMX257CVM4, and MCIMX258CVM4.

Figure 53 shows the ESAI HCKR timing diagram. Figure 53. ESAI HCKR Timing respectively the conditions and signals cited in Table 56. Table 54. ESAI Timing Conditions Table 55. ESAI Signals Table 56. ESAI General Timing Requirements

62 Clock cycle 4 tSSICC 4 × Tc

63 Clock high period

64 Clock low period

MCIMX257CVM4, and MCIMX258CVM4.

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65 SCKR rising edge to FSR out (bl) high — — —

66 SCKR rising edge to FSR out (bl) low — — —

67 SCKR rising edge to FSR out (wr) high 5 —— —

68 SCKR rising edge to FSR out (wr) low 5 —— —

69 SCKR rising edge to FSR out (wl) high — — —

70 SCKR rising edge to FSR out (wl) low — — —

71 Data in setup time before SCKR (SCK in

73 FSR input (bl, wr) high before SCKR falling

78 SCKT rising edge to FST out (bl) high — — —

79 SCKT rising edge to FST out (bl) low — — —

80 SCKT rising edge to FST out (wr) high

81 SCKT rising edge to FST out (wr) low

82 SCKT rising edge to FST out (wl) high — — —

83 SCKT rising edge to FST out (wl) low — — —

84 SCKT rising edge to data out enable from

85 SCKT rising edge to transmitter #0 drive

Table 56. ESAI General Timing Requirements (continued) MCIMX257CVM4, and MCIMX258CVM4.

3.6.8 Enhanced Secured Digital Host Controller (eSDHCv2) Timing

86 SCKT rising edge to data out valid — — —

87 SCKT rising edge to data out high

88 SCKT rising edge to transmitter #0 drive

89 FST input (bl, wr) setup time before SCKT

90 FST input (wl) setup time before SCKT falling

92 FST input (wl) to data out enable from high

93 FST input (wl) to transmitter #0 drive enable

94 Flag output valid after SCKT rising edge — — —

95 HCKR/HCKT clock cycle — 2 x T

2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative

3 In the “Expression” column, TC = 7.5 ns. 4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. until the second-to-last bit-clock of the first word in the frame. 6 Periodically sampled and not 100% tested. MCIMX257CVM4, and MCIMX258CVM4.

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Figure 54. eSDHCv2 Timing Table 57. eSDHCv2 Interface Timing Specification 1 In low-speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. frequency can be any value between 0 ~ 50 MHz. frequency can be any value between 0 ~ 52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. MCIMX257CVM4, and MCIMX258CVM4.

3.6.9 Fast Ethernet Controller (FEC) Timing

operating at a voltage of 3.3 V . The following subsections describe the timing for MII and RMII modes.

3.6.9.1 FEC MII Mode Timing

3.6.9.1.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

Figure 55. MII Receive Signal Timing Diagram 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. Table 58. MII Receive Signal Timing MCIMX257CVM4, and MCIMX258CVM4.

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3.6.9.1.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

Figure 56. MII Transmit Signal Timing Diagram 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.6.9.1.3 MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)

Figure 57. MII Async Inputs Timing Diagram Table 59. MII Transmit Signal Timing MCIMX257CVM4, and MCIMX258CVM4.

1 FEC_COL has the same timing in 10-Mbit 7-wire interface mode.

3.6.9.2 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

(M10—M15) shown in the figure. Figure 58. MII Serial Management Channel Timing Diagram Table 60. MII Asynchronous Inputs Signal Timing Table 61. MII Serial Management Channel Timing M10 FEC_MDC falling edge to FEC_MDIO output invalid (min. M11 FEC_MDC falling edge to FEC_MDIO output valid (max. MCIMX257CVM4, and MCIMX258CVM4.

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3.6.9.3 RMII Mode Timing

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and FEC_RX_ER. Figure 59. RMII Mode Signal Timing Diagram Table 62. RMII Signal Timing MCIMX257CVM4, and MCIMX258CVM4.

3.6.10 Controller Area Network (FlexCAN) Transceiver Parameters and

Table 63 and Table 64 show voltage requirements for the FlexCAN transceiver Tx and Rx pins. Figure 60. FlexCAN Timing Diagram Table 63. Tx Pin Characteristics Table 64. Rx Pin Characteristics MCIMX257CVM4, and MCIMX258CVM4.

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Figure 61. Timing Diagram for FlexCAN Standby Signal Figure 62. Timing Diagram for FlexCAN Shutdown Signal Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal has to operate, DPLLs work in FOL mode only. MCIMX257CVM4, and MCIMX258CVM4.

3.6.11 Inter IC Communication (I 2C) Timing

parameters (IC1–IC6) shown in the figure. Figure 64. I2C Module Timing Diagram Table 65. I2C Module Timing Parameters: 3.0 V +/–0.30 V MCIMX257CVM4, and MCIMX258CVM4.

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of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal. specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF. Table 66. I2C Module Timing Parameters: 1.8 V +/– 0.10 V MCIMX257CVM4, and MCIMX258CVM4.

3.6.12 Liquid Crystal Display Controller (LCDC) Timing

Table 68 list the timing parameters used in the associated figures. Figure 65. LCDC Non-TFT Mode Timing Diagram Table 67. LCDC Non-TFT Mode Timing Parameters

1 T is pixel clock period

MCIMX257CVM4, and MCIMX258CVM4.

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Figure 66. LCDC TFT Mode Timing Diagram

3.6.13 Pulse Width Modulator (PWM) Timing Parameters

Figure 67 depicts the timing of the PWM, and Table 69 lists the PWM timing characteristics. pulse width modulator output (PWMO) external pin. Table 68. LCDC TFT Mode Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

Figure 67. PWM Timing

3.6.14 Subscriber Identity Module (SIM) Timing

Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals). Typically a port uses five signals. SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate. information see ISO/IEC 7816). Table 69. PWM Output Timing Parameter

1 System CLK frequency1

1 CL of PWMO = 30 pF

MCIMX257CVM4, and MCIMX258CVM4.

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Figure 68. SIM Clock Timing Diagram Table 70 defines the general timing requirements for the SIM interface. Table 70. Timing Specifications, High Drive Strength

2 With C = 50 pF

3 With C = 50 pF

4 With Cin = 30 pF, Cout = 30 pF,

5 With Cin = 30 pF,

MCIMX257CVM4, and MCIMX258CVM4.

3.6.14.1 SIM Reset Sequences

3.6.14.1.1 SIM Cards with Internal Reset

 After 200 clock cycles, SIM x_DA TAy_RX_TX must be asserted. 400–40000 clock cycles after T0. Figure 69. Internal Reset Card Reset Sequence Table 71 defines the general timing requirements for the SIM interface.

3.6.14.1.2 SIM Cards with Active Low Reset

 After 200 clock cycles, SIM x_DA TAy_RX_TX must be asserted. received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. Table 71. Timing Specifications, Internal Reset Card Reset Sequence MCIMX257CVM4, and MCIMX258CVM4.

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Figure 70. Active-Low-Reset SIM Card Reset Sequence Table 72 defines the general timing requirements for the SIM interface.

3.6.14.2 SIM Power-Down Sequence

requirements for parameters (SI7–SI10) shown in the figure. SIM card removal detection; or it may be launched by the processor. Table 72. Timing Specifications, Active-Low-Reset SIM Card Reset Sequence MCIMX257CVM4, and MCIMX258CVM4.

Figure 71. SmartCard Interface Power Down AC Timing

3.6.15 System JTAG Controller (SJC) Timing

Figure 72. Test Clock Input Timing Diagram Table 73. Timing Requirements for Power-down Sequence MCIMX257CVM4, and MCIMX258CVM4.

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Figure 73. Boundary Scan (JTAG) Timing Diagram Figure 74. Test Access Port Timing Diagram MCIMX257CVM4, and MCIMX258CVM4.

Figure 75. TRST Timing Diagram Table 74. SJC Timing Parameters core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.

2 VM – mid point voltage

MCIMX257CVM4, and MCIMX258CVM4.

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3.6.16 Smart Liquid Crystal Display Controller (SLCDC)

Table 76 describe the timing parameters shown in the respective figures. Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device MCIMX257CVM4, and MCIMX258CVM4.

Figure 77. SLCDC Timing Diagram—Parallel Transfers to LCD Device Table 75. SLCDC Serial Interface Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

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3.6.17 Synchronous Serial Interface (SSI) Timing

3.6.17.1 SSI Transmitter Timing with Internal Clock

Figure 78. SSI Transmitter with Internal Clock Timing Diagram Table 76. SLCDC Parallel Interface Timing Parameters MCIMX257CVM4, and MCIMX258CVM4.

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on pads when SSI is being used for a data transfer.  ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI. Table 77. SSI Transmitter Timing with Internal Clock MCIMX257CVM4, and MCIMX258CVM4.

104 Freescale Semiconductor

3.6.17.2 SSI Receiver Timing with Internal Clock

parameters (SS1–SS51) shown in the figure. Figure 79. SSI Receiver Internal Clock Timing Diagram Table 78. SSI Receiver Timing with Internal Clock MCIMX257CVM4, and MCIMX258CVM4.

the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on pads when SSI is being used for a data transfer.  ”Tx” and “Rx” refer to the transmit and receive sections of the SSI.

3.6.17.3 SSI Transmitter Timing with External Clock

parameters (SS22-SS46) shown in the figure. Figure 80. SSI Transmitter with External Clock Timing Diagram Table 78. SSI Receiver Timing with Internal Clock (continued) MCIMX257CVM4, and MCIMX258CVM4.

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the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures.  All timings are on pads when SSI is being used for data transfer.  ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI. Table 79. SSI Transmitter Timing with External Clock MCIMX257CVM4, and MCIMX258CVM4.

3.6.17.4 SSI Receiver Timing with External Clock

parameters (SS22–SS41) used in the figure. Figure 81. SSI Receiver with External Clock Timing Diagram the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.  All timings are on pads when SSI is being used for data transfer. Table 80. SSI Receiver Timing with External Clock MCIMX257CVM4, and MCIMX258CVM4.

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 ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.

3.6.18 Touchscreen ADC Electrical Specifications and Timing

This section describes the electrical specifications, operation modes, and timing of the touchscreen ADC.

3.6.18.1 ADC Electrical Specifications

Table 81 shows the electrical specifications for the touchscreen ADC. Table 81. Touchscreen ADC Electrical Specifications MCIMX257CVM4, and MCIMX258CVM4.

3.6.18.2 ADC Timing Diagrams

conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated. soc signals applied to the touchscreen controller. touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA. 3 At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 °C, fclk = 1.75 MHz, any process corner, unless otherwise noted. 4 Value measured with a –0.5 dBFS sinusoidal input signal and computed with the code density test. Table 81. Touchscreen ADC Electrical Specifications (continued) MCIMX257CVM4, and MCIMX258CVM4.

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Figure 82. Start-up Sequence xnsw) are totally asynchronous. selection during clock cycles 2 to 13. only after an eoc pulse has been acquired, during the last clock cycle (14). MCIMX257CVM4, and MCIMX258CVM4.

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for any value of N equal or greater than 1. Figure 84. ADC Usage with Idle Cycles Between Conversions

3.6.19 UART Timing

This section describes the timing of the UART module in serial and parallel mode.

3.6.19.1 UART RS-232 Serial Mode Timing

3.6.19.1.1 UART Transmit Timing in RS-232 Serial Mode

bit. Table 82 describes the timing parameter (UA1) shown in the figure. Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram MCIMX257CVM4, and MCIMX258CVM4.

3.6.19.1.2 UART Receive Timing in RS-232 Serial Mode

Figure 86 shows the UART receive timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit. Table 83 describes the timing parameter (UA2) shown in the figure. Figure 86. UART RS-232 Serial Mode Receive Timing Diagram

3.6.19.2 UART Infrared (IrDA) Mode Timing

The following subsections describe the UART transmit and receive timing in IrDA mode.

3.6.19.2.3 UART IrDA Mode Transmit Timing

Figure 87 depicts the UART transmit timing in IrDA mode, showing only 8 data bits and 1 stop bit. Table 84 describes the timing parameters (UA3–UA4) shown in the figure. Figure 87. UART IrDA Mode Transmit Timing Diagram Table 82. UART RS-232 Serial Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 83. UART RS-232 Serial Mode Receive Timing Parameters not exceed 3/(16 × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. MCIMX257CVM4, and MCIMX258CVM4.

114 Freescale Semiconductor

3.6.19.2.4 UART IrDA Mode Receive Timing

Figure 88 shows the UART receive timing for IrDA mode, for a format of 8 data bits and 1 stop bit. Table 85 describes the timing parameters (UA5–UA6) shown in the figure. Figure 88. UART IrDA Mode Receive Timing Diagram

3.6.20 USBOTG Timing

3.6.20.1 USB Serial Interface Timing

The following subsections describe the timings for these four modes. Table 84. UART IrDA Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 85. UART IrDA Mode Receive Timing Parameters not exceed 3/(16 × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. MCIMX257CVM4, and MCIMX258CVM4.

3.6.20.1.1 DAT_SE0 Bidirectional Mode Timing

Table 86 defines the DAT_SE0 bidirectional mode signals. Figure 89 shows the USB transmit waveform in DAT_SE0 bidirectional mode diagram. Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Figure 90 shows the USB receive waveform in DAT_SE0 bidirectional mode diagram. Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 86. Signal Definitions—DAT_SE0 Bidirectional Mode MCIMX257CVM4, and MCIMX258CVM4.

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Table 87 shows the OTG port timing specification in DAT_SE0 bidirectional mode.

3.6.20.1.2 DAT_SE0 Unidirectional Mode Timing

Table 88 defines the DAT_SE0 unidirectional mode signals. Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode Table 87. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode Table 88. Signal Definitions—DAT_SE0 Unidirectional Mode MCIMX257CVM4, and MCIMX258CVM4.

Figure 92 shows the USB receive waveform in DAT_SE0 unidirectional mode diagram. Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 89 shows the USB port timing specification in DAT_SE0 unidirectional mode.

3.6.20.1.3 VP_VM Bidirectional Mode Timing

Table 90 defines the VP_VM bidirectional mode signals. Table 89. USB Port Timing Specification in DAT_SE0 Unidirectional Mode Table 90. Signal Definitions—VP_VM Bidirectional Mode MCIMX257CVM4, and MCIMX258CVM4.

118 Freescale Semiconductor

Figure 93 shows the USB transmit waveform in VP_VM bidirectional mode diagram. Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode Figure 94 shows the USB receive waveform in VP_VM bidirectional mode diagram. Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode Table 91 shows the USB port timing specification in VP_VM bidirectional mode. Table 91. USB Port Timing Specifications in VP_VM Bidirectional Mode MCIMX257CVM4, and MCIMX258CVM4.

3.6.20.1.4 VP_VM Unidirectional Mode Timing

Table 92 defines the signals for USB in VP_VM unidirectional mode. Figure 95 shows the USB transmit waveform in VP_VM unidirectional mode diagram. Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode Table 92. Signal Definitions for USB VP_VM Unidirectional Mode Table 91. USB Port Timing Specifications in VP_VM Bidirectional Mode (continued) MCIMX257CVM4, and MCIMX258CVM4.

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Figure 96 shows the USB receive waveform in VP_VM unidirectional mode diagram. Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode Table 93 shows the timing specifications for USB in VP_VM unidirectional mode. Table 93. USB Timing Specifications in VP_VM Unidirectional Mode MCIMX257CVM4, and MCIMX258CVM4.

3.6.20.2 USB Parallel Interface Timing

Table 94 defines the USB parallel interface signals. parameters (USB15–USB17) shown in the figure. Figure 97. USB Parallel Mode Transmit/Receive Waveform

4 Package Information and Contact Assignment

 All dimensions in millimeters.  Dimensioning and tolerancing per ASME Y14.5M-1994. Table 94. Signal Definitions for USB Parallel Interface Table 95. USB Timing Specification in Parallel Mode MCIMX257CVM4, and MCIMX258CVM4.

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 Maximum solder bump diameter measured parallel to datum A.  Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.  Parallelism measurement shall exclude any effect of mark on top surface of package. Figure 98. zzxzi.MX25 Production Package

4.2 Ground, Power, Sense, and Reference Contact Assignments

Figure 96 shows ground, power, sense, and reference contact assignments. Table 96. Ground, Power Sense, and Reference Contact Assignments MCIMX257CVM4, and MCIMX258CVM4.

Table 96. Ground, Power Sense, and Reference Contact Assignments (continued) MCIMX257CVM4, and MCIMX258CVM4.

124 Freescale Semiconductor

Table 97 lists the i.MX25 signal contact assignments. Table 97. i.MX25 Signal Contact Assignment MCIMX257CVM4, and MCIMX258CVM4.

Table 97. i.MX25 Signal Contact Assignment (continued) MCIMX257CVM4, and MCIMX258CVM4.

126 Freescale Semiconductor

Table 98 lists the i.MX25 no connect contact assignments. Table 98. i.MX25 No Connect Contact Assignments MCIMX257CVM4, and MCIMX258CVM4.

Table 99 shows the i.MX25 ball map. Table 99. i.MX25 Ball Map MCIMX257CVM4, and MCIMX258CVM4.

128 Freescale Semiconductor

Table 99. i.MX25 Ball Map (continued) MCIMX257CVM4, and MCIMX258CVM4.

5 Revision History

Table 100 summarizes revisions to this document. Table 100. Revision History 2 12/2009  Updated Table 1, “Ordering Information,” to include new part numbers. 1 10/2009  Updated Table 1, “Ordering Information,” to include new part numbers.  Updated values in Table 52, “WEIM Bus Timing Parameters. MCIMX257CVM4, and MCIMX258CVM4.

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 2

130 Freescale Semiconductor

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