MCIMX25 FREESCALE | Alldatasheet
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Technical content
Data Sheet: Technical Data Document Number: IMX25CEC Rev. 7, 12/2010 MCIMX25
Package Information
Case 5284 17 x 17 mm, 0.8 mm Pitch Case 2107 12 x 12 mm, 0.5 mm Pitch
Ordering Information
See Table 1 on page 3 for ordering information. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. 1I n t r o d u c t i o n The i.MX25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets. At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds of up to 400 MHz. The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs. The device is suitable for a wide range of applications, including the following:
- Graphical remote controls Human Machine Interface (HMI) Residential and commercial control panels Residential gateway (smart metering) Handheld scanners and printers i.MX25 Applications Processor for Consumer and Industrial Products Silicon Version 1.2 3.2. Supply Power-Up/Power-Down Requirements and 4.1. 400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch . 124 4.2. Ground, Power, Sense, and Reference Contact Assignments Case 17x17 mm, 0.8 mm Pitch . . . 125 4.3. Signal Contact Assignments—17 x 17 mm, 0.8 mm 4.5. 347 MAPBGA—Case 12 x 12 mm, 0.5 mm Pitch 138 4.6. Ground, Power, Sense, and Reference Contact Assignments Case 12x12 mm, 0.5 mm Pitch . . . 139 4.7. Signal Contact Assignments—12 x 12 mm, 0.5 mm
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 7
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Electronic point-of-sale terminals Patient-monitoring devices Features of the i.MX25 processor include the following: Advanced power management—The heart of th e device is a level of power management throughout the IC that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-power modes. Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations. Multimedia powerhouse—The multim edia performance of the i.MX25 processor is boosted by a
16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with
alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen controller), and a programmable Smart DMA (SDMA) controller. 128 Kbytes on-chip SRAM—The additional 128 Kbyt e on-chip SRAM makes the device ideal for eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh. Interface flexibility—The device interface suppor ts connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND. Increased security—Becau se the need for advanced security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, Digital Rights Management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads. On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY . Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included. i.MX25 only supports Little Endian mode.
1.1 Ordering Information
Table 1 provides ordering information for the i.MX25. Table 1. Ordering Information1
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Table 2 shows the functional differences between the different parts in the i.MX25 family. Table 2. i.MX25 Parts Functional Differences
1.2 Block Diagram
Figure 1 shows the simplified interface block diagram. Figure 1. i.MX25 Simplified Interface Block Diagram
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Table 3 describes the digital and analog modules of the device. Table 3. i.MX25 Digital and Analog Modules smart battery interfaces, for example: Dallas DS2502. 16-Kbyte L1 data cache, 32-Kbyte ROM and 128-Kbyte RAM. with the ATA device over a number of ATA signals. disabling peripheral clocks appropriately for power conservation. that can be used in secure and non-secure applications.
sections, each section with its own clock generator. as a vehicle serial data bus running at 1 MBps. on an external clock or on an internal clock. Table 3. i.MX25 Digital and Analog Modules (continued)
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occasional communications over a short distance between many devices. The interface operates up to 100 kbps with maximum bus loading and timing. of end products through external connections to an assembly-line computer. signals requiring a fixed value. KPP can be used for either keypad matrix scanning or general purpose I/O. LCDC provides display data for external gray-scale or color LCD panels. occur from any master port to any slave port. module that implements 32 DMA channels. peripheral ownership and access rights to an owned peripheral.
2.1 Special Signal Considerations
“Package Information and Contact Assignment.” Signal descriptions are provided in the reference manual. interface to the AUDMUX for flexible audio routing. for temperature, voltage, and other measurement functions. Table 4. Signal Considerations BAT_VDD DryIce backup power supply input. through CRM registers. This pin can also be configured (through muxing) to work as a normal GPIO. CLK_SEL should be connected to GND. muxing) to work as a normal GPIO. MESH_C. These pins can be left unconnected if the DryIce security features are not being used.
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NVCC_DRYICE This is the DryIce power supply output. The su pply source is QVDD when the i.MX25 is in run mode. pin. A 4.7µF capacitor is recommended. OSC32K_EXTAL analog pin, and OSC32K_XTAL can be no connect (NC). configured to work as a normal GPIO. generated 2.5 V reference supply. security features are not being used. must either float this signal or tie it to GND. muxing) to work as a normal GPIO. series resistors (close to the pins). Table 4. Signal Considerations (continued)
3 Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX25. This section provides the chip-level electrical characteristics for the IC.
3.1.1 DC Absolute Maximum Ratings
Table 5 provides the DC absolute maximum operating conditions. may affect device reliability. not implied beyond the conditions indicated in Table 6.
3.1.2 DC Operating Conditions
Table 6 provides the DC recommended operating conditions. Table 5. DC Absolute Maximum Ratings Table 6. DC Operating Conditions
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2 The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming. Table 6. DC Operating Conditions (continued)
3.1.3 Fusebox Supply Current Parameters
Table 7 lists the fusebox supply current parameters.
3.1.4 Interface Frequency Limits
Table 8 provides information for interface frequency limits. Table 9 provides the recommended external crystal specifications. Table 9. Recommended External Crystal Specifications used from an external clock source). Table 10. Recommended External Reference Clock Specifications Table 7. Fusebox Supply Current Parameters 1 The current Iprogram is during program time (tprogram). 2 The current Iread is present for approximately 50 ns of the read access to the 8-bit word. Table 8. Interface Frequency Limits
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3.1.5 USB_PHY Current Consumption
Table 11 provides information for USB_PHY current consumption.
3.1.6 Power Modes
Table 12 describes the core, clock, and module settings for the different power modes of the processor. Table 11. USB PHY Current Consumption1
1 Values must be verified
Table 12. i.MX25 Power Mode Settings 1 Sleep mode differs from stop mode in that the core voltage is reduced to 1 V.
266 MHz
400 MHz
must be powered back up before it can detect any events. Table 13. i.MX25 Power Mode Current Consumption 1 Values are typical, under typical use conditions.
3.17 V 240 μA 240 μΑ 241 μΑ 242 μΑ
3.17 V 201 μΑ 201 μΑ 191 μΑ
3.0 V 158 μA 0158 μΑ 164 μΑ 164 μΑ
Table 14. iMX25 Reduced Power Mode Current Consumption
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 7
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3.2 Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in this section to ensure reliable operation of the device. Recommended power-up and power-down sequences are given in the following subsections. CAUTION Deviations from the guidelines in this section may result in the following situations: Excessive current during power-up phase Prevention of the device from booting Irreversible damage to the i.MX25 (worst-case scenario) NOTE For security applications, the coin battery must be connected during both power-up and power-down sequences to ensure that security keys are not unintentionally erased.
3.2.1 Power-Up Sequence
The following power-up sequence is recommended: 1. Assert power on reset (POR). 2. Turn on digital logic domain and I/O power supplies VDD n and NVCCx. 3. Turn on all other analog power s upplies, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD, MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses are not being programmed). The minimum time between turning on each power supply is the time it takes for the previous supply to be stable. 4. Negate the POR signal. NOTE The user is advised to connect FUSEVDD to GND except when fuses are being programmed, in order to prevent unintentional blowing of fuses. Other power-up sequences may be possible; however, the above sequence has been verified and is recommended. There is a 1-ms minimum time be tween supplies coming up, and a 1-ms minimum time between POR_B assert and deassert.
powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up. Figure 2. Power-Up Sequence Diagram
3.2.2 Power-Down Sequence
3.2.3 SRTC DryIce Power-Up/Down Sequence
must follow the specific power-up/down sequence.
- Assert Power on reset (POR).
- At any time from step 2 and to step 4, turn on other digital I/O power suppliers NVCCx.
- Turn on digital logic domain QVDD no less th an 1 ms and no greater than 32 ms after
to QVDD domain after QVDD is on.
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- Turn on all other analog power supplies including USBPHY1_VDDA_BIAS,
(reset) values from QVDD domain and NVCCx domain.
- Negate the POR signal at least 90 μs after all previous steps.
MX25 chip, before POR is removed.
- Turn off power for analog parts, incl uding USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,
if fuses are not being programmed).
- Turn off NVCCx, PLL, OSC, and other powers.
3.3 Power Characteristics
conditions in the end system. Table 15. Power Consumption
- Measure the worst case power consumption on i ndividual rails using directed test on i.MX25.
- Correlate the worst case power consumption power measurements with the worst case power
- Combine common voltage rails based on the power supply sequencing requirements (add the
maximize different rails in the power group).
- Guard the worst case numbers for temperature and process variation.
- The sum of individual rails is greater than the real world power consumption, since a real
- BATT_VDD current is measured when the system is in reduced power mode maintaining the
becomes negligible. Refer to Table 12, for more details on the power modes.
3.4 Thermal Characteristics
Core through I.D: 0.118 mm, Core through plating 0.016 mm. 1 The FUSE_VDD rail is connected to ground. it only needs a voltage if the system fuse burning is needed. Table 15. Power Consumption (continued)
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3.5 I/O DC Parameters
chapter of the reference manual.
3.5.1 DDR I/O DC Parameters
External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details). Table 16. Thermal Resistance Data specification for this package. used for the case temperature. Reported value includes the thermal resistance of the interface layer.
3.5.1.1 DDR_TYPE = 00 Standard Setting DDR I/O DC Parameters
- Simulation circuit for parameters Voh and Vol for I/O cells is below
Table 17. Mobile DDR I/O DC Electrical Characteristics
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3.5.1.2 DDR_TYPE = 01 SDRAM I/O DC Parameters
Table 18 shows the DC I/O parameters for SDRAM.
- Simulation circuit for parameters Voh and Vol for I/O cells is below
Maximum condition: wcs model, OVDD = 3.0 V, and 105 °C.
3.5.1.3 DDR_TYPE = 10 Max Setting DDR I/O DC Parameters
Table 19 shows the I/O parameters for DDR2 (SSTL_18). Table 18. SDRAM DC Electrical Characteristics Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics
- OVDD = 1.7 V; Vout = 280 mV. Vout/IOL must be less than 21 W for values of Vout between 0 V and 280 mV. Simulation circuit
- Vin(dc) specifies the allowable DC excursion of each differential input
- Vid(dc) specifies the input differential voltage required for switching. The minimum value is equal to Vih(dc) - Vil(dc).
- Vtt is expected to track OVDD/2.
- The JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any specification in
3.5.2 GPIO I/O DC Parameters
Table 20 shows the I/O parameters for GPIO. Table 20. GPIO DC Electrical Characteristics Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics (continued)
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Table 20. GPIO DC Electrical Characteristics (continued)
- Simulation circuit for parameters Voh and Vol for I/O cells is below
- Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
25 °C. Maximum condition: wcs model, OVDD = 3.0 V, and 105 °C.
3.6 AC Electrical Characteristics
This section provides the AC parameters for slow and fast I/O. Figure 3. Load Circuit for Output
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Figure 4. Output Pad Transition Time Waveform Figure 5. Output Pad Propagation and Transition Time Waveform Figure 6. Output Enable to Output Valid
3.6.1 Slow I/O AC Parameters
Table 21 shows the slow I/O AC parameters. Table 21. Slow I/O AC Parameters
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Table 21. Slow I/O AC Parameters (continued)
–40 °C. Input transition time from core is 1 ns (20%–80%). measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
- Hysteresis mode is recommended for input with transition time greater than 25 ns.
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3.6.2 Fast I/O AC Parameters
Table 22 shows the fast I/O AC parameters for OVDD = 1.65–1.95 V . Table 22. Fast I/O AC Parameters for OVDD = 1.65–1.95 V Output pad propagation delay (max. Output pad propagation delay (max. Output enable to output valid delay (max. Output enable to output valid delay (max.
- Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.95 V, and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V and –40 °C.
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
- Hysteresis mode is recommended for input with transition time greater than 25 ns.
Table 23 shows the fast I/O AC parameters for OVDD = 3.0–3.6 V . Table 23. Fast I/O AC Parameters for OVDD = 3.0–3.6 V Table 22. Fast I/O AC Parameters for OVDD = 1.65–1.95 V (continued)
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Table 23. Fast I/O AC Parameters for OVDD = 3.0–3.6 V (continued)
model, 1.3 V, IO 3.6 V and –40 °C. Input transition time from core is 1ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, IO 3.0 V and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, IO 3.6 V and –40 °C.
IO 3.6 V and –40 °C. Input transition time from pad is 5ns (20%–80%).
- Hysteresis mode is recommended for input with transition time greater than 25 ns.
3.6.3 DDR I/O AC Parameters
3.6.3.1 DDR_TYPE = 00 Standard Setti ng I/O AC Parameters and Requirements
Table 24. AC Parameters for Mobile DDR I/O
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Output enable to output valid delay (max. Output enable to output valid delay (max. Table 24. AC Parameters for Mobile DDR I/O (continued)
- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 25 shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O. Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O Output enable to output valid delay (max.
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- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.
I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 26 shows the AC requirements for mobile DDR I/O. Output enable to output valid delay (max. Table 26. AC Requirements for Mobile DDR I/O Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued)
3.6.3.2 DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements
Table 27 shows AC parameters for SDRAM I/O. Table 27. AC Parameters for SDRAM I/O Output enable to output valid delay (max. Output enable to output valid delay (max.
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- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.
I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 28 shows AC parameters for SDRAM pbijtov18_33_ddr_clk I/O. Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O Table 27. AC Parameters for SDRAM I/O (continued)
Output enable to output valid delay (max. Output enable to output valid delay (max. Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued)
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- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 3.0 V, and 105 °C. Minimum condition for tpr, tpo, and tpv:
bcs model, 1.3 V, I/O 3.6 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V, and 105°C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V, and –40 °C.
I/O 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
3.6.3.3 DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements
Table 29 shows AC parameters for DDR2 I/O. Table 29. AC Parameters for DDR2 I/O
- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
- Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 30 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.
- Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%). Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O Table 29. AC Parameters for DDR2 I/O (continued)
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- Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
- Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%). Table 31 shows the AC requirements for DDR2 I/O.
3.7 Module Timing and Electrical Parameters
This section contains the timing and electrical parameters for i.MX25 modules. Figure 7 shows the reset and presence pulses (RPP) timing for 1-Wire. Figure 7. 1-Wire RPP Timing Diagram Table 31. AC Requirements for DDR2 I/O specification in this document. indicates the voltage at which differential input signal must cross. indicates the voltage at which differential output signal must cross. Cload = 25 pF .
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Figure 10. Read Sequence Timing Diagram
3.7.2 ATA Timing Parameters
implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 34. WR1 /RD Timing Parameters Table 35. Timing Parameters
3.7.2.1 PIO Mode Timing Parameters
Figure 11 shows a timing diagram for PIO read mode. Figure 11. PIO Read Mode Timing Table 35. Timing Parameters (continued)
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Figure 12 gives timing waveforms for PIO write mode. Figure 12. PIO Write Mode Timing Table 36. Timing Parameters for PIO Read Mode
3.7.2.2 Multiword DMA (MDMA) Mode Timing
Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively. Figure 13. MDMA Read Mode Timing Table 37. Timing Parameters for PIO Write Mode
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Figure 14. MDMA Write Mode Timing on timing parameters for MDMA read and write modes.
3.7.2.3 Ultra DMA (UDMA) Mode Timing
diagrams for UDMA in- and out-transfers are provided. Table 38. Timing Parameters for MDMA Read and Write Modes 3 tk1 in the UDMA figures equals (tk –2 × T).
3.7.2.3.1 UDMA In -Transfer Timing
Figure 15 shows the timing for UDMA in-transfer start. Figure 15. Timing for UDMA In-Transfer Start Figure 16 shows the timing for host-terminated UDMA in-transfer. Figure 16. Timing for Host-Terminated UDMA In-Transfer
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Figure 17 shows timing for device-terminated UDMA in-transfer. Figure 17. Timing for Device-Terminated UDMA Transfer Timing parameters for UDMA in-burst are listed in Table 39. Table 39. Timing Parameters for UDMA In-Burst active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. Make ton and toff big enough to avoid bus contention.
3.7.2.4 UDMA Out-Transfer Timing
Figure 18 shows the timing for start of UDMA out-transfer. Figure 18. Timing for UDMA Out-Transfer Start Figure 19 shows timing for host-terminated UDMA out-transfer. Figure 19. Timing for Host-Terminated UDMA Out-Transfer
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Timing parameters for UDMA out-bursts are listed in Table 40.
3.7.3 Digital Audio Mux (AUDMUX) Timing
3.7.4 CMOS Sensor Interface (CSI) Timing
(HSYNC)) and output-only Bayer and statistics data. image (for example, image compression, image pre-filtering, and various data output formats). The following subsections describe the CSI timing in gated and ungated clock modes. Table 40. Timing Parameters UDMA Out-Bursts
3.7.4.1 Gated Clock Mode Timing
HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted. Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge
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3.7.4.2 Ungated Clock Mode Timing
Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge Table 41. CSI Gated Clock Mode Timing Parameters Table 42. CSI Ungated Clock Mode Timing Parameters
3.7.5 Configurable Serial Peripheral Interface (CSPI) Timing
Figure 23. CSPI Master Mode Timing Diagram Figure 24. CSPI Slave Mode Timing Diagram
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3.7.6 External Memory Interface (EMI) Timing
information for these submodules. Table 43. CSPI Interface Timing Parameters 1 The output SCLK transition time is tested with 25 pF drive.
2 Tsclk = CSPI clock period
3 Twait = Wait time, as specified in the sample period control register
4 Tper = CSPI reference baud rate clock period (PERCLK2)
5 Tipg = CSPI main clock IPG_CLOCK period
3.7.6.1 ESDCTL Electrical Specifications
3.7.6.1.1 SDRAM Memory Controller
Figure 25. SDRAM Read Cycle Timing Diagram Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters Note: CKE is high during the read/write cycle.
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Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
Figure 26. SDR SDRAM Write Cycle Timing Diagram 1 SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
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Figure 27. SDRAM Refresh Timing Diagram Table 45. SDR SDRAM Write Timing Parameters 1 SD11 and SD12 are determined by SDRAM controller register settings.
Figure 28. SDRAM Self-Refresh Cycle Timing Diagram Table 46. SDRAM Refresh Timing Parameters 1 SD10 and SD11 are determined by SDRAM controller register settings.
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3.7.6.1.2 Mobile DDR SD RAM–Specific Parameters
Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram Table 47. SDRAM Self-Refresh Cycle Timing Parameters Table 48. Mobile DDR SDRAM Write Cycle Timing Parameters1 1 Test condition: Measured using delay line 5 programmed as follows: ESDCDL Y5[15:0] = 0x0703.
Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 49. Mobile DDR SDRAM Read Cycle Timing Parameters
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3.7.6.1.3 DDR2 SDRAM –Specific Parameters
Figure 31. DDR2 SDRAM Basic Timing Parameters Table 50. DDR2 SDRAM Timing Parameter Table
slew rate of 2 V/ns. Table 51 shows additional values for DDR2-400 and DDR2-533. Table 51. tlS, tlH Derating Values for DDR2-400, DDR2-533 Table 50. DDR2 SDRAM Timing Parameter Table (continued)
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Figure 32. DDR2 SDRAM Write Cycle Timing Diagram Table 52. DDR2 SDRAM Write Cycle Parameter Table Table 53. ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-5331,2,3
Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram SDCLK and SDCLK (inverted clock). Table 54. DDR2 SDRAM Read Cycle Parameter Table1,2 Table 53. ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533 1,2,3 (continued)
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3.7.6.2 NAND Flash Controller (NFC) Timing
under normal mode. Table 55 describes the timing parameters (NF1–NF17) that are shown in the figures. Figure 34. Command Latch Cycle Timing Diagram Figure 35. Address Latch Cycle Timing Diagram SDCLK and SDCLK (inverted clock).
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value; while signal low is defined as 20% of signal value. which are not related to the NFC clock.
3.7.6.3 Wireless External Interface Module (WEIM) Timing
(WE1–WE27) shown in the figure. and DTACK are all captured relative to BCLK rising edge. 1 The Flash clock maximum frequency is 50 MHz. Table 55. NFC Timing Parameters1 (continued)
Figure 38. WEIM Bus Timing Diagram Table 56. WEIM Bus Timing Parameters1
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strength for all controls, address, and BCLK is maximum drive. 1 High is defined as 80% of signal value; low is defined as 20% of signal value. defined as 50% as signal value. Table 56. WEIM Bus Timing Parameters1 (continued)
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Figure 41. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— Figure 42. Synchronous Memory TIming Diagram for Burst Write Access—
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Figure 45. Asynchronous Memory Read Access Figure 46. Asynchronous A/D Muxed Read Access (RWSC = 5)
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Figure 49. DTACK Read Access Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table
Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units. 1 For the value of parameters WE4–WE21, see column BCD = 0 in Table 56. 2 CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles. 3 CS Negation. This bit field determines when the CS signal is negated during read/write cycles. 4 BE Assertion. This bit field determines when the BE signal is asserted during read cycles. 5 BE Negation. This bit field determines when the BE signal is negated during read cycles. 6 Output maximum delay from internal driving ADDR/control FFs to chip outputs. 7 Output maximum delay from CS[x] internal driving FFs to CS[x] out. 8 DATA maximum delay from chip input data to its internal FF . 9 DTACK maximum delay from chip dtack input to its internal FF . Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table (continued)
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3.7.7 Enhanced Serial Audio Interface (ESAI) Timing
Figure 50 shows the ESAI transmit timing diagram. Figure 50. ESAI Transmit Timing frame. In normal mode, the output flag state is asserted for the entire frame period.
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Figure 53 shows the ESAI HCKR timing diagram. Figure 53. ESAI HCKR Timing respectively the conditions and signals cited in Table 60. Table 58. ESAI Timing Conditions Table 59. ESAI Signals Table 60. ESAI General Timing Requirements
62 Clock cycle 4 tSSICC 4 × Tc
63 Clock high period
64 Clock low period
65 SCKR rising edge to FSR out (bl) high — — —
66 SCKR rising edge to FSR out (bl) low — — —
67 SCKR rising edge to FSR out (wr) high 5 —— —
68 SCKR rising edge to FSR out (wr) low 5 —— —
69 SCKR rising edge to FSR out (wl) high — — —
70 SCKR rising edge to FSR out (wl) low — — —
71 Data in setup time before SCKR (SCK in
73 FSR input (bl, wr) high before SCKR falling
78 SCKT rising edge to FST out (bl) high — — —
79 SCKT rising edge to FST out (bl) low — — —
80 SCKT rising edge to FST out (wr) high 5 —— —
81 SCKT rising edge to FST out (wr) low 5 —— —
82 SCKT rising edge to FST out (wl) high — — —
83 SCKT rising edge to FST out (wl) low — — —
84 SCKT rising edge to data out enable from
85 SCKT rising edge to transmitter #0 drive
Table 60. ESAI General Timing Requirements (continued)
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3.7.8 Enhanced Secured Digital Ho st Controller (eSDHCv2) Timing
86 SCKT rising edge to data out valid — — —
87 SCKT rising edge to data out high
88 SCKT rising edge to transmitter #0 drive
89 FST input (bl, wr) setup time before SCKT
90 FST input (wl) setup time before SCKT falling
92 FST input (wl) to data out enable from high
93 FST input (wl) to transmitter #0 drive enable
94 Flag output valid after SCKT rising edge — — —
95 HCKR/HCKT clock cycle — 2 x T C 15 — — ns
2 In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative
3 In the “Expression” column, TC = 7.5 ns. 4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. until the second-to-last bit-clock of the first word in the frame. 6 Periodically sampled and not 100% tested.
Figure 54. eSDHCv2 Timing Table 61. eSDHCv2 Interface Timing Specification 1 In low-speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. frequency can be any value between 0 ~ 50 MHz. frequency can be any value between 0 ~ 52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
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3.7.9 Fast Ethernet Controller (FEC) Timing
operating at a voltage of 3.3 V . The following subsections describe the timing for MII and RMII modes.
3.7.9.1 FEC MII Mode Timing
3.7.9.1.4 MII Receive Signa l Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
Figure 55. MII Receive Signal Timing Diagram 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. Table 62. MII Receive Signal Timing
3.7.9.1.5 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
Figure 56. MII Transmit Signal Timing Diagram 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
3.7.9.1.6 MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
Figure 57. MII Async Inputs Timing Diagram Table 63. MII Transmit Signal Timing
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1 FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
3.7.9.2 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Figure 58. MII Serial Management Channel Timing Diagram Table 64. MII Asynchronous Inputs Signal Timing Table 65. MII Serial Management Channel Timing M10 FEC_MDC falling edge to FEC_MDIO output invalid (min. M11 FEC_MDC falling edge to FEC_MDIO output valid (max.
3.7.9.3 RMII Mode Timing
FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and FEC_RX_ER. Figure 59. RMII Mode Signal Timing Diagram Table 66. RMII Signal Timing
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3.7.10 Controller Area Network (Flex CAN) Transceiver Parameters and
Table 67 and Table 68 show voltage requirements for the FlexCAN transceiver Tx and Rx pins. Figure 60. FlexCAN Timing Diagram Table 67. Tx Pin Characteristics Table 68. Rx Pin Characteristics
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3.7.11 Inter IC Communication (I 2C) Timing
parameters (IC1–IC6) shown in the figure. Figure 64. I2C Module Timing Diagram Table 69. I2C Module Timing Parameters: 3.0 V +/–0.30 V
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal. specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF . Table 70. I2C Module Timing Parameters: 1.8 V +/– 0.10 V
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3.7.12 Liquid Crystal Display Controller (LCDC) Timing
Table 72 list the timing parameters used in the associated figures. Figure 65. LCDC Non-TFT Mode Timing Diagram Table 71. LCDC Non-TFT Mode Timing Parameters
1 T is pixel clock period
Figure 66. LCDC TFT Mode Timing Diagram
3.7.13 Pulse Width Modulator (PWM) Timing Parameters
Figure 67 depicts the timing of the PWM, and Table 73 lists the PWM timing characteristics. pulse width modulator output (PWMO) external pin. Table 72. LCDC TFT Mode Timing Parameters
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Figure 67. PWM Timing
3.7.14 Subscriber Identity Module (SIM) Timing
Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals). Typically a port uses five signals. SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate. information see ISO/IEC 7816). Table 73. PWM Output Timing Parameter
1 System CLK frequency 1
1 CL of PWMO = 30 pF
Figure 68. SIM Clock Timing Diagram Table 74 defines the general timing requirements for the SIM interface. Table 74. Timing Specifications, High Drive Strength
2 With C = 50 pF
3 With C = 50 pF
4 With Cin = 30 pF , Cout = 30 pF ,
5 With Cin = 30 pF ,
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3.7.14.1 SIM Reset Sequences
3.7.14.1.1 SIM Cards w ith Internal Reset
After 200 clock cycles, SIM x_DATAy_RX_TX must be asserted. 400–40000 clock cycles after T0. Figure 69. Internal Reset Card Reset Sequence Table 75 defines the general timing requirements for the SIM interface.
3.7.14.1.2 SIM Cards with Active Low Reset
After 200 clock cycles, SIM x_DATAy_RX_TX must be asserted. received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. Table 75. Timing Specifications, Internal Reset Card Reset Sequence
Figure 70. Active-Low-Reset SIM Card Reset Sequence Table 76 defines the general timing requirements for the SIM interface.
3.7.14.2 SIM Power-Down Sequence
requirements for parameters (SI7–SI10) shown in the figure. SIM card removal detection; or it may be launched by the processor. Table 76. Timing Specifications, Active-Low-Reset SIM Card Reset Sequence
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Figure 71. SmartCard Interface Power Down AC Timing
3.7.15 System JTAG Co ntroller (SJC) Timing
Figure 72. Test Clock Input Timing Diagram Table 77. Timing Requirements for Power-down Sequence
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Figure 75. TRST Timing Diagram Table 78. SJC Timing Parameters core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.
2 VM – mid point voltage
3.7.16 Smart Liquid Crystal Display Controller (SLCDC)
Table 80 describe the timing parameters shown in the respective figures. Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device
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Figure 77. SLCDC Timing Diagram—Parallel Transfers to LCD Device Table 79. SLCDC Serial Interface Timing Parameters
3.7.17 Synchronous Serial Interface (SSI) Timing
3.7.17.1 SSI Transmitter Timing with Internal Clock
Figure 78. SSI Transmitter with Internal Clock Timing Diagram Table 80. SLCDC Parallel Interface Timing Parameters
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the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on pads when SSI is being used for a data transfer. ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI. Table 81. SSI Transmitter Timing with Internal Clock
3.7.17.2 SSI Receiver Timing with Internal Clock
parameters (SS1–SS51) shown in the figure. Figure 79. SSI Receiver Internal Clock Timing Diagram Table 82. SSI Receiver Timing with Internal Clock
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the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on pads when SSI is being used for a data transfer. ”Tx” and “Rx” refer to the transmit and receive sections of the SSI.
3.7.17.3 SSI Transmitter Timing with External Clock
parameters (SS22-SS46) shown in the figure. Figure 80. SSI Transmitter with External Clock Timing Diagram Table 82. SSI Receiver Timing with Internal Clock (continued)
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures. All timings are on pads when SSI is being used for data transfer. ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI. Table 83. SSI Transmitter Timing with External Clock
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3.7.17.4 SSI Receiver Timing with External Clock
(SS22–SS41) used in the figure. Figure 81. SSI Receiver with External Clock Timing Diagram the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on pads when SSI is being used for data transfer. Table 84. SSI Receiver Timing with External Clock
”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.
3.7.18 Touchscreen ADC Electrical Specifications and Timing
This section describes the electrical specifications, operation modes, and timing of the touchscreen ADC.
3.7.18.1 ADC Electrical Specifications
Table 85 shows the electrical specifications for the touchscreen ADC. Table 85. Touchscreen ADC Electrical Specifications
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3.7.18.2 ADC Timing Diagrams
soc signals applied to the touchscreen controller. touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA. 3 At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 °C, fclk = 1.75 MHz, any process corner, unless otherwise noted. 4 Value measured with a –0.5 dBFS sinusoidal input signal and computed with the code density test. Table 85. Touchscreen ADC Electrical Specifications (continued)
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated. Figure 82. Start-up Sequence xnsw) are totally asynchronous. selection during clock cycles 2 to 13. only after an eoc pulse has been acquired, during the last clock cycle (14).
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Figure 83 shows the timing for ADC normal operation. Figure 83. Timing for ADC Normal Operation
any value of N equal or greater than 1. Figure 84. ADC Usage with Idle Cycles Between Conversions
3.7.19 UART Timing
This section describes the timing of the UART module in serial and parallel mode.
3.7.19.1 UART RS-232 Serial Mode Timing
3.7.19.1.1 UART Transmit Ti ming in RS-232 Serial Mode
bit. Table 86 describes the timing parameter (UA1) shown in the figure. Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram
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3.7.19.1.2 UART Receive Ti ming in RS-232 Serial Mode
Figure 86 shows the UART receive timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit. Table 87 describes the timing parameter (UA2) shown in the figure. Figure 86. UART RS-232 Serial Mode Receive Timing Diagram
3.7.19.2 UART Infrared (IrDA) Mode Timing
The following subsections describe the UART transmit and receive timing in IrDA mode.
3.7.19.2.3 UART IrDA Mode Transmit Timing
Figure 87 depicts the UART transmit timing in IrDA mode, showing only 8 data bits and 1 stop bit. Table 88 describes the timing parameters (UA3–UA4) shown in the figure. Figure 87. UART IrDA Mode Transmit Timing Diagram Table 86. UART RS-232 Serial Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 87. UART RS-232 Serial Mode Receive Timing Parameters not exceed 3/(16 × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
3.7.19.2.4 UART IrDA Mode Receive Timing
Figure 88 shows the UART receive timing for IrDA mode, for a format of 8 data bits and 1 stop bit. Table 89 describes the timing parameters (UA5–UA6) shown in the figure. Figure 88. UART IrDA Mode Receive Timing Diagram
3.7.20 USBOTG Timing
3.7.20.1 USB Serial Interface Timing
The following subsections describe the timings for these four modes. Table 88. UART IrDA Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 89. UART IrDA Mode Receive Timing Parameters not exceed 3/(16 × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
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3.7.20.1.1 DAT_SE0 Bidi rectional Mode Timing
Table 90 defines the DAT_SE0 bidirectional mode signals. Figure 89 shows the USB transmit waveform in DAT_SE0 bidirectional mode diagram. Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Figure 90 shows the USB receive waveform in DAT_SE0 bidirectional mode diagram. Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode Table 90. Signal Definitions—DAT_SE0 Bidirectional Mode
Table 91 shows the OTG port timing specification in DAT_SE0 bidirectional mode.
3.7.20.1.2 DAT_SE0 Unid irectional Mode Timing
Table 92 defines the DAT_SE0 unidirectional mode signals. Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode Table 91. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode Table 92. Signal Definitions—DAT_SE0 Unidirectional Mode
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Figure 92 shows the USB receive waveform in DAT_SE0 unidirectional mode diagram. Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 93 shows the USB port timing specification in DAT_SE0 unidirectional mode.
3.7.20.1.3 VP_VM Bidi rectional Mode Timing
Table 94 defines the VP_VM bidirectional mode signals. Table 93. USB Port Timing Specification in DAT_SE0 Unidirectional Mode Table 94. Signal Definitions—VP_VM Bidirectional Mode
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3.7.20.1.4 VP_VM Unid irectional Mode Timing
Table 96 defines the signals for USB in VP_VM unidirectional mode. Figure 95 shows the USB transmit waveform in VP_VM unidirectional mode diagram. Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode Table 96. Signal Definitions for USB VP_VM Unidirectional Mode Table 95. USB Port Timing Specifications in VP_VM Bidirectional Mode (continued)
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3.7.20.2 USB Parallel Interface Timing
Table 98 defines the USB parallel interface signals. parameters (USB15–USB17) shown in the figure. Figure 97. USB Parallel Mode Transmit/Receive Waveform
4 Package Information and Contact Assignment
All dimensions in millimeters. Dimensioning and toleranc ing per ASME Y14.5M-1994. Table 98. Signal Definitions for USB Parallel Interface Table 99. USB Timing Specification in Parallel Mode
Maximum solder bump diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder bumps. Parallelism measurement shall exclude any effect of mark on top surface of package. Figure 98. zzxz17×17 i.MX25 Production Package
4.2 Ground, Power, Sense, and Reference Contact Assignments
Table 100 shows the 17×17 mm package ground, power, sense, and reference contact assignments. Table 100. 17×17 mm Package Ground, Power Sense, and Reference Contact Assignments
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Table 100. 17×17 mm Package Ground, Power Sense, and Reference Contact Assignments (continued)
Table 101 lists the 17×17 mm package i.MX25 signal contact assignments. Table 101. 17×17 mm Package i.MX25 Signal Contact Assignment
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Table 101. 17×17 mm Package i.MX25 Signal Contact Assignment (continued)
2 Y7 LCDC GPIO OUTPUT Low
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2 H18 CSI GPIO OUTPUT Low
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Table 102 lists the 17×17 mm package i.MX25 no connect contact assignments. 1 The state immediately after reset and before ROM firmware or software has executed. 2 During power-on reset this port acts as input for fuse override signal. 3 During power-on reset this port acts as output for diagnostic signal. Table 102. 17×17 mm Package i.MX25 No Connect Contact Assignments
Table 103 shows the i.MX25 17×17 package ball map. Table 103. i.MX25 17×17 Package Ball Map
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Table 103. i.MX25 17×17 Package Ball Map (continued)
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All dimensions in milli meters.Dimensioning and tolerancing per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on package’s top surface. Figure 99. 12×12 mm i.MX25 Production Package
4.6 Ground, Power, Sense, and Reference Contact Assignments
Table 104 shows the 12×12 mm package ground, power, sense, and reference contact assignments. Table 104. 12x12 mm Package Ground, Power Sense, and Reference Contact Assignments
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Table 105 lists the 12×12 mm package i.MX25 signal contact assignments. Table 105. 12x12 mm Package i.MX25 Signal Contact Assignment Table 104. 12x12 mm Package Ground, Power Sense, and Reference Contact Assignments (continued)
Table 105. 12x12 mm Package i.MX25 Signal Contact Assignment (continued)
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2 AB10 LCDC GPIO OUTPUT Low
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2 F22 CSI GPIO OUTPUT Low
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Table 106 lists the 12×12 mm package i.MX25 no connect contact assignments. 1 The state immediately after reset and before ROM firmware or software has executed. 2 During power-on reset this port acts as input for fuse override signal. 3 During power-on reset this port acts as output for diagnostic signal. Table 106. 12×12 mm Package i.MX25 No Connect Contact Assignments
Table 107 shows the i.MX25 12×12 package ball map. Table 107. i.MX25 12×12 Package Ball Map
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Table 107. i.MX25 12×12 Package Ball Map (continued)
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5 Revision History
Table 108 summarizes revisions to this document. Table 108. Revision History Updated Table 4, "Signal Considerations," on page 9 for NVCC_DRYICE signal. Updated the third note for Table 6, "DC Operating Conditions," on page 11. Added Table 9, "Recommended External Crystal Specifications," on page 13. Added Table 10, "Recommended External Reference Clock Specifications," on page 13. and Reference Contact Assignments," on page 125. Updated Table 101, "17×17 mm Package i.MX25 Signal Contact Assignment," on page 127. and Reference Contact Assignments," on page 139. "12x12 mm Package Ground, Power Sense, and Reference Contact Assignments," on page 139. Updated Table 105, "12x12 mm Package i.MX25 Signal Contact Assignment," on page 140. 5 08/2010 Updated Table 56, "WEIM Bus Timing Parameters," on page 71 to include new row for WE19. 4 06/2010 Updated Table 1, “Ordering Information,” to include new part numbers. 3 03/2010 Updated Table 1, “Ordering Information,” to include new part numbers. 2 12/2009 Updated Table 1, “Ordering Information,” to include new part numbers. 1 10/2009 Updated Table 1, “Ordering Information,” to include new part numbers. Updated values in Table 56, “WEIM Bus Timing Parameters.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 7 Freescale Semiconductor 153 THIS PAGE INTENTIONALLY LEFT BLANK
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