MCF8316DULVRGFR

MCF8316D TI | Alldatasheet

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Technical content

MCF8316D Sensorless Field Oriented Control (FOC) Integrated FET BLDC Driver

1 Features

• Three-phase BLDC motor driver with integrated sensorless motor control algorithm – Code-free Field Oriented Control (FOC) – Speed, current, power, and voltage control modes – Forward and reverse windmilling support – Configurable power and speed limit – Lead angle adjustment for high efficiency – Improved acoustic performance with soft-start, soft-stop and dead time compensation – Offline motor parameter measurement with Motor Parameter Extraction Tool (MPET) – Analog, PWM, frequency, or I2C based speed input – Configurable motor start-up and stop options – Flux weakening for high-speed operation – Anti-voltage surge (AVS) protection – Variable monitoring through DACOUT pins
• 4.5 to 35V operating voltage (40V abs max)
• High output current capability: 8A peak
• Low MOSFET on-state resistance – RDS(ON) (HS + LS) at TA = 25°C : 95mΩ (typ.)
• Low power sleep mode: Refer Table 6-8 – 5µA (maximum) at VVM = 24V, TA = 25°C
• Speed loop accuracy: 3% with internal clock and 1% with external clock reference
• Configurable EEPROM with R/W security to store device configuration
• Does not require external current sense resistors; uses built-in current sensing
• Built-in 3.3V, 20mA LDO regulator
• Built-in 3.3V/5V, 170mA buck regulator
• Dedicated DRVOFF pin to disable (Hi-Z) outputs
• Spread spectrum, PWM dithering, and slew rate for EMI reduction
• Suite of integrated protection features – Supply under voltage lockout (UVLO) – Supply over voltage protection (OVP) – Motor lock detection – Configurable current limit – Thermal warning and shutdown (OTW/TSD) – Fault condition indication pin (nFAULT) – Optional fault diagnostics over I2C interface

2 Applications

• Brushless-DC (BLDC) Motor Modules
• Washer and Dishwashers Pumps
• Air Purifiers and Humidifier Fans
• Small Home Appliances
• Residential and Living Fans
• Projector Color Wheels

3 Description

The MCF8316D provides a single-chip, code-free sensorless FOC device for customers driving speed- controlled 12 to 24V brushless-DC motors (BLDC) or Permanent Magnet Synchronous motor (PMSM) up to 8A peak current. The MCF8316D integrates three ½-bridges with 40V absolute maximum capability and a very low R DS(ON) of 95mΩ (high-side + low-side FETs). MCF8316D integrates power management circuits including a voltage-adjustable buck regulator (3.3V/5V, 170mA) and LDO (3.3V, 20mA) that can be used to power external circuits. The FOC algorithm configuration can be stored in non-volatile EEPROM, which allows the device to operate stand-alone once the device has been configured. The device receives a speed command through a PWM input, analog voltage, variable frequency square wave or I 2C command. There are a large number of protection features integrated into the MCF8316D, intended to protect the device, motor, and system against fault events. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) 2 MCF8316DVRGFR VQFN (40) 7.00mm x 5.00mm MCF8316DULVRGFR3 VQFN (40) 7.00mm x 5.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable (3) Device available for preview only Documentation for reference:

• Refer MCF8316D EVM User's Guide
• Refer to the MCF8316D EVM GUI MCF8316D MOSFETs Buck/LDO Regulator Integrated Current Sensing EEPROM Sensorless FOC DIRECTION BRAKE I2C Op onal during opera on; I2C speed, diagnos cs, or on-the- y con gura on PWM, analog, frequency or commanded over I2C SPEED FG Speed feecback nFAULT A B C 4.5 to 35-V (40-V abs max) 8-A peak output current, typically 12 to 24-V Buck out 3.3 or 5.0-V, up to 170-mA LDO out 3.3-V, up to 20-mA Simplified Schematic MCF8316D SLLSFX9 – DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

5.6 Characteristics of the SDA and SCL bus for

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

EXT_CLK DACOUT1 DACOUT2 ALARM DIR BRAKE DVDD DGND EXT_WD AVDD AGND SCL SPEED/WAKE SDA FG VM CP CPH CPL FB_BK SW_BK VM VM PGND DRVOFF NC PGND PGND GND_BK NC NC NC OUT A OUT A OUT B OUT B OUT C OUT C DACOUT2/SOX Thermal Pad Figure 4-1. MCF8316D, 40-Pin VQFN With Exposed Thermal Pad, Top View Table 4-1. Pin Functions PIN 40-pin package TYPE(1) DESCRIPTION NAME MCF8316D AGND 26 GND Device analog ground. Refer Layout Guidelines for connection recommendation. ALARM 39 O Alarm signal: push-pull output. Pulled logic high during fault condition, if enabled. If ALARM pin is not used, leave it floating. AVDD 27 PWR O 3.3V internal regulator output. Connect a X7R, 1µF, 10V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 20mA for external circuits. BRAKE 35 I High → Brake the motor Low → Normal motor operation If BRAKE pin is not used, connect to AGND directly. If BRAKE pin is used to brake the motor, use an (optional) external 10kΩ pull-down resistor (to AGND) for better noise rejection. CP 8 PWR Charge pump output. Connect a X7R, 1µF, 16V ceramic capacitor between the CP and VM pins. CPH 7 PWR Charge pump switching node. Connect a X7R, 47nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.CPL 6 PWR DACOUT1 36 O DAC output DACOUT1 DACOUT2 37 O DAC output DACOUT2 DACOUT2/S OX 38 O Multi-purpose pin: DAC output when configured as DACOUT2 CSA output when configured as SOX www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: MCF8316D

Table 4-1. Pin Functions (continued) PIN 40-pin package TYPE(1) DESCRIPTION NAME MCF8316D DGND 2 GND Device digital ground. Refer Layout Guidelines for connection recommendation. DIR 34 I Direction of motor spinning; When low, phase driving sequence is OUT A → OUT C → OUT B When high, phase driving sequence is OUT A → OUT B → OUT C If DIR pin is not used, connect to AGND or AVDD directly (depending on phase driving sequence needed). If DIR pin is used for changing motor spin direction, use an (optional) external 10kΩ pull-down resistor (to AGND) for better noise rejection. DRVOFF 21 I Coast (Hi-Z) all six MOSFETs as long as DRVOFF is high. If DRVOFF pin is not used, connect to AGND directly. If DRVOFF pin is to be used for instantly coasting (Hi-Z) the MOSFETs, use an external 10kΩ pull-down resistor (to AGND) for better noise rejection. DVDD 1 PWR 1.5V internal regulator output. Connect a X7R, 1µF, 6.3V ceramic capacitor between the DVDD and DGND pins. EXT_CLK 33 I External clock reference input in external clock reference mode. EXT_WD 32 I External watchdog input. FB_BK 3 PWR I/O Feedback for buck regulator output control. Connect to buck regulator output after the inductor/resistor. FG 29 O Motor speed indicator : open-drain output that requires an external pull-up resistor to 1.8V to 5.0V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. GND_BK 4 GND Buck regulator ground. Refer Layout Guidelines for connection recommendation. NC 22, 23, 24, 25 - No connection. Leave these pins floating. These pins can also be tied to AGND plane and thermal pad for better heat dissipation. nFAULT 40 O Fault indicator. Pulled logic-low with fault condition; open-drain output that requires an external pull-up resistor to 1.8V to 5.0V. An optional internal pull-up resistor to AVDD is enabled by setting PULLUP_ENABLE to 1b; no external pull-up resistor should be used when internal pull-up resistor is enabled. OUTA 13, 14 PWR O Half-bridge output A OUTB 16, 17 PWR O Half-bridge output B OUTC 19, 20 PWR O Half-bridge output C PGND 12, 15, 18 GND Device power ground. Refer Layout Guidelines for connection recommendation. SCL 31 I I2C clock input SDA 30 I/O I2C data line SPEED/ WAKE 28 I Device speed input; supports analog, PWM or frequency based speed input. The speed pin input mode can be configured through SPEED_MODE. SW_BK 5 PWR Buck switch node. Connect this pin to an inductor or resistor. VM 9, 10, 11 PWR I Device and motor power supply. Connect to motor supply voltage; bypass to PGND with one 0.1µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. Thermal pad GND Must be connected to AGND. (1) I = input, O = output, GND = ground, PWR = power, NC = no connect MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply pin voltage (VM) –0.3 40 V Power supply voltage ramp (VM) 4 V/µs Voltage difference between ground pins (GND_BK, DGND, PGND, AGND) –0.3 0.3 V Charge pump voltage (CPH, CP) –0.3 VVM + 6 V Charge pump negative switching pin voltage (CPL) –0.3 VVM +0.3 V Switching regulator pin voltage (FB_BK) –0.3 6 V Switching node pin voltage (SW_BK) –0.3 VVM +0.3 V Analog regulator pin voltage (AVDD) –0.3 4 V Digital regulator pin voltage (DVDD) –0.3 1.7 V Logic pin input voltage (BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED) –0.3 6 V Open drain pin output voltage (nFAULT, FG) –0.3 6 V Output pin voltage (OUTA, OUTB, OUTC) –1 VVM + 1 V Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage tempertaure, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per JEDEC specification JS-002(2) ±750 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted) MIN NOM MAX UNIT VVM Power supply voltage VVM 4.5 24 35 V IOUT (1) Peak output winding current OUTA, OUTB, OUTC 8 A VIN_LOGIC Logic input voltage BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD, SPEED, SDA, SCL –0.1 5.5 V VOD Open drain pullup voltage nFAULT, FG –0.1 5.5 V IOD Open drain output current capability nFAULT, FG 5 mA TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) Power dissipation and thermal limits must be observed

5.4 Thermal Information

THERMAL METRIC(1) MCF8316D UNITRGF (VQFN)

40 Pins

RθJA Junction-to-ambient thermal resistance 25.7 °C/W www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: MCF8316D

THERMAL METRIC(1) MCF8316D UNITRGF (VQFN) RθJC(top) Junction-to-case (top) thermal resistance 15.2 °C/W RθJB Junction-to-board thermal resistance 7.3 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 7.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES IVMQ VM sleep mode current VVM > 6 V, VSPEED = 0, TA = 25 °C 3 5 µA VSPEED = 0, TA = 125 °C 3.5 7 µA IVMS VM standby mode current VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, TA = 25 °C, LBK = 47 µH, CBK = 22 µF 8 15 mA VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF 25 28 mA VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, LBK = 47 µH, CBK = 22 µF 8 15 mA VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF 25 28 mA IVM VM operating mode current VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TJ = 25 °C, LBK = 47 µH, CBK = 22 µF, No Motor Connected 11 18 mA VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TJ = 25 °C, RBK = 22 Ω, CBK = 22 µF, No Motor Connected 27 32 mA VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), LBK = 47 µH, CBK = 22 µF, No Motor Connected 11 17 mA VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), RBK = 22 Ω, CBK = 22 µF, No Motor Connected 28 33 mA VAVDD Analog regulator voltage 0 mA ≤ IAVDD ≤ 20 mA 3.125 3.3 3.465 V IAVDD External analog regulator load 20 mA VDVDD Digital regulator voltage 1.4 1.55 1.65 V VVCP Charge pump regulator voltage VCP with respect to VM 4.0 4.7 5.5 V MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BUCK REGULATOR VBK Buck regulator average voltage (LBK = 47 µH, CBK = 22 µF) VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 11b 5.2 5.7 5.8 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 170 mA VVM– IBK*(RLBK +2) 1 V VBK Buck regulator average voltage (LBK = 22 µH, CBK = 22 µF) VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 11b 5.2 5.7 5.8 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 20 mA VVM– IBK*(RLBK +2)1 V VBK Buck regulator average voltage (RBK = 22 Ω, CBK = 22 µF) VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V VVM > 6.7 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 11b 5.2 5.7 5.8 V VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 10 mA VVM– IBK*(RLBK +2) (1) V VBK_RIP Buck regulator ripple voltage VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, Buck regulator with inductor, LBK = 47 µH, CBK = 22 µF –100 100 mV VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, Buck regulator with inductor, LBK = 22 µH, CBK = 22 µF –100 100 mV VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, Buck regulator with resistor, RBK = 22 Ω, CBK = 22 µF –100 100 mV IBK External buck regulator load LBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 1b 170 mA LBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 0b 170 – IAVDD mA LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 1b 20 mA LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 0b 20 – IAVDD mA RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b 10 mA RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b 10 – IAVDD mA www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: MCF8316D

at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSW_BK Buck regulator switching frequency Regulation Mode 20 535 kHz Linear Mode 20 535 kHz VBK_UV Buck regulator undervoltage lockout VBK rising, BUCK_SEL = 00b 2.7 2.8 2.95 V VBK falling, BUCK_SEL = 00b 2.5 2.6 2.7 V VBK rising, BUCK_SEL = 01b 4.3 4.4 4.55 V VBK falling, BUCK_SEL = 01b 4.1 4.2 4.38 V VBK rising, BUCK_SEL = 10b 2.7 2.8 2.95 V VBK falling, BUCK_SEL = 10b 2.5 2.6 2.7 V VBK rising, BUCK_SEL = 11b 4.3 4.4 4.55 V VBK falling, BUCK_SEL = 11b 4.1 4.2 4.38 V VBK_UV_HYS Buck regulator undervoltage lockout hysteresis Rising to falling threshold, BUCK_SEL = 00b 90 200 400 mV Rising to falling threshold, BUCK_SEL = 01b 90 200 400 mV Rising to falling threshold, BUCK_SEL = 10b 90 200 400 mV Rising to falling threshold, BUCK_SEL =11b 90 200 400 mV IBK_CL Buck regulator current limit threshold BUCK_CL = 0b 360 600 910 mA BUCK_CL = 1b 80 150 260 mA IBK_OCP Buck regulator overcurrent protection trip point 2 3 4 A tBK_RETRY Overcurrent protection retry time 0.7 1 1.3 ms DRIVER OUTPUTS RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6 V, IOUT = 1 A, TA = 25°C 95 125 mΩ VVM < 6 V, IOUT = 1 A, TA = 25°C 105 130 mΩ VVM > 6 V, IOUT = 1 A, TJ = 150 °C 140 185 mΩ VVM < 6 V, IOUT = 1 A, TJ = 150 °C 145 190 mΩ SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM = 24 V, SLEW_RATE = 10b 80 125 185 V/µs VVM = 24 V, SLEW_RATE = 11b 130 200 280 V/µs SR Phase pin slew rate switching high to low (Falling from 80 % to 20 % VVM = 24 V, SLEW_RATE = 10b 80 125 185 V/µs VVM = 24 V, SLEW_RATE = 11b 110 200 280 V/µs tDEAD Output dead time (high to low / low to high) VVM = 24 V, SLEW_RATE = 10b 650 1000 ns VVM = 24 V, SLEW_RATE = 11b 500 750 ns MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SPEED INPUT - PWM MODE ƒPWM PWM input frequency 0.01 100 kHz ResPWM PWM input resolution 0.01 kHz ≤ fPWM < 0.35 kHz 11 12 13 bits 0.35 kHz ≤ fPWM < 2 kHz 12 13 14 bits 2 kHz ≤ fPWM < 3.5 kHz 11 11.5 12 bits 3.5 kHz ≤ fPWM < 7 kHz 13 13.5 14 bits 7 kHz ≤ fPWM < 14 kHz 12 12.5 13 bits 14 kHz ≤ fPWM < 29.3 kHz 11 11.5 12 bits 29.3 kHz ≤ fPWM < 60 kHz 10 10.5 11 bits 60 kHz ≤ fPWM ≤ 100 kHz 8 9 10 bits SPEED INPUT - ANALOG MODE VANA_FS Analog full-speed voltage 2.95 3 3.05 V VANA_RES Analog voltage resolution 732 μV SPEED INPUT - FREQUENCY MODE ƒPWM_FREQ PWM input frequency range Duty cycle = 50% 3 32767 Hz SLEEP MODE VEN_SL Analog voltage to enter sleep state SPEED_MODE = 00b (analog mode) 40 mV VEX_SL Analog voltage to exit sleep state SPEED_MODE = 00b (analog mode) 2.2 V tDET_ANA Time needed to detect wake-up signal on SPEED pin SPEED_MODE = 00b (analog mode) VSPEED > VEX_SL 0.5 1 1.5 μs tWAKE Wake-up time from sleep state VSPEED > VEX_SL to DVDD voltage available, SPEED_MODE = 00b (analog mode) 3 5 ms tEX_SL_DR_A NA Time taken to drive motor after wake-up from sleep state (MCF8316D) SPEED_MODE = 00b (analog mode), DVDD voltage available to first output PWM pulse, ISD detection disabled 30 ms tEX_SL_DR_A NA Time taken to drive motor after wake-up from sleep state (MCF8316DUL) SPEED_MODE = 00b (analog mode), DVDD voltage available to first output PWM pulse, ISD detection disabled 180 ms tDET_PWM Time needed to detect wake-up signal on SPEED pin SPEED_MODE = 01b (PWM mode) VSPEED > VIH 0.5 1 1.5 μs tWAKE_PWM Wake-up time from sleep state VSPEED > VIH to DVDD voltage available, SPEED_MODE = 01b (PWM mode) 3 5 ms tEX_SL_DR_P WM Time taken to drive motor after wake-up from sleep state (MCF8316D) SPEED_MODE = 01b (PWM mode), DVDD voltage available to first output PWM pulse, ISD detection disabled 30 ms tEX_SL_DR_P WM Time taken to drive motor after wake-up from sleep state (MCF8316DUL) SPEED_MODE = 01b (PWM mode), DVDD voltage available to first output PWM pulse, ISD detection disabled 180 ms www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: MCF8316D

at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDET_SL_ANA Time needed to detect sleep command SPEED_MODE = 00b (analog mode), VSPEED < VEN_SL , SLEEP_ENTRY_TIME = 00b 0.035 0.05 0.065 ms SPEED_MODE = 00b (analog mode), VSPEED < VEN_SL , SLEEP_ENTRY_TIME = 01b 0.14 0.2 0.26 ms SPEED_MODE = 00b (analog mode), VSPEED < VEN_SL , SLEEP_ENTRY_TIME = 10b 14 20 26 ms SPEED_MODE = 00b (analog mode), VSPEED < VEN_SL , SLEEP_ENTRY_TIME = 11b 140 200 260 ms tDET_SL_PWM Time needed to detect sleep command SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 00b 0.035 0.05 0.065 ms SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 01b 0.14 0.2 0.26 ms SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 10b 14 20 26 ms SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), VSPEED < VIL, SLEEP_ENTRY_TIME = 11b 140 200 260 ms tEN_SL Time needed to stop driving motor after detecting sleep command VSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM mode or Frequency mode) or VSPEED < VIL and DIGITAL_SPEED_CTRL = 0b (I2C mode) 1 2 ms MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STANDBY MODE tEX_SB_DR_A NA Time taken to drive motor after exiting standby state SPEED_MODE = 00b (analog mode) VSPEED > VEX_SB, ISD detection disabled 6 ms tEX_SB_DR_P WM Time taken to drive motor after exiting standby state SPEED_MODE = 01b (PWM mode) VSPEED > VIH, ISD detection disabled 6 ms tDET_SB_ANA Time needed to detect standby command SPEED_MODE = 00b (analog mode) VSPEED < VEN_SB 0.5 1 2 ms tEN_SB_PWM Time needed to detect standby command SPEED_MODE = 01b (PWM mode) VSPEED < VIL, SLEEP_ENTRY_TIME = 00b 0.035 0.05 0.065 ms SPEED_MODE = 01b (PWM mode) VSPEED < VIL, SLEEP_ENTRY_TIME = 01b 0.14 0.2 0.26 ms SPEED_MODE = 01b (PWM mode) VSPEED < VIL, SLEEP_ENTRY_TIME = 10b 14 20 26 ms SPEED_MODE = 01b (PWM mode) VSPEED < VIL, SLEEP_ENTRY_TIME = 11b 140 200 260 ms tEN_SB_DIG Time needed to detect standby command SPEED_MODE = 10b (I2C mode), DIGITAL_SPEED_CTRL = 0b 1 2 ms tEN_SB_FREQ Time needed to detect standby command SPEED_MODE = 11b (Frequency mode), VSPEED < VIL 4000 ms tEN_SB Time needed to stop driving motor after detecting standby command VSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM or Frequency mode) or DIGITAL_SPEED_CTRL = 0b (I2C mode) 1 2 ms LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED) VIL Input logic low voltage AVDD = 3 to 3.6 V 0.25*AV DD V VIH Input logic high voltage AVDD = 3 to 3.6 V 0.65*AV DD V VHYS Input hysteresis 50 500 800 mV IIL Input logic low current AVDD = 3 to 3.6 V -0.15 0.15 µA IIH Input logic high current AVDD = 3 to 3.6 V -0.4 0.15 µA RPD_SPEED Input pulldown resistance SPEED pin To GND 0.6 1 1.4 MΩ OPEN-DRAIN OUTPUTS (nFAULT, FG) VOL Output logic low voltage IOD =-5 mA 0.4 V IOZ Output logic high current VOD = 3.3 V 0 0.5 µA I2C Serial Interface VI2C_L LOW-level input voltage -0.5 0.3*AVD D V VI2C_H HIGH-level input voltage 0.7*AVD D 5.5 V VI2C_HYS Hysteresis 0.05*AV DD V VI2C_OL LOW-level output voltage open-drain at 2mA sink current 0 0.4 V II2C_OL LOW-level output current VI2C_OL = 0.6V 6 mA II2C_IL Input current on SDA and SCL -102 102 µA Ci Capacitance for SDA and SCL 10 pF www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: MCF8316D

at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tof Output fall time from VI2C_H(min) to VI2C_L(max) Standard Mode 2503 ns Fast Mode 2503 ns tSP Pulse width of spikes that must be suppressed by the input filter Fast Mode 0 504 ns OSCILLATOR fOSCREF External clock reference EXT_CLK_CONFIG = 000b 8 kHz EXT_CLK_CONFIG = 001b 16 kHz EXT_CLK_CONFIG = 010b 32 kHz EXT_CLK_CONFIG = 011b 64 kHz EXT_CLK_CONFIG = 100b 128 kHz EXT_CLK_CONFIG = 101b 256 kHz EXT_CLK_CONFIG = 110b 512 kHz EXT_CLK_CONFIG = 111b 1024 kHz EEPROM EEProg Programming voltage 1.35 1.5 1.65 V EERET Retention TA = 25 ℃ 100 Years TJ = -40 to 150 ℃ 10 Years EEEND Endurance TJ = -40 to 150 ℃ 1000 Cycles TJ = -40 to 85 ℃ 20000 Cycles PROTECTION CIRCUITS VUVLO Supply undervoltage lockout (UVLO) VM rising 4.3 4.4 4.5 V VM falling 4.1 4.2 4.3 V VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 110 200 350 mV tUVLO Supply undervoltage deglitch time 3 5 7 µs VOVP Supply overvoltage protection (OVP) Supply rising, OVP_EN = 1, OVP_SEL = 0 32.5 34 35 V Supply falling, OVP_EN = 1, OVP_SEL = 0 31.8 33 34.3 V Supply rising, OVP_EN = 1, OVP_SEL = 1 20 22 23 V Supply falling, OVP_EN = 1, OVP_SEL = 1 19 21 22 V VOVP_HYS Supply overvoltage protection (OVP) Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V Rising to falling threshold, OVP_SEL = 0 0.7 0.8 0.9 V tOVP Supply overvoltage deglitch time 2.5 5 7 µs VCPUV Charge pump undervoltage lockout (above VM) Supply rising 2.25 2.5 2.75 V Supply falling 2.2 2.4 2.6 V VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 65 100 150 mV VAVDD_UV Analog regulator undervoltage lockout Supply rising 2.7 2.85 3 V Supply falling 2.5 2.65 2.8 V VAVDD_ UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 180 200 240 mV IOCP Overcurrent protection trip point OCP_LVL = 0b 9.5 16 22 A OCP_LVL = 1b 15 24 28 A MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tOCP Overcurrent protection deglitch time OCP_DEG = 00b 0.02 0.2 0.4 µs OCP_DEG = 01b 0.2 0.6 1.2 µs OCP_DEG = 10b 0.5 1.2 1.8 µs OCP_DEG = 11b 0.9 1.6 2.5 µs tRETRY Overcurrent protection retry time 425 500 575 ms TOTW Thermal warning temperature Die temperature (TJ) 135 145 155 °C TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 15 20 25 °C TTSD_BUCK Thermal shutdown temperature (Buck) Die temperature (TJ) 170 180 190 °C TTSD_BUCK_ HYS Thermal shutdown hysteresis (Buck) Die temperature (TJ) 15 20 25 °C TTSD_FET Thermal shutdown temperature (FET) Die temperature (TJ) 165 175 185 °C TTSD_FET_HY S Thermal shutdown hysteresis (FET) Die temperature (TJ) 20 25 30 °C (1) RLBK is the resistance of inductor LBK (2) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines. (3) The maximum tf for the SDA and SCL bus lines (300ns) is longer than the specified maximum tof for the output stages (250ns). This allows series protection resistors (Rs) to connect the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. (4) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns

5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Standard-mode fSCL SCL clock frequency 0 100 kHz tHD_STA Hold time (repeated) START condition After this period, the first clock pulse is generated 4 µs tLOW LOW period of the SCL clock 4.7 µs tHIGH HIGH period of the SCL clock 4 µs tSU_STA Set-up time for a repeated START condition 4.7 µs tHD_DAT Data hold time (2) I2C bus devices 0 (3) (4) µs tSU_DAT Data set-up time 250 ns tr Rise time for both SDA and SCL signals 1000 ns tf Fall time of both SDA and SCL signals (3) (6) (7) (8) 300 ns tSU_STO Set-up time for STOP condition 4 µs tBUF Bus free time between STOP and START condition 4.7 µs Cb Capacitive load for each bus line (9) 400 pF tVD_DAT Data valid time (10) 3.45 (4) µs tVD_ACK Data valid acknowledge time (11) 3.45 (4) µs VnL Noise margin at the LOW level For each connected device (including hysteresis) 0.1*AVD D V Vnh Noise margin at the HIGHlevel For each connected device (including hysteresis) 0.2*AVD D V Fast-mode fSCL SCL clock frequency 0 400 KHz tHD_STA Hold time (repeated) START condition After this period, the first clock pulse is generated 0.6 µs www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: MCF8316D

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU_STA Set-up time for a repeated START condition 0.6 µs tHD_DAT Data hold time (2) 0 (3) (4) µs tSU_DAT Data set-up time 100 (5) ns tr Rise time for both SDA and SCL signals 20 300 ns tf Fall time of both SDA and SCL signals (3) (6) (7) (8) 20 x (AVDD/ 5.5V) 300 ns tSU_STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between STOP and START condition 1.3 µs Cb Capacitive load for each bus line (9) 400 pF tVD_DAT Data valid time (10) 0.9 (4) µs tVD_ACK Data valid acknowledge time (11) 0.9 (4) µs VnL Noise margin at the LOW level For each connected device (including hysteresis) 0.1*AVD D V Vnh Noise margin at the HIGHlevel For each connected device (including hysteresis) 0.2*AVD D V (1) All values referred to VIH(min) and VIL(max) levels (2) tHD_DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum tHD_DAT could be 3.45 us and 0.9 µs for Standard-mode and Fast-mode, but must be less than the maximum of tVD_DAT or tVD_ACK by a transistion time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock. (5) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU_DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period if the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU_DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. (6) If mixed with HS-mode devices, faster fall times according to Table 10 are allowed. (7) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. (8) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. (9) The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the application. (10) tVD_DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). (11) tVD_ACK = time for acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, dependging on which one is worse). MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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5.7 Typical Characteristics

S u p p l y V o l t a g e ( V ) Active Current (mA) 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 B u c k w i t h I n d u c t o r ( 2 5  C ) B u c k w i t h I n d u c t o r ( 1 2 5  C ) B u c k w i t h R e s i s t o r ( 2 5  C ) B u c k w i t h R e s i s t o r ( 1 2 5  C ) Figure 5-1. Supply current over supply voltage S u p p l y V o l t a g e ( V ) Buck Efficiency (%) 4 8 1 2 1 6 2 0 2 4 2 8 3 2 3 6 7 5 7 7 . 5 8 0 8 2 . 5 8 5 8 7 . 5 9 0 9 2 . 5 9 5 9 7 . 5 1 0 0 T J = - 4 0  C T J = 2 5  C T J = - 1 5 0  C Figure 5-2. Buck regulator efficiency over supply voltage B u c k O u t p u t L o a d C u r r e n t ( A ) Buck Output Voltage (V) 3 . 2 5 3 . 5 3 . 7 5 4 . 2 5 4 . 5 4 . 7 5 5 . 2 5 5 . 5 5 . 7 5 B U C K _ S E L = 0 0 b B U C K _ S E L = 0 1 b B U C K _ S E L = 1 0 b B U C K _ S E L = 1 1 b Figure 5-3. Buck regulator output voltage over load current www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: MCF8316D

6 Detailed Description

6.1 Overview

The MCF8316D provides a single-chip, code-free sensorless FOC solution for customers driving speed- controlled 12 to 24V brushless-DC motors requiring up to 8A peak phase currents. The MCF8316D integrates three ½-bridges with 40V absolute maximum capability and a very low R DS(ON) of 95mΩ (high-side + low-side) to enable high power drive capability. Current is sensed using an integrated current sensing circuit which eliminates the need for external sense resistors. Power management features of an adjustable buck regulator and LDO generate the necessary voltage rails for the device and can also be used to power external circuits. MCF8316D implements sensorless FOC, and so an external microcontroller is not required to spin the brushless-DC motor. The algorithm is implemented in a fixed-function state machine, so no coding is needed. The algorithm is highly configurable through register settings ranging from motor start-up behavior to closed loop operation. Register settings can be stored in non-volatile EEPROM, which allows the device to operate stand-alone once it has been configured. The device receives a speed command through a PWM input, analog voltage, frequency input, or I2C command. In-built protection features include power-supply under voltage lockout (UVLO), charge-pump under voltage lockout (CPUV), over current protection (OCP), AVDD under voltage lockout (AVDD_UV), buck regulator UVLO, motor lock detection and over temperature warning and shutdown (OTW and TSD). Fault events are indicated by the nFAULT pin with detailed fault information available in the registers. The MCF8316D device is available in a 0.5mm pin pitch, VQFN surface-mount package. The VQFN package size is 7mm x 5mm with a height of 1mm. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.2 Functional Block Diagram

1µF CFLY 47nF Charge Pump Integrated current sensing VM CVM1 0.1µF CVM2 >10µF Buck/LDO Regulator GND_BK FB_BK SW_BK LBK CBK - or - RBK DVDD DGND CDVDD 1µF AVDD LDO Regulator Input: VM or Buck AVDD CAVDD 1µF AGND Buck Out AVDD Out DVDD LDO Regulator Speed profiles Speed loop Motor Parameter Extraction ISENA ISENB ISENC Protection Protection Protection Protection Protection Protection BRAKE DIR SPEED/WAKE FG nFAULT SCL SDA 2 EXT_WD EXT_CLK DACOUT1 PWM, Freq. or Analog Input I2C Built-in 60-MHz Oscillator 12-bit ADC 12-bit DAC Variable monitoring on DACOUTpin Op onal external crystal oscillator or clock reference AVDD AVDD VM OUTA OUTB OUTC ALARM IO Interface A q B C d S N AVDD AVDD DACOUT2 DACOUT2/SOX PGND VM Figure 6-1. MCF8316D Functional Block Diagram www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: MCF8316D

6.3 Feature Description

6.3.1 Output Stage

The MCF8316D consists of integrated 95mΩ (combined high-side and low-side FETs' on-state resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side NMOS FETs across a wide operating voltage range in addition to providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side MOSFETs.

6.3.2 Device Interface

The MCF8316D supports I 2C interface to provide end application design with adequate flexibility. MCF8316D allows controlling the motor operation and system through BRAKE, DRVOFF, DIR, EXT_CLK, EXT_WD and SPEED/WAKE pins. MCF8316D also provides different signals for monitoring system variables, speed, fault and phase current feedback through DACOUT1, DACOUT2, FG, nFAULT and SOX pins.

6.3.2.1 Interface - Control and Monitoring

• SPEED/WAKE pin is used to control the motor speed and to wake up MCF8316D from sleep. SPEED pin can be configured to accept PWM, frequency or analog input signals. It is also used to enter and exit from sleep and standby mode (see Table 6-8).
• When BRAKE pin is driven 'High', MCF8316D enters brake state. Brake state can be configured to either low side brake (see Low-Side Braking) or align brake (see Section 6.3.22) through BRAKE_PIN_MODE. MCF8316D decreases output speed to value defined by BRAKE_SPEED_THRESHOLD before entering brake state. As long as BRAKE is driven 'High', MCF8316D stays in brake state. Brake pin input can be overwritten by configuring BRAKE_INPUT over the I2C interface.
• The DIR pin decides the direction of motor spin; when driven 'High', the sequence is OUT A → OUT B → OUT C, and when driven 'Low', the sequence is OUT A → OUT C → OUT B. DIR pin input can be overwritten by configuring DIR_INPUT over the I2C interface.
• When DRVOFF pin is driven 'High', MCF8316D stops driving the motor by turning OFF (Hi-Z) all MOSFETs (coast state) - this could be accompanied by faults like no motor or abnormal BEMF. When DRVOFF is driven 'Low', MCF8316D returns to normal state of operation, as if it was restarting the motor (see DRVOFF Functionality). DRVOFF does not cause the device to go to sleep or standby mode; the digital core is still active. Entry and exit from sleep or standby condition is controlled by SPEED pin. External Oscillator and Watchdog Signals
• EXT_CLK pin can be used to provide an external clock reference (see External Clock Source).
• EXT_WD pin can be used to provide an external watchdog signal (see External Watchdog). Output Signals
• DACOUT1 outputs internal variable defined by address in register DACOUT1_VAR_ADDR. DACOUT1 is refreshed every 100µs (see DAC outputs).
• DACOUT2 outputs internal variable defined by address in register DACOUT2_VAR_ADDR. DACOUT2 is refreshed every 100µs (see DAC outputs).
• FG pin provides pulses which are proportional to motor speed (see FG Configuration).
• nFAULT (active low) pin provides fault status in device or motor operation.
• ALARM pin, when enabled using ALARM_PIN_EN, provides fault status in device or motor operation as an active high signal. When ALARM pin is enabled, report only faults are reported only on ALARM pin (as logic high) and not reported on nFAULT pin (as logic low). When ALARM pin is enabled, actionable faults are reported on ALARM pin (as logic high) as well as on nFAULT pin (as logic low). When ALARM pin is disabled, it is in Hi-Z state and all faults (actionable and report only) are reported on nFAULT as logic low. ALARM pin should be left floating when unused/disabled.
• SOX pin provides the output of one of the current sense amplifiers. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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1. Internal pull-up resistor (to AVDD) for both FG and nFAULT pins can be enabled by configuring PULLUP_ENABLE to 1b. Any change to this bit needs to be written to EEPROM followed by a power recycle to take effect. When PULLUP_ENABLE is set to 1b, no external pull-up resistor should be provided. 2. DIR and BRAKE pins each have an internal pull-down resistor of 100kΩ. When these pins are used, an additional pull-down resistor of 10kΩ may be added externally for additional noise immunity. 3. SPEED pin has an internal pull-down resistor of 1MΩ. In analog speed input mode, a suitable R-C filter can be added externally for reducing noise. In PWM speed input mode, SPEED_PIN_GLITCH_FILTER can be appropriately configured for glitch rejection.

6.3.2.2 I2C Interface

The MCF8316D supports an I 2C serial communication interface that allows an external controller to send and receive data. This I 2C interface lets the external controller to configure the EEPROM and read detailed fault and motor state information. The pull-down strength of the I 2C pins can be configured using SLEW_RATE_I2C_PINS. The I2C bus is a two-wire interface using the SCL and SDA pins which are described as follows :

• The SCL pin is the clock signal input.
• The SDA pin is the data input and output.

6.3.3 Step-Down Mixed-Mode Buck Regulator

The MCF8316D has an integrated mixed-mode buck regulator to supply regulated 3.3V or 5V power for an external controller or system voltage rail. Additionally, the buck output can also be configured to 4V or 5.7V for supporting the extra headroom for an external LDO for generating a 3.3V or 5V supplies. The output voltage of the buck is set by BUCK_SEL. The buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device improves performance during line and load transients by implementing a pulse-frequency current-mode control scheme which requires less output capacitance and simplifies frequency compensation design. Table 6-1. Recommended settings for Buck Regulator Buck Mode Buck output voltage AVDD power sequencing Max output current from AVDD (IAVDD_MAX) Max output current from Buck (IBK_MAX) Buck current limit Inductor - 47μH 3.3V or 4V Not supported (BUCK_PS_DIS = 1b) 20mA 170mA 600mA (BUCK_CL = 0b) Inductor - 47μH 5V or 5.7V Supported (BUCK_PS_DIS = 0b) 20mA 170mA - IAVDD 600mA (BUCK_CL = 0b) Inductor - 22μH 3.3V or 4V Not supported (BUCK_PS_DIS = 1b) 20mA 20mA 150mA (BUCK_CL = 1b) Inductor - 22μH 5V or 5.7V Supported (BUCK_PS_DIS = 0b) 20mA 20mA - IAVDD 150mA (BUCK_CL = 1b) Resistor - 22Ω 3.3V or 4V Not supported (BUCK_PS_DIS = 1b) 20mA 10mA 150mA (BUCK_CL = 1b) Resistor - 22Ω 5V or 5.7V Supported (BUCK_PS_DIS = 0b) 20mA 10mA - IAVDD 150mA (BUCK_CL = 1b)

6.3.3.1 Buck in Inductor Mode

The buck regulator in MCF8316D is primarily designed to support low inductance of 47-µH and 22-µH. A 47-µH inductor allows the buck regulator to operate up to 170-mA load current support, whereas applications requiring current up to 20-mA can use a 22-µH inductor which saves component size. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: MCF8316D

Figure 6-2 shows the connection of buck regulator in inductor mode. LBK SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK Figure 6-2. Buck (Inductor Mode)

6.3.3.2 Buck in Resistor mode

If the external load requirement is less than 10-mA, the inductor can be replaced with a resistor. In resistor mode the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode. Figure 6-3 shows the connection of buck in resistor mode. RBK SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK Figure 6-3. Buck (Resistor Mode)

6.3.3.3 Buck Regulator with External LDO

The buck regulator also supports the voltage requirement to supply an external LDO to generate standard 3.3-V or 5-V output rail with higher accuracies. The buck output voltage should be configured to 4-V or 5.7-V to provide extra headroom to support the external LDO for generating 3.3-V or 5-V rail as shown in Figure 6-4. This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out voltage. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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SW_BK GND_BK VM Control CBK VBK (4V / 5.7V) VM FB_BK 3.3V / 5V LDO VIN GND VLDO CLDO GND Ext. Load VLDO (3.3V / 5V) External LDO Figure 6-4. Buck Regulator with External LDO

6.3.3.4 AVDD Power Sequencing from Buck Regulator

The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce the device power dissipation. The power sequencing mode allows on-the-fly changeover of AVDD LDO input from DC mains (VM) to buck output (V BK) as shown in Figure 6-5. This sequencing can be configured through the BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5-V or 5.7-V. AVDD AGND CAVDD External Load VM REF LBK SW_BK GND_BK VM Control CBK Ext. Load VBK VM FB_BK VBK BUCK_PS_DIS AVDD LDO Figure 6-5. AVDD Power Sequencing from Mixed Mode Buck Regulator www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: MCF8316D

6.3.3.5 Mixed Mode Buck Operation and Control

The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control. The output voltage of the buck regulator is compared with the internal reference voltage (V BK_REF) which is internally generated depending on the buck output voltage setting (BUCK_SEL) which constitutes an outer voltage control loop. Depending on the comparator output going high (V BK < V BK_REF) or low (V BK > V BK_REF), the high-side power FET of the buck turns on and off respectively. An independent current control loop monitors the current in high-side power FET (I BK) and turns off the high-side FET when the current becomes higher than the buck current limit (I BK_CL set by BUCK_CL) - this implements a current limit control for the buck regulator. Figure 6-6 shows the architecture of the buck and various control/protection loops. VM IBK_CL LBK SW_BK GND_BK CBK Ext. Load VBK VM FB_BK BUCK_SEL IBK IBK_OCP Buck Reference Voltage Generator VBK VBK_REF IBK IBK Current Limit OC Protection Voltage Control PWM Control and Driver _ VBK_UVLO + VBK UV Protection Buck Control Figure 6-6. Buck Operation and Control Loops

6.3.4 AVDD Linear Voltage Regulator

A 3.3-V linear regulator is integrated into MCF8316D and is available for use by external circuitry. This AVDD LDO regulator is used for powering up the internal circuitry of the device and additionally, this regulator can also provide the supply voltage for a low-power MCU or other external circuitry supporting up to 20-mA. The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin. The AVDD nominal, no-load output voltage is 3.3-V. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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BUCK_PS_DIS FB_BK Figure 6-7. AVDD Linear Regulator Block Diagram Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply (BUCK_PS_DIS = 1b) (1) For example, at a VVM of 24-V, drawing 20-mA out of AVDD results in a power dissipation as shown in Equation P 24 V 3.3 V 20 mA 414 mW u (2) Use Equation 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as supply (BUCK_PS_DIS = 0b) P = V F B _ BK − V A VD D × I A VD D (3)

6.3.5 Charge Pump

Since the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power supply to turn-on the high-side FETs. The MCF8316D integrates a charge-pump circuit that generates a voltage above the VM supply for this purpose. The charge pump requires two external capacitors (C CP, CFLY) for operation. See Figure 6-8 and Table 4-1 for details on these capacitors (value, connection, and so forth). www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: MCF8316D

Figure 6-8. Charge Pump

6.3.6 Slew Rate Control

An adjustable gate-drive current control is provided for the output stage MOSFETs to achieve configurable slew rate for EMI mitigation. The MOSFET VDS slew rate is a critical factor for optimizing conducted and radiated emissions, total energy and duration of diode recovery spikes and switching voltage transients related to parasitic elements of the PCB. This slew rate is predominantly determined by the control of the internal MOSFET gate current as shown in Figure 6-9. VM OUTx VCP (Internal) Slew Rate Control Slew Rate Control VCP (Internal) GND Figure 6-9. Slew Rate Circuit Implementation The slew rate of each half-bridge can be adjusted through SLEW_RATE. Slew rate can be configured as either 125-V/µs or 200-V/µs. The slew rate is calculated by the rise-time and fall-time of the voltage on OUTx pin as shown in Figure 6-10. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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20% 80% 20% 80% tfall VM trise VM VOUTx Time Figure 6-10. Slew Rate Timings

6.3.7 Cross Conduction (Dead Time)

The device is fully protected against any cross conduction of MOSFETs - during the switching of high-side and low-side MOSFETs, MCF8316D avoids shoot-through events by inserting a dead time (t dead). This is implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring that VGS of high-side MOSFET has dropped below turn-off level before switching on the low-side MOSFET of same half-bridge (or vice-versa) as shown in Figure 6-11and Figure 6-12. The VGS of the high-side and low-side MOSFETs (VGS_HS and VGS_LS) shown in Figure 6-12 are internal signals. VM OUTx GND HS Gate Control LS Gate Control VGS_LS VGS_HS Figure 6-11. Cross Conduction Protection www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: MCF8316D

VGS_HS VGS_LS tDEAD Time 10% 10% Figure 6-12. Dead Time MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.3.8 Motor Control Input Sources

The MCF8316D provides four ways of controlling the motor : 1. SPEED Control: In speed control mode, the speed of the motor is controlled using a closed loop PI control according to the input reference. 2. POWER Control: In power control mode, the DC input power of the inverter power stage is controlled using a closed loop PI control according to the input reference. 3. CURRENT Control: In current control mode, the torque generating current (iq) is controlled using a closed loop PI control according to the input reference. 4. VOLTAGE Control: In voltage control mode, the voltage applied to the motor is controlled according to the input reference. The MCF8316D provides four sources of the reference input for motor control as listed below. The reference input source is configured by SPEED_MODE.

• PWM input on SPEED/WAKE pin by varying duty cycle of input signal
• Frequency input on SPEED/WAKE pin by varying frequency of input signal
• Analog input on SPEED/WAKE pin by varying amplitude of input signal
• Over I2C by configuring DIGITAL_SPEED_CTRL register Freq based Duty PWM Duty DUTY_CMD Linear / Stair case / Bi-Dir Profiles SPEED_REF ADC POWER_REF VOLTAGE_REF CURRENT_REF Slew rate limit (Hz/s, W/s, A/s, V/s) PWM Analog I2C SPEED Pin Freq REF_PROFILE_ CONFIG 00b REF_PROFILE_ CONFIG = 00b Figure 6-13. Multiplexing the Reference Input Command The signal path from REF (SPEED/WAKE) pin input (or I 2C based speed input) to output reference (SPEED_REF or POWER_REF or CURRENT_REF or VOLTAGE_REF) shown in Figure 6-13.

6.3.8.1 Analog-Mode Motor Control

Analog input based motor control can be configured by setting SPEED_MODE to 00b. In this mode, the duty command (DUTY_CMD) varies with the analog voltage input on the SPEED pin (V SPEED). When 0 ≤ VSPEED ≤ VEN_SB, DUTY_CMD is set to zero. When V EX_SB ≤ VSPEED ≤ VANA_FS, DUTY_CMD varies linearly with V SPEED as shown in Figure 6-14. VEX_SB and VEN_SB are the standby entry and exit thresholds - refer Section 6.4.1.2 for more information on VEX_SB and VEN_SB. When VSPEED > VANA_FS, DUTY_CMD is clamped to 100%. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: MCF8316D

DUTY_CMD SPEED pin voltageVANA_FS0 100% VEN_SB VEX_SB Figure 6-14. Analog-Mode Motor Control

6.3.8.2 PWM-Mode Motor Control

PWM based motor control can be configured by setting SPEED_MODE to 01b. In this mode, the PWM duty cycle applied to the SPEED pin can be varied from 0 to 100% and duty command (DUTY_CMD) varies linearly with the applied PWM duty cycle. When 0 ≤ DutySPEED ≤ DutyEN_SB, DUTY_CMD is set to zero. When DutyEX_SB ≤ Duty SPEED ≤ 100%, DUTY_CMD varies linearly with Duty SPEED as shown in Figure 6-15 . Duty EX_SB and DutyEN_SB are the standby entry and exit thresholds - refer Section 6.4.1.2 for more information on Duty EX_SB and DutyEN_SB. The frequency of the PWM input signal applied to the SPEED pin is defined as f PWM and the range for this frequency can be configured through SPEED_RANGE_SEL. Note 1. fPWM is the frequency of the PWM signal the device can accept at SPEED pin to control motor speed. It does not correspond to the PWM output frequency that is applied to the motor phases. The PWM output frequency can be configured through PWM_FREQ_OUT (see Section 6.3.17 ). 2. SLEEP_ENTRY_TIME should be set longer than the off time in PWM signal (VSPEED < VIL) at lowest duty input. For example, if fPWM is 10 kHz and lowest duty input is 2%, SLEEP_ENTRY_TIME should be more than 98 µs to ensure there is no unintended sleep/standby entry. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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DUTY_CMD PWM Duty at SPEED pin100%0 100% DutyEN_SB DutyEX_SB Figure 6-15. PWM-Mode Motor Control

6.3.8.3 I2C-based Motor Control

I2C based serial interface can be used for motor control by setting SPEED_MODE to 10b. In this mode, the control command can be written directly into DIGITAL_SPEED_CTRL register . The SPEED pin can be used to control the sleep entry and exit - if SPEED pin input is set to a value lower than V EN_SL after DIGITAL_SPEED_CTRL register has been set to 0b for a time longer than SLEEP_ENTRY_TIME, MCF8316D enters sleep state. When SPEED pin > V EX_SL, MCF8316D exits sleep state and motor is controlled through DIGITAL_SPEED_CTRL register . If 0 ≤ DIGITAL_SPEED_CTRL register ≤ DIGITAL_SPEED_CTRLEN_SB and SPEED pin > V EX_SL, MCF8316D is in standby state. The relationship between DUTY_CMD and DIGITAL_SPEED_CTRL register is shown in Figure 6-16 . Refer Section 6.4.1.2 for more information on DIGITAL_SPEED_CTRLEN_SB EX_SB and DIGITAL_SPEED_CTRLEN_SB EN_SB. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: MCF8316D

DUTY_CMD DIGITAL_SPEED_CTRL327670 100% DIGITAL_SPEED _CTRLEN_SB DIGITAL_SPEED_ CTRLEX_SB Figure 6-16. I2C Mode Speed Control

6.3.8.4 Frequency-Mode Motor Control

Frequency based motor control is configured by setting SPEED_MODE to 11b. In this mode, duty command varies linearly as a function of the frequency of the square wave input at SPEED/WAKE pin. When 0 ≤ FreqSPEED ≤ FreqEN_SB, DUTY_CMD is set to zero. When Freq EX_SB ≤ FreqSPEED ≤ INPUT_MAXIMUM_FREQ, DUTY_CMD varies linearly with Freq SPEED as shown in Figure 6-17. FreqEX_SB and Freq EN_SB are the standby entry and exit thresholds - refer Section 6.4.1.2 for more information on Freq EX_SB and Freq EN_SB. Input frequency greater than INPUT_MAXIMUM_FREQ clamps the DUTY_CMD to 100%. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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DUTY_CMD Frequency at SPEED pinINPUT_MAXIMUM_FREQ0 100% FreqEN_SB FreqEX_SB Figure 6-17. Frequency Mode Speed Control

6.3.8.5 Input Reference Profiles

MCF8316D supports three different kinds of input reference profiles (linear, step, forward-reverse) to enable a variety of end-user applications. The different profiles can be configured through REF_PROFILE_CONFIG and the input reference can be a speed, power, current or voltage command as configured by INPUT_REFERENCE_MODE. In speed reference mode, the profiler output REF_X corresponds to percentage of MAX_SPEED as shown in Equation 4. In power reference mode, the profiler output REF_X corresponds to percentage of MAX_POWER as shown in Equation 5. In current reference mode, the profiler output REF_X corresponds to percentage of ILIMIT as shown in Equation 6. In voltage reference mode, REF_X corresponds to the modulation index applied to the motor. SPEED_REF (Hz) = (REF_X/255) x MAX_SPEED (Hz) (4) POWER_REF (W) = (REF_X/255) x MAX_POWER (W) (5) CURRENT_REF (A) = (REF_X/255) x ILIMIT (A) (6) When REF_PROFILE_CONFIG is set to 00b, the input reference is set by the duty command (DUTY_CMD) as

6.3.8.5.1 Linear Control Profiles

For all three profiles (linear, step, forward/reverse),

• When MCF8316D is configured as a sleep device, a zero input reference (0V in analog mode, 0% duty in PWM mode, DIGITAL_SPEED_CTRL = 0b in I2C mode or 0Hz in frequency mode) will stop the motor.
• When MCF8316D is configured as a standby device, a zero input reference will result in motor operating at reference level (speed, power, current or voltage) set by REF_OFF1. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: MCF8316D

DUTY_ON1 DUTY_CMD REF REF_CLAMP1 DUTY_OFF1 DUTY_CLAMP1 DUTY_OFF2DUTY_ON2DUTY_A DUTY_CLAMP2DUTY_B DUTY_C DUTY_D DUTY_E REF_CLAMP2 REF_OFF1 REF_OFF2 REF_A REF_B REF_C REF_D REF_E Figure 6-18. Linear Control Profiles Linear control profiles can be configured by setting REF_PROFILE_CONFIG to 01b. Linear profiles feature input control references which change linearly between REF_CLAMP1 and REF_CLAMP2 with different slopes which can be set by configuring DUTY_x and REF_x combination.

• DUTY_OFF1 configures the duty command below which the reference will be REF_OFF1.
• DUTY_OFF1 and DUTY_ON1configures a hysteresis around reference control input REF_CLAMP1 and REF_OFF1 as shown in Figure 6-18.
• DUTY_CLAMP1 configures the duty command till which reference will be constant with a value REF_CLAMP1. DUTY_CLAMP1 can be placed anywhere between DUTY_OFF1 and DUTY_A.
• DUTY_A configures the duty command for reference REF_A. The reference changes from REF_CLAMP1 to REF_A linearly between DUTY_CLAMP1 and DUTY_A. DUTY_A to DUTY_E has to be in the same order as shown in Figure 6-18.
• DUTY_B configures the duty command for reference REF_B. The reference changes linearly between DUTY_A and DUTY_B.
• DUTY_C configures the duty command for reference REF_C. The reference changes linearly between DUTY_B and DUTY_C.
• DUTY_D configures the duty command for reference REF_D. The reference changes linearly between DUTY_C and DUTY_D.
• DUTY_E configures the duty command for reference REF_E. The reference changes linearly between DUTY_D and DUTY_E.
• DUTY_CLAMP2 configures the duty command above which the reference will be constant at REF_CLAMP2. REF_CLAMP2 configures this constant reference between DUTY_CLAMP2 and DUTY_OFF2 . The reference changes linearly between DUTY_E and DUTY_CLAMP2. DUTY_CLAMP2 can be placed anywhere between DUTY_E and DUTY_OFF2. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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• DUTY_OFF2 and DUTY_ON2 configures a hysteresis around reference control input REF_CLAMP2 and REF_OFF2 as shown in Figure 6-18.
• DUTY_OFF2 configures the duty command above which the reference will change from REF_CLAMP2 to REF_OFF2.

6.3.8.5.2 Staircase Control Profiles

DUTY_ON1 DUTY_CMD REF REF_CLAMP1 DUTY_OFF1 DUTY_CLAMP1 DUTY_OFF2DUTY_ON2DUTY_A DUTY_CLAMP2DUTY_B DUTY_C DUTY_D DUTY_E REF_CLAMP2 REF_OFF1 REF_OFF2 REF_A REF_B REF_C REF_D REF_E DUTY_HYS Figure 6-19. Staircase Control Profiles Staircase control profiles can be configured by setting REF_PROFILE_CONFIG to 10b. Staircase profiles feature input control reference changes in steps between REF_CLAMP1 and REF_CLAMP2, by configuring DUTY_x and REF_x.

• DUTY_OFF1 configures the duty command below which the reference will be REF_OFF1.
• DUTY_OFF1 and DUTY_ON1configures a hysteresis around reference control input REF_CLAMP1 and REF_OFF1 as shown in Figure 6-19.
• DUTY_CLAMP1 configures the duty command till which reference will be constant. REF_CLAMP1 configures this constant reference between DUTY_OFF1 and DUTY_CLAMP1. DUTY_CLAMP1 can be placed anywhere between DUTY_OFF1 and DUTY_A.
• DUTY_A configures the duty command for reference REF_A. There is a step change in reference from REF_CLAMP1 to REF_A at DUTY_CLAMP1. DUTY_A to DUTY_E has to be in the same order as shown in Figure 6-19.
• DUTY_B configures the duty command for reference REF_B. There is a step change in reference from REF_A to REF_B at DUTY_A.
• DUTY_C configures the duty command for reference REF_C. There is a step change in reference from REF_B to REF_C at DUTY_B.
• DUTY_D configures the duty command for reference REF_D. There is a step change in reference from REF_C to REF_D at DUTY_C. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: MCF8316D

• DUTY_E configures the duty command for reference REF_E. There is a step change in reference from REF_D to REF_E at DUTY_D.
• DUTY_CLAMP2 configures the duty command above which the reference will be constant at REF_CLAMP2. REF_CLAMP2 configures this constant reference between DUTY_CLAMP2 and DUTY_OFF2. There is a step change in reference from REF_E to REF_CLAMP2 at DUTY_E. DUTY_CLAMP2 can be placed anywhere between DUTY_E and DUTY_OFF2.
• DUTY_OFF2 and DUTY_ON2 configures a hysteresis around reference control input REF_CLAMP2 and REF_OFF2 as shown in Figure 6-19.
• DUTY_OFF2 configures the duty command above which the reference will change from REF_CLAMP2 to REF_OFF2.
• DUTY_HYS configures the hysteresis during every step change at DUTY_CLAMP1, DUTY_A to DUTY_E.

6.3.8.5.3 Forward-Reverse Profiles

DUTY_ON1 DUTY_CMD REF REF_CLAMP1 DUTY_OFF1 DUTY_CLAMP1 DUTY_OFF2DUTY_ON2DUTY_A DUTY_CLAMP2DUTY_B DUTY_C DUTY_D DUTY_E REF_CLAMP2 REF_OFF1 REF_OFF2 REF_A REF_D Forward Direction OUT A OUT B OUT C Reverse Direction OUT A OUT C OUT B DUTY_HYS Figure 6-20. Forward Reverse Control Profiles Forward-Reverse control profiles can be configured by setting REF_PROFILE_CONFIG to 11b. Forward- Reverse profiles feature direction change through adjusting the duty command. DUTY_C configures duty command at which the direction will be changed. The Forward-Reverse speed profile can be used to eliminate the separate signal used to control the motor direction. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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The direction change functionality through DIR pin and DIR_INPUT bits are disabled in forward reverse profile mode.

• DUTY_OFF1 configures the duty command below which the reference will be REF_OFF1.
• DUTY_OFF1 and DUTY_ON1configures a hysteresis around reference control input REF_CLAMP1 and REF_OFF1 as shown in Figure 6-20.
• DUTY_CLAMP1 configures the duty command till which reference will be constant. REF_CLAMP1 configures this constant reference between DUTY_OFF1 and DUTY_CLAMP1. DUTY_CLAMP1 can be placed anywhere between DUTY_OFF1 and DUTY_A.
• DUTY_A configures the duty command for reference REF_A. The reference changes linearly between DUTY_CLAMP1 and DUTY_A. DUTY_A to DUTY_E has to be in the same order as shown in Figure 6-20.
• DUTY_B configures the duty command above which MCF8316D will be in off state. The reference remains constant at REF_A between DUTY_A and DUTY_B.
• DUTY_C configures the duty command at which the direction is changed
• DUTY_D configures the duty command above which the MCF8316D will be in running state in the reverse direction. REF_D configures constant reference between DUTY_D and DUTY_E.
• DUTY_E configures the duty command above which reference changes linearly between DUTY_E and DUTY_CLAMP2.
• DUTY_CLAMP2 configures the duty command above which the reference will be constant at REF_CLAMP2. REF_CLAMP2 configures this constant reference between DUTY_CLAMP2 and DUTY_OFF2. DUTY_CLAMP2 can be placed anywhere between DUTY_E and DUTY_OFF2.
• DUTY_OFF2 and DUTY_ON2 configures a hysteresis around reference control input REF_CLAMP2 and REF_OFF2 as shown in Figure 6-20.
• DUTY_OFF2 configures the duty command above which the reference changes in the reverse direction from REF_CLAMP2 to REF_OFF2.
• DUTY_HYS configures the hysteresis during step change at DUTY_B and DUTY_D.

6.3.8.5.4 Multi-Reference Mode Operation

The multi-reference (mixed) mode operation is available only when REF_PROFILE_CONFIG is set 01b (linear profile) or 10b (staircase profile). MCF8316D provides the option of multi-reference mode operation when VOLTAGE_MODE_CONFIG is set to 01b or 10b. When VOLTAGE_MODE_CONFIG is set to 01b, MCF8316D operates in speed, current or power reference mode till DUTY_CMD reaches DUTY_C and then switches to voltage reference mode from DUTY_C till 100% duty command as shown in Figure 6-21. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: MCF8316D

DUTY_CMD REF DUTY_C 100% Speed, Current or Power Reference Voltage Reference DUTY_HYS MIN_DUTY (%) x MAX_REF Figure 6-21. Multi-Reference Mode Operation (when VOLTAGE_MODE_CONFIG = 01b) Conversely, MCF8316D operates in voltage reference mode till DUTY_C and then switches to speed, current or power reference from DUTY_C till 100% duty command when VOLTAGE_MODE_CONFIG is set to 10b as shown in Figure 6-22. DUTY_CMD REF DUTY_C 100% Speed, Current or Power Reference Voltage Reference DUTY_HYS MIN_DUTY (%) x MAX_REF Figure 6-22. Multi-Reference Mode Operation (when VOLTAGE_MODE_CONFIG = 10b)

6.3.8.5.5 Input Reference Transfer Function without Profiler

The input reference can be a speed, power, current or voltage command as configured by INPUT_REFERENCE_MODE. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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MAX_POWER). If MAX_POWER is set to 0-W, POWER_REF is clamped to zero (irrespective of DUTY_CMD) and motor is in stopped state. Voltage Reference Transfer Function VOLTAGE_REF/MOD_INDEX (%) DUTY_CMD (%) 100%0 100% MIN_DUTY MIN_DUTY (%) DUTY_HYS Figure 6-25. Voltage Reference Transfer Function In voltage reference mode, the phase voltage applied to motor is proportional to the DUTY_CMD (from MIN_DUTY to 100%) as shown in Figure 6-25 . For DUTY_CMD less than MIN_DUTY, the applied voltage to motor is clamped to zero. Current Input Transfer Function CURRENT_REF (A) DUTY_CMD (%) 100%0 ILIMIT MIN_DUTY MIN_DUTY (%) x ILIMIT DUTY_HYS Figure 6-26. Current Reference Transfer Function Figure 6-26 shows the relationship between DUTY_CMD and CURRENT_REF. ILIMIT sets the CURRENT_REF at DUTY_CMD of 100%. MIN_DUTY sets the minimum CURRENT_REF (MIN_DUTY x ILIMIT).

6.3.9 Starting the Motor Under Different Initial Conditions

The motor can be in one of three states when MCF8316D begins the start-up process. The motor may be stationary, spinning in the forward direction, or spinning in the reverse direction. The MCF8316D includes a number of features to allow for reliable motor start-up under all of these conditions. Figure 6-27 shows the motor start-up flow for each of the three initial motor states. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Coast (Hi-Z) Brake Reverse Drive IPD Brake Open Loop Figure 6-27. Starting the motor under different initial conditions Note "Forward" means "spinning in the same direction as the commanded direction", and "Reverse" means "spinning in the opposite direction as the commanded direction".

6.3.9.1 Case 1 – Motor is Stationary

If the motor is stationary, the commutation must be initialized to be in phase with the position of the motor. The MCF8316D provides various options to initialize the commutation logic to the motor position and reliably start the motor.

• The align and double align techniques force the motor into alignment by applying a voltage across particular motor phases to force the motor to rotate in alignment with this phase.
• Initial position detect (IPD) determines the position of the motor based on the deterministic inductance variation, which is often present in BLDC motors.
• The slow first cycle method starts the motor by applying a low frequency cycle to align the rotor position to the applied commutation by the end of one electrical rotation. MCF8316D also provides a configurable brake option to ensure the motor is stationary before initiating one of the above start-up methods. Device enters open loop acceleration after going through the configured start-up method.

6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction

If the motor is spinning forward (same direction as the commanded direction) with sufficient speed (BEMF), the MCF8316D resynchronizes with the spinning motor and continues commutation by going directly to closed loop operation. If the motor speed is too low for closed loop operation, MCF8316D enters open loop operation to accelerate the motor till it reaches sufficient speed to enter closed loop operation. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time for this initial condition. This resynchronization feature can be enabled or disabled through RESYNC_EN. If resynchronization is disabled, the MCF8316D can be configured to wait for the motor to coast to a stop and/or apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1, considering the motor is stationary. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: MCF8316D

6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction

If the motor is spinning in the reverse direction (the opposite direction as the commanded direction), the MCF8316D provides several methods to change the direction and drive the motor to the target speed reference in the commanded direction. The reverse drive method allows the motor to be driven so that it decelerates through zero speed. If reverse drive is not enabled, then the MCF8316D can be configured to wait for the motor to coast to a stop and/or apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1, considering the motor is stationary. Note Take care when using the reverse drive or brake feature to ensure that the current is limited to an acceptable level and that the supply voltage does not surge as a result of energy being returned to the power supply. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.3.10 Motor Start Sequence (MSS)

Figure 6-28 shows the motor-start sequence implemented in the MCF8316D device. Sleep/Standby (SPEED_REF = 0) ISD_EN RVS_DR_EN Motor Start-up Direc on of Spin Closed Loop ForwardReverse N Y Y N YMotor BEMF < STAT_DETECT_THR BRAKE_EN Closed Loop Decelera on RESYNC_EN Open loop YN Open Loop Decelera on Direc on Reversal : Zero Speed Crossover Brake_Rou ne SPEED_REF > 0 Y Power On Motor driven at SPEED_REF DIR_CHANGE_ MODE Y N NDirec on Change Command Speed > OPN_CL_HANDOFF_THR Speed > FW_DRV_RESYN_THR HIZ_EN Hi-Z Time > HIZ_TIME N Y 0b0b Figure 6-28. Motor Start Sequence www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: MCF8316D

BRK_TIME Brake Time > BRK_TIME Y N Y BRK_CONFIG Brake N Brake_Rou ne Brake_Rou ne_End BRK_CURR (Current < BRK_CURR_THR for BRAKE_CURRENT_PERSIST) || Time > BRK_TIME Figure 6-29. Brake Routine Power-On State This is the initial state of the Motor Start Sequence (MSS) when MCF8316D is powered on. In this state, MCF8316D configures the peripherals, initializes the algorithm parameters from EEPROM and prepares for driving the motor. Sleep/Standby In this state, SPEED_REF is set to zero and MCF8316D is either in sleep or standby mode depending on DEV_MODE and SPEED/WAKE pin voltage. SPEED_REF > 0 Judgement When SPEED_REF is set to greater than zero, MCF8316D exits the sleep/ standby state and proceeds to ISD_EN judgement. As long as SPEED_REF is set to zero, MCF8316D stays in sleep/standby state. Direction Change Command Judgement When a direction change command is received, MCF8316D proceeds to DIR_CHANGE_MODE judgement. DIR_CHANGE_MODE Judgement If DIR_CHANGE_MODE is set to 0b, MCF8316D initiates direction change by proceeding to ISD_EN judgement. Instead, if DIR_CHANGE_MODE is set to 1b, MCF8316D initiates direction change by proceeding to Speed > OPN_CL_HANDOFF_THR judgement. ISD_EN Judgement MCF8316D checks to see if the initial speed detect (ISD) function is enabled (ISD_EN = 1b). If ISD is enabled, MSS proceeds to the BEMF < STAT_DETECT_THR judgement. Instead, if ISD is disabled, the MSS proceeds directly to the BRAKE_EN judgement. BEMF < STAT_DETECT_THR ISD determines the initial condition (speed, angle, direction of spin) of the motor (see Section 6.3.10.1). If motor is deemed to be stationary (BEMF < STAT_DETECT_THR), the MSS proceeds to BRAKE_EN judgement. If the motor is not stationary, MSS proceeds to verify the direction of spin. Direction of spin Judgement The MSS determines whether the motor is spinning in the forward or the reverse direction. If the motor is spinning in the forward direction, the MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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MCF8316D proceeds to the RESYNC_EN judgement. If the motor is spinning in the reverse direction, the MSS proceeds to the RVS_DR_EN judgement. RESYNC_EN Judgement If RESYNC_EN is set to 1b, MCF8316D proceeds to Speed > Open to Closed Loop Handoff (Resync) judgement. If RESYNC_EN is set to 0b, MSS proceeds to HIZ_EN judgement. Speed > FW_DRV_RESYN_THR Judgement If motor speed > FW_DRV_RESYN_THR, MCF8316D uses the speed and position information from the ISD to transition to the closed loop state (see Section 6.3.10.2 ) directly. If motor speed < FW_DRV_RESYN_THR, MCF8316D transitions to open loop state. RVS_DR_EN Judgement The MSS checks to see if the reverse drive function is enabled (RVS_DR_EN = 1b). If it is enabled, the MSS transitions to check speed of the motor in reverse direction. If the reverse drive function is not enabled (RVS_DR_EN = 0b), the MSS advances to the HIZ_EN judgement. Speed > OPN_CL_HANDOFF_THR Judgement The MSS checks to see if the reverse speed is high enough for MCF8316D to decelerate in closed loop. Till the speed (in reverse direction) is above OL_CL_HANDOFF_THR, MSS stays in closed loop deceleration. If speed is below OPN_CL_HANDOFF_THR, then the MSS transitions to open loop deceleration. Reverse Closed Loop, Open Loop Deceleration and Zero Speed Crossover The MCF8316D resynchronizes in the reverse direction, decelerates the motor in closed loop till motor speed falls below the handoff threshold. (see Reverse Drive). When motor speed in reverse direction is too low, the MCF8316D switches to open-loop, decelerates the motor in open-loop, crosses zero speed, and accelerates in the forward direction in open-loop before entering closed loop operation after motor speed is sufficiently high. HIZ_EN Judgement The MSS checks to determine whether the coast (Hi-Z) function is enabled (HIZ_EN = 1b). If the coast function is enabled (HIZ_EN = 1b), the MSS advances to the coast routine. If the coast function is disabled (HIZ_EN = 0b), the MSS advances to the BRAKE_EN judgement. Coast (Hi-Z) Routine The device coasts the motor by turning OFF all six MOSFETs for a certain time configured by HIZ_TIME. BRAKE_EN Judgement The MSS checks to determine whether the brake function is enabled (BRAKE_EN = 1b). If the brake function is enabled (BRAKE_EN = 1b), the MSS advances to the brake routine. If the brake function is disabled (BRAKE_EN = 0b), the MSS advances to the motor start-up state (see Section 6.3.10.4). Brake Routine MCF8316D implements either a time based brake (duration configured by BRK_TIME) or a current based brake (brake applied till phase currents < BRK_CURR_THR for BRAKE_CURRENT_PERSIST) based on BRK_CONFIG. Current based brake has a timeout to ensure brake state ends in case phase currents do not drop below BRK_CURR_THR within BRK_TIME. Time based brake can be applied either using high-side or low-side MOSFETs based on BRK_MODE configuration. Current based brake is applied using low-side MOSFETs only. Closed Loop State In this state, the MCF8316D drives the motor with sensorless FOC based on rotor angle estimation.

6.3.10.1 Initial Speed Detect (ISD)

The ISD function is used to identify the initial condition of the motor and is enabled by setting ISD_EN to 1b. The initial speed, position and direction is determined by sensing the three phase voltages. ISD can be disabled by setting ISD_EN to 0b. If the function is disabled (ISD_EN set to 0b), the MCF8316D does not perform the initial speed detect function and proceeds to check if the brake routine (BRAKE_EN) is enabled. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: MCF8316D

6.3.10.2 Motor Resynchronization

The motor resynchronization function works when the ISD and resynchronization functions are both enabled and the device determines that the initial state of the motor is spinning in the forward direction (same direction as the commanded direction). The speed and position information measured during ISD are used to initialize the drive state of the MCF8316D , which can transition directly into closed loop (or open loop if motor speed is not sufficient for closed loop operation) state without needing to stop the motor. In the MCF8316D , motor resynchronization can be enabled/disabled through RESYNC_EN bit. If motor resynchronization is disabled, the device proceeds to check if the motor coast (Hi-Z) routine is enabled.

6.3.10.3 Reverse Drive

The MCF8316D uses the reverse drive function to change the direction of the motor rotation when ISD_EN and RVS_DR_EN are both set to 1b and the ISD determines the motor spin direction to be opposite to that of the commanded direction. Reverse drive includes synchronizing with the motor speed in the reverse direction, reverse decelerating the motor through zero speed, changing direction, and accelerating in open loop in forward (or commanded) direction until the device transitions into closed loop in forward direction (see Figure 6-30 ). MCF8316D provides the option of using the forward direction parameters or a separate set of reverse drive parameters by configuring REV_DRV_CONFIG. Reverse Deceleration Open Loop Handoff to close loop Open loop Close loop Speed Time Handoff to open loop Figure 6-30. Reverse Drive Function

6.3.10.3.1 Reverse Drive Tuning

MCF8316D provides the option of tuning the open to closed loop handoff threshold, open loop acceleration (and deceleration) rates and open loop current limit in reverse drive to values different to those used in forward drive operation; the reverse drive specific parameters can be used by setting REV_DRV_CONFIG to 1b. If REV_DRV_CONFIG is set to 0b, MCF8316D uses the equivalent parameters configured for forward drive operation during the reverse drive operation too. The speed at which motor would enter the open loop in reverse direction can be configured using REV_DRV_HANDOFF_THR. For a smooth transition without jerks or loss of synchronism, user can configure an appropriate current limit when the motor is spinning in open loop during speed reversal using REV_DRV_OPEN_LOOP_CURRENT. The open loop acceleration rates for the forward direction during speed reversal are defined using REV_DRV_OPEN_LOOP_ACCEL_A1 and REV_DRV_OPEN_LOOP_ACCEL_A2. The reverse drive open loop deceleration rate, when the motor is decelerating in the opposite direction MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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to zero speed, can be configured as a percentage of reverse drive open loop acceleration using REV_DRV_OPEN_LOOP_DEC.

6.3.10.4 Motor Start-up

There are different options available for motor start-up from a stationary position and these options can be configured by MTR_STARTUP. In align and double align mode, the motor is aligned to a known position by injecting a DC current. In IPD mode, the rotor position is estimated by applying 6 different high-frequency pulses. In slow first cycle mode, the motor is started by applying a low frequency cycle.

6.3.10.4.1 Align

Align is enabled by configuring MTR_STARTUP to 00b. The MCF8316D aligns the motor by injecting a DC current through a particular phase pattern for a certain time configured by ALIGN_TIME. The phase pattern during align is generated based on ALIGN_ANGLE. In the MCF8316D, the current limit during align is configured through ALIGN_OR_SLOW_CURRENT_ILIMIT. A fast change in the phase current may result in a sudden change in the driving torque and this could result in acoustic noise. To avoid this, the MCF8316D ramps up the current from 0 to the current limit at a configurable ramp rate set by ALIGN_SLOW_RAMP_RATE. At the end of align routine, the motor will be aligned at the known position.

6.3.10.4.2 Double Align

Double align is enabled by configuring MTR_STARTUP to 01b. Single align is not reliable when the initial position of the rotor is 180 o out of phase with the applied phase pattern. In this case, it is possible to have start-up failures using single align. In order to improve the reliability of align based start-up, the MCF8316D provides the option of double align start-up. In double align start-up, MCF8316D uses a phase pattern for the second align that is 90 o ahead of the first align phase pattern. In double align, relevant parameters like align time, current limit, ramp rate are the same as in the case of single align - two different phase patterns are applied in succession with the same parameters to ensure that the motor will be aligned to a known position irrespective of initial rotor position.

6.3.10.4.3 Initial Position Detection (IPD)

Initial Position Detection (IPD) can be enabled by configuring MTR_STARTUP to 10b. In IPD, inductive sense method is used to determine the initial position of the motor using the spatial variation in the motor inductance. Align or double align may result in the motor spinning in the reverse direction before starting open loop acceleration. IPD can be used in such applications where reverse rotation of the motor is unacceptable. IPD does not wait for the motor to align with the commutation and therefore can allow for a faster motor start-up sequence. IPD works well when the inductance of the motor varies as a function of position. IPD works by pulsing current in to the motor and hence can generate acoustics which must be taken into account when determining the best start-up method for a particular application. IPD operates by sequentially applying six different phase patterns according to the following sequence: BC-> CB-> AB-> BA-> CA-> AC (see Figure 6-31 ). When the current reaches the threshold configured by IPD_CURR_THR, the MCF8316D stops driving the particular phase pattern and measures the time taken to reach the current threshold from when the particular phase pattern was applied. Thus, the time taken to reach IPD_CURR_THR is measured for all six phase patterns - this time varies as a function of the inductance in the motor windings. The state with the shortest time represents the state with the minimum inductance. The minimum inductance is because of the alignment of the north pole of the motor with this particular driving state. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: MCF8316D

IPD_CLK Drive B C C B A B B A C A A C Current Search the Minimum Time IPD_CURR_THR A B C Minimum Time Smallest Inductance Saturation Position of the Magnetic Field Permanent Magnet Position Figure 6-31. IPD Function Two modes are available for configuring the way the MCF8316D stops driving the motor when the current threshold is reached. The recirculate (or brake) mode is selected if IPD_RLS_MODE = 0b. In this configuration, the low-side (LSC) MOSFET remains ON to allow the current to recirculate between the MOSFET (LSC) and body diode (LSA) (see Figure 6-32). Hi-Z mode is selected if IPD_RLS_MODE = 1b. In Hi-Z mode, both the high-side (HSA) and low-side (LSC) MOSFETs are turned OFF and the current recirculates through the body diodes back to the power supply (see Figure 6-33). In the Hi-Z mode, the phase current has a faster settle-down time, but that can result in a voltage increase on VM. The user must manage this with an appropriate selection of either a clamp circuit or by providing sufficient capacitance between V M and PGND to absorb the energy. If the voltage surge cannot be contained or if it is unacceptable for the application, recirculate mode must be used. When using the recirculate mode, select the IPD_CLK_FREQ appropriately to give the current in the motor windings enough time to decay to 0-A before the next IPD phase pattern is applied. M HSA LSA HSB HSC LSB LSC VM Driving Brake (Recirculate) M HSA LSA HSB HSC LSB LSC VM Figure 6-32. IPD Release Mode - Brake (0b) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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M HSA LSA HSB HSC LSB LSC VM Driving Hi-Z (Tri-State) M HSA LSA HSB HSC LSB LSC VM Figure 6-33. IPD Release Mode - Tristate (1b) After the initial position is detected, the MCF8316D begins driving the motor in open loop at an angle specified by IPD_ADV_ANGLE. Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by 90° results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the rotor. Select the IPD_ADV_ANGLE to allow for smooth acceleration in the application (see Figure 6-34). A B C Motor spinning direction 30 advance 60 advance 90 advance 120 advance A B C A B C A B C A B C Figure 6-34. IPD Advance Angle

6.3.10.4.4 Slow First Cycle Startup

Slow First Cycle start-up is enabled by configuring MTR_STARTUP to 11b. In slow first cycle start-up, the MCF8316D starts motor commutation at a frequency defined by SLOW_FIRST_CYCLE_FREQ. The frequency configured is used only for first cycle, and then the motor commutation follows acceleration profile configured by open loop acceleration coefficients A1 and A2. The slow first cycle frequency has to be configured to be slow enough to allow motor to synchronize with the commutation sequence. This mode is useful when fast startup is desired as it significantly reduces the align time.

6.3.10.4.5 Open Loop

Upon completing the motor position initialization with either align, double align, IPD or slow first cycle, the MCF8316D begins to accelerate the motor in open loop. In MCF8316D, the current limit in open loop is set by OL_ILIMIT and the speed is increased using this current. In open loop, the control PI loops for I q and Id actively control the currents. The angle during open loop is provided from the ramp generator as shown in Figure 6-35. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: MCF8316D

Torque (Iq) PI Controller Inverse Clarke/ SVM Clarke Ia Ib Ic Va Vb Vc I I V V Id Iq Vq Vd SPEED_EST ( est) Iq_ref Flux (Id) PI Controller Id_ref = 0 Open Loop Ramp Generator (A1 and A2) VM -VM VM -VM gen est Back-EMF Observer I V V I OL_ILIMIT ALIGN_SLOW_ RAMP_RATE Id_ref Modulation index reference CL_ACC / CL_DEC Vq and Vd calculation ILIMIT -ILIMIT SPEED_REF / POWER_REF Speed/ Power PI Controller CURRENT_REF INPUT_REFERENCE_ MODE = 10b INPUT_REFER ENCE_MODE = 00b or 01b SPEED_EST / POWER_EST CL_ACC / CL_DEC CL_ACC / CL_DEC Flux Weakening Control *cos(LEAD _ANGLE) *sin(LEAD _ANGLE) Mod. Index FLUX_WEAK_ REF Mod. Index < FLUX_WEAK_ REF Min(Itarget *cos(LEAD_ANGLE), (ILIMIT2 – Id_ref 2)) Itarget CIR_CURR_ LIM_EN = 0b Figure 6-35. Open Loop The function of the open-loop operation is to drive the motor to a speed at which the motor generates sufficient BEMF to allow the back-EMF observer to accurately detect the position of the rotor. The motor is accelerated in open loop and speed at any given time is determined by Equation 7. In MCF8316D, open loop acceleration coefficients, A1 and A2 are configured through OL_ACC_A1 and OL_ACC_A2 respectively. Speed(t) = A1 * t + 0.5 * A2 * t2 (7)

6.3.10.4.6 Transition from Open to Closed Loop

Once the motor has reached a sufficient speed for the back-EMF observer to estimate the angle and speed of the motor, the MCF8316D transitions into closed loop state. This handoff speed is automatically determined based on the measured back-EMF and motor speed. Users also have an option to manually set the handoff speed by configuring OPN_CL_HANDOFF_THR and setting AUTO_HANDOFF_EN to 0b. In order to have smooth transition and avoid speed transients, the theta error (Ɵ gen - Ɵ est) is decreased linearly after transition. The ramp rate of theta error reduction can be configured using THETA_ERROR_RAMP_RATE. If the current limit set during the open loop is high and if it is not reduced before transition to closed loop, the motor speed may momentarily rise to higher values than SPEED_REF after transition into closed loop. In order to avoid such speed variations, configure the IQ_RAMP_EN to 1b, so that i q_ref decreases prior to transition into closed loop. However if the final speed reference (SPEED_REF) is more than two times the open loop to closed loop hand off speed (OPN_CL_HANDOFF_THR), then i q_ref is not decreased independent of the IQ_RAMP_EN setting, to enable faster motor acceleration. After hand off to closed loop at a sufficient speed, there could be still some theta error, as the estimators may not be fully aligned. A slow acceleration can be used after the open loop to closed loop transition, ensuring that the theta error reduces to zero. The slow acceleration can be configured using CL_SLOW_ACC. Figure 6-36 shows the control sequence in open to closed loop transition. The current i q_ref reduces to a lower value in current decay region, if IQ_RAMP_EN is set to 1b. If IQ_RAMP_EN is set to 0b, then the current decay region will not be present in the transition sequence. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Theta_error iqref I. Open Loop Accelera on, II. Current Decay, III. Closed loop slow accelera on IV. Closed loop accelera on, V. Closed loop steady state SPEED I II III IV V THETA_ERROR_RAMP_RATE OPN_CL_HANDOFF_THR SPEED_REF Figure 6-36. Control Sequence in Open to Closed Loop Transition www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: MCF8316D

Torque (Iq) PI Controller Inverse Clarke/ SVM Clarke Ia Ib Ic Va Vb Vc I I V V Id Iq Vq Vd SPEED_EST ( est) Iq_ref Flux (Id) PI Controller Id_ref = 0 Open Loop Ramp Generator (A1 and A2) VM -VM VM -VM gen est Back-EMF Observer I V V I OL_ILIMIT ALIGN_SLOW_ RAMP_RATE Id_ref Modulation index reference CL_ACC / CL_DEC Vq and Vd calculation ILIMIT -ILIMIT SPEED_REF / POWER_REF Speed/ Power PI Controller CURRENT_REF SPEED_EST / POWER_EST CL_ACC / CL_DEC CL_ACC / CL_DEC Flux Weakening Control *cos(LEAD _ANGLE) *sin(LEAD _ANGLE) Mod. Index FLUX_WEAK_ REF Mod. Index < FLUX_WEAK_ REF Min(Itarget *cos(LEAD_ANGLE), (ILIMIT2 – Id_ref 2)) Itarget CIR_CURR_ LIM_EN = 0b CIR_CURR_ LIM_EN = 1b INPUT_REFERENCE_ MODE = 10b INPUT_REFER ENCE_MODE = 00b or 01b Figure 6-37. Open to Closed Loop Transition Control Block Diagram MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.3.11 Closed Loop Operation

The MCF8316D drives the motor using Field Oriented Control (FOC) as shown in Figure 6-38. In closed loop operation, the motor angle (Ɵ est) and speed (SPEED_EST) are estimated using the back-EMF observer. The speed, power or current regulation is achieved using PI control loops. Inverse Park Torque (Iq) PI Controller Inverse Clarke/ SVM Clarke Ia Ib Ic Va Vb Vc I I V V Id Iq Vq Vd Iq_ref Flux (Id) PI Controller Id_ref ILIMIT -ILIMIT VM -VM est SPEED_REF / POWER_REF I I V V Speed/ Power PI Controller BEMF Observer Park CURRENT_REF SPEED_EST / POWER_EST CL_ACC / CL_DEC SPEED_EST ( est) VM -VM CL_ACC / CL_DEC Modulation index reference CL_ACC / CL_DEC Vq and Vd calculation Flux Weakening Control *cos(LEAD _ANGLE) *sin(LEAD _ANGLE) Mod. Index FLUX_WEAK_ REF Mod. Index < FLUX_WEAK_ REF Min(Itarget *cos(LEAD_ANGLE), (ILIMIT2 – Id_ref 2)) Itarget CIR_CURR_ LIM_EN = 0b CIR_CURR_ LIM_EN = 1b INPUT_REFERENCE_ MODE = 10b INPUT_REFER ENCE_MODE = 00b or 01b INPUT_REFERENCE_ MODE = 11b Figure 6-38. Closed Loop FOC Control

6.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate

During closed loop acceleration/deceleration, MCF8316D provides the option of configuring the slew rate of the reference input. This allows for a linear change in reference input (speed or power or current or modulation index) even when there is a step change in reference input (from Analog, PWM, Frequency or I 2C) as seen in Figure 6-39 . This slew rate can be configured so as to prevent sudden changes in the torque applied to the motor which could result in acoustic noise. The closed loop acceleration/deceleration slew rate parameter, CL_ACC/CL_DEC, sets the slew rate of the reference during acceleration and deceleration respectively. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: MCF8316D

REF_1 REF_1 REF_2 REF_2 t t Reference input can be ramped at different rates based on CL_ACC or CL_DEC Figure 6-39. Closed Loop Acceleration/Deceleration Slew Rate

6.3.11.2 Speed PI Control

The integrated speed control loop helps maintain a constant speed over varying operating conditions. The K p and Ki coefficients are configured through SPD_LOOP_KP and SPD_LOOP_KI. The output of the speed loop is used to generate the current reference for torque control (I q_ref). The output of the speed loop is limited to implement a current limit. The current limit is set by configuring ILIMIT. When output of the speed loop saturates, the integrator is disabled to prevent integral wind-up. SPEED_REF_SLEW is derived from the duty command input, speed profiles and closed loop acceleration/ deceleration rates configured by the user and SPEED_EST is the estimated speed from the back-EMF observer. Kp Ki Z-1 SPEED_REF_SLEW SPEED_EST OUT Iq_ref ILIMIT -ILIMIT Switch close, if -ILIMIT < OUT < ILIMIT Figure 6-40. Speed PI Control

6.3.11.3 Current PI Control

The MCF8316D has two PI controllers, one each for I d and I q to control flux and torque separately. K p and K i coefficients are the same for both PI controllers and are configured through CURR_LOOP_KP and CURR_LOOP_KI. The outputs of the current control loops are used to generate voltage signals V d and Vq to be MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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applied to the motor. The outputs of the current loops are clamped to supply voltage V M. Id current PI loop is executed first and output of I d current PI loop V d is checked for saturation. When the output of the current loop saturates, the integration is disabled to prevent integral wind-up. Kp Ki Z-1 Id_ref Id OUT Vd VM -VM Switch close, if -VM < Vd < VM Priority is given to Vd; Vd is calculated first for saturaon detecon Figure 6-41. Id Current PI Control Kp Ki Z-1 Iq_ref Iq OUT Vq VM -VM Switch close, if Vd 2 + Vq 2 < VM2 when overmodula on is disabled; when enabled, switch close if -VM < Vq < VM Priority is given to Vd; Vd is calculated first for saturaon detecon Figure 6-42. Iq Current PI Control

6.3.11.4 Power Control Mode

MCF8316D provides an option of regulating the (input DC) power instead of motor speed for a closed loop power control. Input power regulation (instead of motor speed) mode is selected by setting INPUT_REFERENCE_MODE to 01b. The maximum power that MCF8316D can draw from the DC input supply is set by MAX_POWER. The K p and Ki coefficients for power loop are configured through SPD_LOOP_KP and SPD_LOOP_KI. POWER_REF (W) = DUTY_CMD (%) x MAX_POWER (W) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: MCF8316D

-ILIMIT Switch Close If -ILIMIT < OUT <ILIMIT POWER_REF_SLEW POWER ESTIMATED MEASURED INPUT DC VOLTAGE ESTIMATED INPUT DC CURRENT PI_OUT Figure 6-43. Closed Loop Power Control

6.3.11.5 Current (Torque) Control Mode

MCF8316D provides the option of controlling the motor q- and d-axis currents directly by setting INPUT_REFERENCE_MODE to 10b. In this mode, the q- and d-axis current references, I q_ref and I d_ref is directly set by the duty cycle input, DUTY CMD, ILIMIT and LEAD_ANGLE instead of the speed PI loop output as shown in Figure 6-38. Thus, this mode enables torque control through setting ILIMIT and hence can be used for torque mode operation.

6.3.11.6 Modulation Index Control

MCF8316D provides voltage control mode, selected by setting INPUT_REFERENCE_MODE to 11b. The closed loop speed control, power control and current control (iq and id) are disabled in this mode. The applied Vq and Vd are controlled directly using the user defined modulation index reference voltage (VOLTAGE REF) and the lead angle setting. The VOLTAGE REF varies from MIN_DUTY to 100%. Vq,MAX MODULATION INDEX REF (Vs) Vq Vd LEAD ANGLE ( ) Vd,MAX Vs * cos( ) -Vs * sin( )MODULATION INDEX REF (Vs) LEAD ANGLE ( ) Figure 6-44. Open Loop Voltage Control Note MCF8316D does not support recirculation stop mode during modulation index control mode.

6.3.11.7 Overmodulation

MCF8316D provides an overmodulation option to operate the motor at a higher speed at the same VM voltage by increasing the applied fundamental phase voltage by suitably modifying the applied PWM pattern - the higher fundamental phase voltage is accompanied by an increase in higher order harmonics. This feature can be enabled by setting OVERMODULATION_ENABLE to 1b.

6.3.11.8 Motor Speed Limit

MCF8316D provides the option of limiting the motor speed to a user configured limit. When SPEED_LIMIT_ENABLE is set to 1b, irrespective of the input reference mode (current, power or voltage) and operating conditions like (VM, load), MCF8316D limits the motor speed to MAX_SPEED by restricting the input DC power, motor phase current or voltage (depending on input reference mode). When speed limit is active MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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(motor speed limited at MAX_SPEED), the acceleration/deceleration rate is set by CL_SLOW_ACC instead of CL_ACC/CL_DEC to minimize chattering around the MAX_SPEED value. When the speed limit condition becomes inactive (motor speed < MAX_SPEED), acceleration/deceleration rate reverts to CL_ACC/CL_DEC.

6.3.11.9 Input DC Power Limit

MCF8316D provides the option of limiting the power that the motor driver can draw from the input DC source (VM). When BUS_POWER_LIMIT_ENABLE is set to 1b, irrespective of the input reference mode (speed, current, or voltage) and operating conditions like (VM, load), MCF8316D limits the input DC power to MAX_POWER by restricting the motor speed, current or voltage (depending on input reference mode). When power limit is active (input DC power limited at MAX_POWER), the acceleration/deceleration rate is set by CL_SLOW_ACC instead of CL_ACC/CL_DEC to minimize chattering around the MAX_POWER value. When the power limit condition becomes inactive (input DC power < MAX_POWER), acceleration/deceleration rate reverts to CL_ACC/CL_DEC.

6.3.12 Flux Weakening Control

PMSM motors can be operated not only in the constant torque region below the base speed (rated speed) but also in the constant power region above the base speed, but the base speed can be varied according to current and voltage limitation. MCF8316D provides a flux weakening control, to increase the motor speed beyond the rated speed. The flux weakening can be enabled by setting FLUX_WEAK_EN to 1b. The flux weakening control uses a PI control loop as shown in , to create the I d_ref. Kp and Ki coefficients for flux weakening loop are configured through FLUX_WEAK_KP and FLUX_WEAK_KI. User can configure the modulation index reference, V s_ref (shown in Figure 6-45) below that the flux weakening is not active and Id_FW is set to zero. The configuration is available in the bits FLUX_WEAK_REF. V s _ re f = V q _ r e f 2 + V d _ re f 2 (8) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: MCF8316D

Vs_ref Id_ref Flux Weakening Id_FW Id_ref = Id_FW if mod. index FLUX_WEAK_REF, else Id_ref = Itarget * sin(LEAD_ANGLE) Kp Ki Z-1 Iq_ref Iq OUT Vq VM -VM Switch close, if Vd 2 + Vq 2 < VM2 Kp Ki Z-1 Id OUT Vd VM -VM Switch close, if -VM < Vd < VM Figure 6-45. Flux Weakening Control

6.3.13 Motor Parameters

The MCF8316D uses the motor resistance, motor inductance and motor back-EMF constant to estimate motor position when operating in closed loop. The MCF8316D has the capability of measuring these motor parameters in the offline state (see Motor Parameter Extraction Tool (MPET) ). Offline measurement of parameters, when enabled, takes place before normal motor operation. The user can also disable the offline measurement and configure motor parameters through EEPROM. This feature of offline motor parameter measurement is useful to account for motor to motor variation during manufacturing.

6.3.13.1 Motor Resistance

For a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the center tap, RPH (denoted as RPH in Figure 6-46). For a delta-connected motor, the motor phase resistance refers to the equivalent phase to center tap in the wye configuration in Figure 6-46. Phase A Phase BPhase C RPH_PH R PH _PH R PH _PH RPH RPH RPH CT Figure 6-46. Motor Resistance For both the delta-connected and the wye-connected motor, the easy way to get the equivalent R PH is to measure the resistance between two phase terminals (R PH_PH), and then divide this value by two, R PH = ½ MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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RPH_PH. In wye-connected motor, if user has access to center tap (CT), R PH can also be measured between center tap (CT) and phase terminal. Configure the motor resistance (RPH) to a nearest value from Table 6-2. Table 6-2. Motor Resistance Look-Up Table MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) 0x00 Self Measurement (see Motor Parameter Extraction Tool (MPET)) 0x40 0.145 0x80 0.465 0xC0 2.1 0x01 0.006 0x41 0.150 0x81 0.470 0xC1 2.2 0x02 0.007 0x42 0.155 0x82 0.475 0xC2 2.3 0x03 0.008 0x43 0.160 0x83 0.480 0xC3 2.4 0x04 0.009 0x44 0.165 0x84 0.485 0xC4 2.5 0x05 0.010 0x45 0.170 0x85 0.490 0xC5 2.6 0x06 0.011 0x46 0.175 0x86 0.495 0xC6 2.7 0x07 0.012 0x47 0.180 0x87 0.50 0xC7 2.8 0x08 0.013 0x48 0.185 0x88 0.51 0xC8 2.9 0x09 0.014 0x49 0.190 0x89 0.52 0xC9 3.0 0x0A 0.015 0x4A 0.195 0x8A 0.53 0xCA 3.2 0x0B 0.016 0x4B 0.200 0x8B 0.54 0xCB 3.4 0x0C 0.017 0x4C 0.205 0x8C 0.55 0xCC 3.6 0x0D 0.018 0x4D 0.210 0x8D 0.56 0xCD 3.8 0x0E 0.019 0x4E 0.215 0x8E 0.57 0xCE 4.0 0x0F 0.020 0x4F 0.220 0x8F 0.58 0xCF 4.2 0x10 0.022 0x50 0.225 0x90 0.59 0xD0 4.4 0x11 0.024 0x51 0.230 0x91 0.60 0xD1 4.6 0x12 0.026 0x52 0.235 0x92 0.61 0xD2 4.8 0x13 0.028 0x53 0.240 0x93 0.62 0xD3 5.0 0x14 0.030 0x54 0.245 0x94 0.63 0xD4 5.2 0x15 0.032 0x55 0.250 0x95 0.64 0xD5 5.4 0x16 0.034 0x56 0.255 0x96 0.65 0xD6 5.6 0x17 0.036 0x57 0.260 0x97 0.66 0xD7 5.8 0x18 0.038 0x58 0.265 0x98 0.67 0xD8 6.0 0x19 0.040 0x59 0.270 0x99 0.68 0xD9 6.2 0x1A 0.042 0x5A 0.275 0x9A 0.69 0xDA 6.4 0x1B 0.044 0x5B 0.280 0x9B 0.70 0xDB 6.6 0x1C 0.046 0x5C 0.285 0x9C 0.72 0xDC 6.8 0x1D 0.048 0x5D 0.290 0x9D 0.74 0xDD 7.0 0x1E 0.050 0x5E 0.295 0x9E 0.76 0xDE 7.2 0x1F 0.052 0x5F 0.300 0x9F 0.78 0xDF 7.4 0x20 0.054 0x60 0.305 0xA0 0.80 0xE0 7.6 0x21 0.056 0x61 0.310 0xA1 0.82 0xE1 7.8 0x22 0.058 0x62 0.315 0xA2 0.84 0xE2 8.0 0x23 0.060 0x63 0.320 0xA3 0.86 0xE3 8.2 0x24 0.062 0x64 0.325 0xA4 0.88 0xE4 8.4 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: MCF8316D

Table 6-2. Motor Resistance Look-Up Table (continued) MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) MOTOR_RES (HEX) RPH (Ω) 0x25 0.064 0x65 0.330 0xA5 0.90 0xE5 8.6 0x26 0.066 0x66 0.335 0xA6 0.92 0xE6 8.8 0x27 0.068 0x67 0.340 0xA7 0.94 0xE7 9 0x28 0.070 0x68 0.345 0xA8 0.96 0xE8 9.2 0x29 0.072 0x69 0.350 0xA9 0.98 0xE9 9.4 0x2A 0.074 0x6A 0.355 0xAA 1.00 0xEA 9.6 0x2B 0.076 0x6B 0.360 0xAB 1.05 0xEB 9.8 0x2C 0.078 0x6C 0.365 0xAC 1.10 0xEC 10.0 0x2D 0.080 0x6D 0.370 0xAD 1.15 0xED 10.5 0x2E 0.082 0x6E 0.375 0xAE 1.20 0xEE 11.0 0x2F 0.084 0x6F 0.380 0xAF 1.25 0xEF 11.5 0x30 0.086 0x70 0.385 0xB0 1.30 0xF0 12.0 0x31 0.088 0x71 0.390 0xB1 1.35 0xF1 12.5 0x32 0.090 0x72 0.395 0xB2 1.40 0xF2 13.0 0x33 0.092 0x73 0.400 0xB3 1.45 0xF3 13.5 0x34 0.094 0x74 0.405 0xB4 1.50 0xF4 14.0 0x35 0.096 0x75 0.410 0xB5 1.55 0xF5 14.5 0x36 0.098 0x76 0.415 0xB6 1.60 0xF6 15.0 0x37 0.100 0x77 0.420 0xB7 1.65 0xF7 15.5 0x38 0.105 0x78 0.425 0xB8 1.70 0xF8 16.0 0x39 0.110 0x79 0.430 0xB9 1.75 0xF9 16.5 0x3A 0.115 0x7A 0.435 0xBA 1.80 0xFA 17.0 0x3B 0.120 0x7B 0.440 0xBB 1.85 0xFB 17.5 0x3C 0.125 0x7C 0.445 0xBC 1.90 0xFC 18.0 0x3D 0.130 0x7D 0.450 0xBD 1.95 0xFD 18.5 0x3E 0.135 0x7E 0.455 0xBE 2.00 0xFE 19.0 0x3F 0.140 0x7F 0.460 0xBF 2.05 0xFF 20.0

6.3.13.2 Motor Inductance

For a wye-connected motor, the motor phase inductance refers to the inductance from the phase output to the center tap, LPH (denoted as LPH in Figure 6-47). For a delta-connected motor, the motor phase inductance refers to the equivalent phase to center tap in the wye configuration in Figure 6-47. LPH_PH Phase A Phase BPhase C L PH _PH LPH _PH LPH LPH LPH CT Figure 6-47. Motor Inductance For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent L PH is to measure the inductance between two phase terminals (L PH_PH), and then divide this value by two, L PH = ½ LPH_PH. In wye-connected motor, if user has access to center tap (CT), L PH can also be measured between center tap (CT) and phase terminal. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Configure the motor inductance (LPH) to a nearest value from Table 6-3. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: MCF8316D

Table 6-3. Motor Inductance Look-Up Table MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) 0x00 Self Measurement (see Motor Parameter Extraction Tool (MPET)) 0x40 0.145 0x80 0.465 0xC0 2.1 0x01 0.006 0x41 0.150 0x81 0.470 0xC1 2.2 0x02 0.007 0x42 0.155 0x82 0.475 0xC2 2.3 0x03 0.008 0x43 0.160 0x83 0.480 0xC3 2.4 0x04 0.009 0x44 0.165 0x84 0.485 0xC4 2.5 0x05 0.010 0x45 0.170 0x85 0.490 0xC5 2.6 0x06 0.011 0x46 0.175 0x86 0.495 0xC6 2.7 0x07 0.012 0x47 0.180 0x87 0.50 0xC7 2.8 0x08 0.013 0x48 0.185 0x88 0.51 0xC8 2.9 0x09 0.014 0x49 0.190 0x89 0.52 0xC9 3.0 0x0A 0.015 0x4A 0.195 0x8A 0.53 0xCA 3.2 0x0B 0.016 0x4B 0.200 0x8B 0.54 0xCB 3.4 0x0C 0.017 0x4C 0.205 0x8C 0.55 0xCC 3.6 0x0D 0.018 0x4D 0.210 0x8D 0.56 0xCD 3.8 0x0E 0.019 0x4E 0.215 0x8E 0.57 0xCE 4.0 0x0F 0.020 0x4F 0.220 0x8F 0.58 0xCF 4.2 0x10 0.022 0x50 0.225 0x90 0.59 0xD0 4.4 0x11 0.024 0x51 0.230 0x91 0.60 0xD1 4.6 0x12 0.026 0x52 0.235 0x92 0.61 0xD2 4.8 0x13 0.028 0x53 0.240 0x93 0.62 0xD3 5.0 0x14 0.030 0x54 0.245 0x94 0.63 0xD4 5.2 0x15 0.032 0x55 0.250 0x95 0.64 0xD5 5.4 0x16 0.034 0x56 0.255 0x96 0.65 0xD6 5.6 0x17 0.036 0x57 0.260 0x97 0.66 0xD7 5.8 0x18 0.038 0x58 0.265 0x98 0.67 0xD8 6.0 0x19 0.040 0x59 0.270 0x99 0.68 0xD9 6.2 0x1A 0.042 0x5A 0.275 0x9A 0.69 0xDA 6.4 0x1B 0.044 0x5B 0.280 0x9B 0.70 0xDB 6.6 0x1C 0.046 0x5C 0.285 0x9C 0.72 0xDC 6.8 0x1D 0.048 0x5D 0.290 0x9D 0.74 0xDD 7.0 0x1E 0.050 0x5E 0.295 0x9E 0.76 0xDE 7.2 0x1F 0.052 0x5F 0.300 0x9F 0.78 0xDF 7.4 0x20 0.054 0x60 0.305 0xA0 0.80 0xE0 7.6 0x21 0.056 0x61 0.310 0xA1 0.82 0xE1 7.8 0x22 0.058 0x62 0.315 0xA2 0.84 0xE2 8.0 0x23 0.060 0x63 0.320 0xA3 0.86 0xE3 8.2 0x24 0.062 0x64 0.325 0xA4 0.88 0xE4 8.4 0x25 0.064 0x65 0.330 0xA5 0.90 0xE5 8.6 0x26 0.066 0x66 0.335 0xA6 0.92 0xE6 8.8 0x27 0.068 0x67 0.340 0xA7 0.94 0xE7 9 0x28 0.070 0x68 0.345 0xA8 0.96 0xE8 9.2 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-3. Motor Inductance Look-Up Table (continued) MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) MOTOR_IND (HEX) LPH (mH) 0x29 0.072 0x69 0.350 0xA9 0.98 0xE9 9.4 0x2A 0.074 0x6A 0.355 0xAA 1.00 0xEA 9.6 0x2B 0.076 0x6B 0.360 0xAB 1.05 0xEB 9.8 0x2C 0.078 0x6C 0.365 0xAC 1.10 0xEC 10.0 0x2D 0.080 0x6D 0.370 0xAD 1.15 0xED 10.5 0x2E 0.082 0x6E 0.375 0xAE 1.20 0xEE 11.0 0x2F 0.084 0x6F 0.380 0xAF 1.25 0xEF 11.5 0x30 0.086 0x70 0.385 0xB0 1.30 0xF0 12.0 0x31 0.088 0x71 0.390 0xB1 1.35 0xF1 12.5 0x32 0.090 0x72 0.395 0xB2 1.40 0xF2 13.0 0x33 0.092 0x73 0.400 0xB3 1.45 0xF3 13.5 0x34 0.094 0x74 0.405 0xB4 1.50 0xF4 14.0 0x35 0.096 0x75 0.410 0xB5 1.55 0xF5 14.5 0x36 0.098 0x76 0.415 0xB6 1.60 0xF6 15.0 0x37 0.100 0x77 0.420 0xB7 1.65 0xF7 15.5 0x38 0.105 0x78 0.425 0xB8 1.70 0xF8 16.0 0x39 0.110 0x79 0.430 0xB9 1.75 0xF9 16.5 0x3A 0.115 0x7A 0.435 0xBA 1.80 0xFA 17.0 0x3B 0.120 0x7B 0.440 0xBB 1.85 0xFB 17.5 0x3C 0.125 0x7C 0.445 0xBC 1.90 0xFC 18.0 0x3D 0.130 0x7D 0.450 0xBD 1.95 0xFD 18.5 0x3E 0.135 0x7E 0.455 0xBE 2.00 0xFE 19.0 0x3F 0.140 0x7F 0.460 0xBF 2.05 0xFF 20.0

6.3.13.3 Motor Back-EMF constant

The back-EMF constant describes the motor phase-to-neutral back-EMF voltage as a function of the motor speed. For a wye-connected motor, the motor BEMF constant refers to the BEMF as a function of time from the phase output to the center tap, Kt PH_N (denoted as Kt PH_N in Figure 6-48). For a delta-connected motor, the motor BEMF constant refers to the equivalent phase to center tap in the wye configuration in Figure 6-48. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: MCF8316D

EPH_A LPH RPH EPH_C LPH R PH EPH_B EPH tE KtPH_N = (1/sqrt(3)) *EPH * tE L PH R PH E PH_A LPHRPH EPH_B LPH R PH EPH_C Figure 6-48. Motor back-EMF constant For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent Kt PH_N is to measure the peak value of BEMF on scope for one electrical cycle between two phase terminals (E PH), and then multiply by time duration of one electrical cycle and in order to convert from phase-to-phase to phase-to-neutral divide by sqrt(3) as shown in Equation 9 . Kt PH _ N = 1 3 × E PH × t E (9) Configure the motor BEMF constant (KtPH_N) to a nearest value from Table 6-4. Table 6-4. Motor BEMF constant Look-Up Table MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEM F_CONST (HEX) KtPH_N (mV/Hz) 0x00 Self Measurement (see Motor Parameter Extraction Tool (MPET)) 0x40 14.5 0x80 46.5 0xC0 210 0x01 0.6 0x41 15.0 0x81 47.0 0xC1 220 0x02 0.7 0x42 15.5 0x82 47.5 0xC2 230 0x03 0.8 0x43 16.0 0x83 48.0 0xC3 240 0x04 0.9 0x44 16.5 0x84 48.5 0xC4 250 0x05 1.0 0x45 17.0 0x85 49.0 0xC5 260 0x06 1.1 0x46 17.5 0x86 49.5 0xC6 270 0x07 1.2 0x47 18.0 0x87 50.0 0xC7 280 0x08 1.3 0x48 18.5 0x88 51 0xC8 290 0x09 1.4 0x49 19.0 0x89 52 0xC9 300 0x0A 1.5 0x4A 19.5 0x8A 53 0xCA 320 0x0B 1.6 0x4B 20.0 0x8B 54 0xCB 340 0x0C 1.7 0x4C 20.5 0x8C 55 0xCC 360 0x0D 1.8 0x4D 21.0 0x8D 56 0xCD 380 0x0E 1.9 0x4E 21.5 0x8E 57 0xCE 400 0x0F 2.0 0x4F 22.0 0x8F 58 0xCF 420 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-4. Motor BEMF constant Look-Up Table (continued) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEM F_CONST (HEX) KtPH_N (mV/Hz) 0x10 2.2 0x50 22.5 0x90 59 0xD0 440 0x11 2.4 0x51 23.0 0x91 60 0xD1 460 0x12 2.6 0x52 23.5 0x92 61 0xD2 480 0x13 2.8 0x53 24.0 0x93 62 0xD3 500 0x14 3.0 0x54 24.5 0x94 63 0xD4 520 0x15 3.2 0x55 25.0 0x95 64 0xD5 540 0x16 3.4 0x56 25.5 0x96 65 0xD6 560 0x17 3.6 0x57 26.0 0x97 66 0xD7 580 0x18 3.8 0x58 26.5 0x98 67 0xD8 600 0x19 4.0 0x59 27.0 0x99 68 0xD9 620 0x1A 4.2 0x5A 27.5 0x9A 69 0xDA 640 0x1B 4.4 0x5B 28.0 0x9B 70 0xDB 660 0x1C 4.6 0x5C 28.5 0x9C 72 0xDC 680 0x1D 4.8 0x5D 29.0 0x9D 74 0xDD 700 0x1E 5.0 0x5E 29.5 0x9E 76 0xDE 720 0x1F 5.2 0x5F 30.0 0x9F 78 0xDF 740 0x20 5.4 0x60 30.5 0xA0 80 0xE0 760 0x21 5.6 0x61 31.0 0xA1 82 0xE1 780 0x22 5.8 0x62 31.5 0xA2 84 0xE2 800 0x23 6.0 0x63 32.0 0xA3 86 0xE3 820 0x24 6.2 0x64 32.5 0xA4 88 0xE4 840 0x25 6.4 0x65 33.0 0xA5 90 0xE5 860 0x26 6.6 0x66 33.5 0xA6 92 0xE6 880 0x27 6.8 0x67 34.0 0xA7 94 0xE7 900 0x28 7.0 0x68 34.5 0xA8 96 0xE8 920 0x29 7.2 0x69 35.0 0xA9 98 0xE9 940 0x2A 7.4 0x6A 35.5 0xAA 100 0xEA 960 0x2B 7.6 0x6B 36.0 0xAB 105 0xEB 980 0x2C 7.8 0x6C 36.5 0xAC 110 0xEC 1000 0x2D 8.0 0x6D 37.0 0xAD 115 0xED 1050 0x2E 8.2 0x6E 37.5 0xAE 120 0xEE 1100 0x2F 8.4 0x6F 38.0 0xAF 125 0xEF 1150 0x30 8.6 0x70 38.5 0xB0 130 0xF0 1200 0x31 8.8 0x71 39.0 0xB1 135 0xF1 1250 0x32 9.0 0x72 39.5 0xB2 140 0xF2 1300 0x33 9.2 0x73 40.0 0xB3 145 0xF3 1350 0x34 9.4 0x74 40.5 0xB4 150 0xF4 1400 0x35 9.6 0x75 41.0 0xB5 155 0xF5 1450 0x36 9.8 0x76 41.5 0xB6 160 0xF6 1500 0x37 10.0 0x77 42.0 0xB7 165 0xF7 1550 0x38 10.5 0x78 42.5 0xB8 170 0xF8 1600 0x39 11.0 0x79 43.0 0xB9 175 0xF9 1650 0x3A 11.5 0x7A 43.5 0xBA 180 0xFA 1700 0x3B 12.0 0x7B 44.0 0xBB 185 0xFB 1750 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: MCF8316D

Table 6-4. Motor BEMF constant Look-Up Table (continued) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEMF_ CONST (HEX) KtPH_N (mV/Hz) MOTOR_BEM F_CONST (HEX) KtPH_N (mV/Hz) 0x3C 12.5 0x7C 44.5 0xBC 190 0xFC 1800 0x3D 13.0 0x7D 45.0 0xBD 195 0xFD 1850 0x3E 13.5 0x7E 45.5 0xBE 200 0xFE 1900 0x3F 14.0 0x7F 46.0 0xBF 205 0xFF 2000

6.3.14 Motor Parameter Extraction Tool (MPET)

The MCF8316D uses motor winding resistance, motor winding inductance and Back-EMF constant to estimate motor position in closed loop operation. The MCF8316D has capability of automatically measuring motor parameters in offline state, rather than having the user enter the values themselves. The MPET routine measures motor winding resistance, inductance, back EMF constant and mechanical load inertia and frictional coefficients. Offline measurement of parameters takes place before normal motor operation. TI recommends to estimate the motor parameters before motor startup to minimize the impact caused due to possible parameter variations. Figure 6-49 shows the sequence of operation in the MPET routine. The MPET routine is entered when either the MPET_CMD bit is set to 1b or a non-zero target speed is set. The MPET routine consists of four steps namely, IPD, Open Loop Acceleration, Current Ramp Down and Coasting. Each one of these steps are executed if the condition shown below the step evaluates to TRUE; if the condition evaluates to FALSE, the algorithm bypasses that particular step and moves on to the next step in the sequence. Once all the 4 steps are completed (or bypassed), the algorithm exits the MPET routine. If target speed is set to a non-zero value, the algorithm begins the start-up and acceleration sequence (to target speed reference) once MPET routine is exited. IPD MPET_R = 1b || MPET_L = 1b || MOTOR_RES = 0 || MOTOR_IND = 0 Motor R and L estimated; Open Loop Acceleration Coasting BEMF Constant and Mechanical Parameter Measurement BEMF constant estimated, initial speed PI loop constants tuned Current Ramp Down MPET_KE = 1b || MPET_MECH = 1b || MOTOR_BEMF_CONST = 0 || SPD_LOOP_KP = 0 || SPD_LOOP_KI = 0 Motor Winding R and L Measurement MPET_MECH = 1b || SPD_LOOP_KP = 0 || SPD_LOOP_KI = 0 MPET_KE = 1b || MPET_MECH = 1b || MOTOR_BEMF_CONST = 0 || SPD_LOOP_KP = 0 || SPD_LOOP_KI = 0 MPET_CMD = 1b || Target_speed is non- zero End of MPET Figure 6-49. MPET Sequence TI proprietary MPET routine includes following sequence of operation.

• IPD: The MPET routine starts with IPD, if the user enables motor winding resistance or inductance measurement by setting MPET_R = 1b and MPET_L = 1b or if the user defines MOTOR_RES = 0 or MOTOR_IND = 0. The IPD during MPET is configured using the normal motor operation IPD configuration parameters. The IPD current limit and the repeat number is configured using IPD_CURR_THR and IPD_REPEAT. The IPD timer over flow or the IPD current decay time more than three times the current ramp up time can result in MPET_IPD_FAULT.
• Open loop Acceleration: After IPD, the MPET routine runs align and then open loop acceleration if the back-EMF constant or mechanical parameter measurement are enabled by setting MPET_KE = 1b and MPET_MECH = 1b. The MPET routine incorporates the sequences for mechanical parameter measurement, if the speed loop PI constants are defined as zero, even if MPET_MECH = 0b. This routine uses normal motor operation open loop configuration parameters. The speed slew rate is set by OL_ACC_A1 and OL_ACC_A2, current reference is set by OL_ILIMIT and speed reference is set by OPN_CL_HANDOFF_THR. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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• Current Ramp Down: After open loop acceleration, if the mechanical parameter measurement is enabled, then the MPET routine optimizes the motor current to lower value sufficient to support the load. If mechanical parameter measurement is disabled (MPET_MECH = 0b, or non-zero speed loop PI parameters) then the MPET will not have the current ramp down sequence.
• Coasting: MPET routine completes the sequence by allowing the motor to coast by enabling Hi-Z. The motor back EMF and indicative values of mechanical parameters are measured during the motor coasting period. If the motor back EMF is lower than the threshold defined in STAT_DETECT_THR, the MPET_BEMF_FAULT is generated. Note User can exit the MPET routine at any time by writing 0b to MPET_CMD bit and by making target speed as zero. Selecting the parameters from EEPROM or MPET The MPET estimated values are available in the MTR_PARAMS Register. Setting the MPET_WRITE_SHADOW bit to 1, writes the MPET estimated values to the shadow/RAM registers and the user-configured (from EEPROM) values in MOTOR_RES, MOTOR_IND, MOTOR_BEMF_CONST, CURR_LOOP_KP, CURR_LOOP_KI, SPD_LOOP_KP and SPD_LOOP_KI shadow/RAM registers will be overwritten by the estimated values from MPET. If any of the shadow/RAM registers are initialized to zero (from EEPROM registers), the MPET estimated values are used for those registers independent of the MPET_WRITE_SHADOW setting. The MPET calculates the current loop KP and KI by using the measured resistance and inductance. The MPET does an estimation of the mechanical parameters including the inertia and frictional coefficient at the shaft (includes both motor and shaft coupled load). These values are used to set an initial values speed loop KP and KI. The estimated speed loop KP and KI setting can be used as an initial setting only and TI recommends to tune these parameters on application by the user based on the performance requirement.

6.3.15 Anti-Voltage Surge (AVS)

When a motor is driven, energy is transferred from the power supply into the motor. Some of this energy is stored in the form of inductive and mechanical energy. If the speed command suddenly drops such that the BEMF voltage generated by the motor is greater than the voltage that is applied to the motor, then the mechanical energy of the motor is returned to the power supply and the V M voltage surges. The AVS feature works to prevent this voltage surge on VM and can be enabled by setting AVS_EN to 1b. AVS can be disabled by setting AVS_EN to 0b. When AVS is disabled, the deceleration rate is configured through CL_DEC.

6.3.16 Active Braking

Decelerating the motor quickly requires the motor mechanical energy to be extracted from the rotor in a fast and controlled manner. However, the supply voltage (VM) increases if the motor mechanical energy is returned to the power supply during the deceleration process. MCF8316D is capable of decelerating the motor quickly without pumping energy back into the supply voltage by using a novel technique called active braking. ACTIVE_BRAKE_EN should be set to 1b to enable active braking and prevent DC bus voltage (VM) spike during fast motor deceleration. Active braking can also be used during reverse drive (see Reverse Drive) or motor stop (see Active Spin-Down) to reduce the motor speed quickly without DC bus voltage (VM) spike. The maximum limit on the current sourced from the DC bus (i dc_ref) during active braking can be configured using ACTIVE_BRAKE_CURRENT_LIMIT. The D-axis current reference (i d_ref) is generated from the error between DC bus current limit (i dc_ref) and the estimated DC bus current (i dc) using a PI controller as shown in Figure 6-50 . The gain constants of PI controller can be configured using ACTIVE_BRAKE_KP and ACTIVE_BRAKE_KI. During active braking, the DC bus current limit (i dc_ref) starts from zero and linearly increases to ACTIVE_BRAKE_CURRENT_LIMIT with current slew rate as defined by ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATE. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: MCF8316D

idc_ref idc PI id_ref ACTIVE_BRAKE_KP ACTIVE_BRAKE_KI Figure 6-50. Active Braking Current Control Loop for id_ref ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY sets the minimum difference between the initial and target speed above which active braking will be entered. For example, consider ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY is set to 10%; if the initial speed is 100% and target speed is set to 95%, MCF8316D uses AVS instead of active braking to reach 95% speed since the difference in commanded speed change (5%) is less than ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY (10%). ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT sets the difference between the current and target speed below which active braking will be exited. For example, consider ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT is set to 5%; if the initial motor speed is 100% and target speed is set to 10%, MCF8316D uses active braking to reduce the motor speed to 15%; upon reaching 15% speed, MCF8316D exits active braking and uses AVS to decelerate the motor speed to 10%. ACTIVE_BRAKE_MOD_INDEX_LIMIT sets the modulation index below which active braking will be used. For example, consider ACTIVE_BRAKE_MOD_INDEX_LIMIT is set to 50%, ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY is set to 5%, ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT is set to 2.5%. If the initial motor speed is at 70% (corresponding modulation index is 90%) and target speed is 40% (corresponding modulation index is 60%), MCF8316D uses AVS to decelerate the motor till target speed of 40% since the modulation index (60%) corresponding to final speed is higher than ACTIVE_BRAKE_MOD_INDEX_LIMIT of 50%. In the same case, if final speed command is 10% (corresponding modulation index is 30%), MCF8316D uses AVS till 30% speed (corresponding modulation index is 50%), switches to active braking from 30% to 15% speed (final speed of 10% + ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT of 5%) and uses AVS again from 15% to 10% speed to complete the active braking. TI recommends starting active braking tuning with ACTIVE_BRAKE_MOD_INDEX_LIMIT set to 100%; if there is a DC bus voltage (VM) spike observed during active braking, reduce ACTIVE_BRAKE_MOD_INDEX_LIMIT in steps so as to eliminate this voltage spike. If ACTIVE_BRAKE_MOD_INDEX_LIMIT is set to 0%, MCF8316D decelerates in AVS (even when ACTIVE_BRAKE_EN is set to 1b) in the forward direction; in reverse direction (during direction change), ACTIVE_BRAKE_MOD_INDEX_LIMIT is not applicable and therefore MCF8316D decelerates in active braking. Note 1. ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY, ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT and ACTIVE_BRAKE_MOD_INDEX_LIMIT are applicable only during deceleration in forward direction and not used during direction change. 2. ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY should be set higher than ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXIT for active braking operation. 3. During active (or closed loop) braking, Iq_ref is clamped to -ILIMIT. This (Iq_ref being clamped to -ILIMIT) may result in the speed PI loop getting saturated and SPEED_LOOP_SATURATION bit getting set to 1b during deceleration. This bit is automatically set to 0b once the deceleration is completed and the speed PI loop is out of saturation. Hence, speed loop saturation fault should be ignored during deceleration. 4. Active braking is available only in speed control mode. 5. Active braking is not available (even when ACTIVE_BRAKE_EN = 1b) when (bus) power limit feature (BUS_POWER_LIMIT_ENABLE = 1b) is enabled.

6.3.17 Output PWM Switching Frequency

MCF8316D provides the option to configure the output PWM switching frequency of the MOSFETs through PWM_FREQ_OUT. PWM_FREQ_OUT has range of 10-60kHz. In order to select optimal output PWM switching MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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frequency, user has to make tradeoff between the current ripple and the switching losses. Generally, motors having lower L/R ratio require higher PWM switching frequency to reduce current ripple.

6.3.18 PWM Dithering

MCF8316D provides the option of PWM dithering to reduce the EMI generated by MOSFET switching - when enabled, the PWM switching frequency is varied continuously (within a user configured frequency range) around the PWM_FREQ_OUT setting to spread the EMI energy across the frequency spectrum and reduce the EMI peak values. The user configured frequency range for PWM dithering is set by PWM_DITHER_DEPTH; setting PWM_DITHER_DEPTH to 0x0 disables PWM dithering. PWM_DITHER_DEPTH provides ±5%, ±7.5% and ±10% frequency spread options. When PWM_FREQ_OUT is set to 25kHz and PWM_DITHER_DEPTH is set to ±10%, the PWM switching frequency applied to the MOSFETs continuously varies between 22.5kHz (25kHz-10%) and 27.5kHz (25kHz+10%), thereby reducing the EMI peaks at multiples of 25kHz. PWM dithering is available in two modes - random or triangular (configured by PWM_DITHER_MODE). In random dithering, the PWM switching frequency is continuously varied randomly within the range set by PWM_FREQ_OUT and PWM_DITHER_DEPTH. In triangular dithering, the PWM switching frequency is varied at user configured slew rate (configured by PWM_DITHER_STEP) as shown in Figure 6-51. PWM switching frequency t PWM_FREQ_OUT PWM_FREQ_OUT_MAX PWM_FREQ_OUT_MIN PWM_FREQ_OUT_MAX = PWM_FREQ_OUT x (1 + (PWM_DITHER_DEPTH/100)) PWM_FREQ_OUT_MIN = PWM_FREQ_OUT x (1 – (PWM_DITHER_DEPTH/100)) PWM_DITHER_SLEW Figure 6-51. Triangular PWM Dithering The PWM switching frequency slew rate (PWM_DITHER_SLEW in Figure 6-51) is set as shown in Equation 10. PWM_DITHER_SLEW (kHz/s) = PWM_DITHER_STEP * SLEW_SCALING FACTOR (10) SLEW_SCALING FACTOR varies with PWM switching frequency as listed in Table 6-5. Table 6-5. SLEW_SCALING FACTOR vs PWM switching frequency PWM switching frequency (kHz) SLEW_SCALING FACTOR 10 1 15 2.25 20 2 25 3.125 30 4.5 35 3.0625 40 4 45 5.0625 50 6.25 55 7.5625 60 9 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: MCF8316D

6.3.19 PWM Modulation Schemes

The MCF8316D supports two different modulation schemes, namely, continuous and discontinuous space vector PWM modulation schemes. In continuous PWM modulation, all the three phases switch all the time as per the defined switching frequency. In discontinuous PWM modulation, one of the phases is clamped to ground for 120 o electrical period, and the other two phases are pulse width modulated. The modulation scheme is configured using PWM_MODE. Figure 6-52 shows the modulated average phase voltages for different modulation schemes. OUTA - OUTB OUTA OUTB OUTC Voltage from Phase to GND - Con nuous PWM modula on Sinusoidal voltage from phase to phase Voltage from Phase to GND - Discon nuous PWM modula on OUTB - OUTC OUTC - OUTA OUTA OUTB OUTC Figure 6-52. Continuous and Discontinuous PWM Modulation Phase Voltages Continuous modulation helps in reducing current ripple for motors having low inductance but it results in higher switching losses because all three phases are switching. Discontinuous modulation has lower switching losses due to only two phases switching at a time, but higher current ripple.

6.3.20 Dead Time Compensation

Dead time is inserted between the switching instants of high-side and low-side MOSFETs in a half-bridge leg to avoid shoot-through condition. Due to dead time insertion, the expected voltage and applied voltage at the phase node differ based on the phase current direction. The phase node voltage distortion introduces undesired distortion in the phase current causing audible noise. MCF8316D integrates a proprietary dead time compensation technique to remove this phase current distortion and greatly reduce the audible noise, thereby significantly improving the acoustic performance of the FOC in MCF8316D. This dead time compensation can be enabled or disabled by configuring DEADTIME_COMP_EN. Even when DEADTIME_COMP_EN is set to 1b (compensation enabled), dead time compensation is disabled when motor electrical frequency exceeds 108Hz and re-enabled when motor electrical frequency drops below 102Hz.

6.3.21 Motor Stop Options

The MCF8316D provides different options for stopping the motor which can be configured by MTR_STOP.

6.3.21.1 Coast (Hi-Z) Mode

Coast (Hi-Z) mode is configured by setting MTR_STOP to 000b. When motor stop command is received, the MCF8316D will transition into a high impedance (Hi-Z) state by turning off all MOSFETs. When the MCF8316D transitions from driving the motor into a Hi-Z state, the inductive current in the motor windings continues to flow and the energy returns to the power supply through the body diodes in the MOSFET output stage (see example Figure 6-53). MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Driving State High-Impedance State HSA LSA LSB HSC LSC HSB HSA LSA LSB HSC LSC HSB Figure 6-53. Coast (Hi-Z) Mode In this example, current is applied to the motor through the high-side phase-A MOSFET (HSA) , high-side phase- B MOSFET(HSB) and returned through the low-side phase-C MOSFET (LSC). When motor stop command is received all 6 MOSFETs transition to Hi-Z state and the inductive energy returns to supply through body diodes of MOSFETs LSA, LSB and HSC.

6.3.21.2 Recirculation Mode

Recirculation mode is configured by setting MTR_STOP to 001b. In order to prevent the inductive energy from returning to DC input supply during motor stop, the MCF8316D allows current to circulate within the MOSFETs by selectively turning OFF some of the active (ON) MOSFETs for a certain time (auto calculated recirculation time to allow the inductive current to decay to zero) before transitioning into Hi-Z by turning OFF the remaining MOSFETs. Depending on the phase voltage pattern at the time of receiving the stop command, either low-side (see Figure 6-54) or high-side recirculation (see Figure 6-55) will be used to stop the motor without sending the inductive energy back to the DC input supply. MVM HSA LSA LSB HSC LSC MVM HSA LSA HSB LSB HSC LSC Driving State Low-Side Recirculaon Mode HSB Figure 6-54. Low-Side Recirculation www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: MCF8316D

Driving State High-Side Recircula on Mode HSB Figure 6-55. High-Side Recirculation Note Recirculation stop will not be available when the motor is in open loop state or active braking state or during flux weakening or when lead angle is non-zero; in such cases, the motor stop mode is set by LOW_SPEED_RECIRC_BRAKE_EN.

6.3.21.3 Low-Side Braking

Low-side braking mode is configured by setting MTR_STOP to 010b. When a motor stop command is received, the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all low-side MOSFETs ON (see example Figure 6-56) for a time configured by MTR_STOP_BRK_TIME. If the motor speed is below BRAKE_SPEED_THRESHOLD prior to receiving stop command, then the MCF8316D transitions directly into the brake state. After applying the brake for MTR_STOP_BRK_TIME, the MCF8316D transitions into the Hi-Z state by turning OFF all MOSFETs. MVM MVM Driving State Low-Side Braking HSA LSA LSB HSC LSC HSB HSA LSA LSB HSC LSC HSB Figure 6-56. Low-Side Braking The MCF8316D can also enter low-side braking through BRAKE pin input. When BRAKE pin is pulled to HIGH state, the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all low-side MOSFETs ON. In this case, MCF8316D stays in low-side brake state till BRAKE pin changes to LOW state.

6.3.21.4 High-Side Braking

High-side braking mode is configured by setting MTR_STOP to 011b. When a motor stop command is received, the output speed is reduced to a value defined by BRAKE_SPEED_THRESHOLD prior to turning all high-side MOSFETs ON (see example Figure 6-57) for a time configured by MTR_STOP_BRK_TIME. If the motor speed is below BRAKE_SPEED_THRESHOLD prior to receiving stop command, then the MCF8316D transitions directly into the brake state. After applying the brake for MTR_STOP_BRK_TIME, the MCF8316D transitions into Hi-Z state by turning OFF all MOSFETs. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Driving State High-Side Braking HSA LSA LSB HSC LSC HSB HSA LSA LSB HSC LSC HSB Figure 6-57. High-Side Braking

6.3.21.5 Active Spin-Down

Active spin down mode is configured by setting MTR_STOP to 100b. When a motor stop command is received, the MCF8316D reduces SPEED_REF to ACT_SPIN_THR and then transitions to Hi-Z state by turning all MOSFETs OFF. The advantage of this mode is that by reducing SPEED_REF, the motor is decelerated to lower speed thereby reducing the phase currents before entering Hi-Z. Now, when the motor transitions into Hi-Z state, the energy transfer to the power supply is reduced. The threshold ACT_SPIN_THR needs to configured high enough for MCF8316D to not lose synchronization with the motor.

6.3.22 Align Braking

Align braking is available only when BRAKE_PIN_MODE is set to 1b. Align braking is used to stop the motor at a user configured angle when a brake command is received either through a logic High signal on the BRAKE pin or by setting BRAKE_INPUT to 01b. In this mode, on receiving the brake command, MCF8316D reduces the motor speed to a value defined by BRAKE_SPEED_THRSHOLD before bringing the motor to an "aligned stop" by continuously injecting a DC current through a particular phase pattern. The phase pattern during align brake is generated based on the angle at which align needs to be performed - this angle can be configured either as the last commutation angle when BRAKE_SPEED_THRESHOLD is reached (ALIGN_BRAKE_ANGLE_SEL = 0b) or set directly using ALIGN_ANGLE (when ALIGN_BRAKE_ANGLE_SEL = 1b). The current limit during align braking is configured through ALIGN_OR_SLOW_CURRENT_ILIMIT.

6.3.23 FG Configuration

The MCF8316D provides information about the motor speed through the Frequency Generate (FG) pin. In MCF8316D, the FG pin output is configured through FG_CONFIG. When FG_CONFIG is configured to 0b, the FG output is active as long as the MCF8316D is driving the motor. When FG_CONFIG is configured to 1b, the MCF8316D provides an FG output until the motor back-EMF falls below FG_BEMF_THR.

6.3.23.1 FG Output Frequency

The FG output frequency can be configured by FG_DIV. Many applications require the FG output to provide a pulse for every mechanical rotation of the motor. Different FG_DIV configurations can accomplish this for 2-pole up to 30-pole motors. FG_DIV = 0000b provides an FG pulse every 120 o (electrical) for backward compatibility with legacy 3-Hall sensored solutions. Figure 6-58 shows the FG output when MCF8316D has been configured to provide FG pulses every 120 o (elec.), once every electrical cycle (2 poles), once every two electrical cycle (4 poles), once every three electrical cycles (6 poles), once every four electrical cycles (8 poles), and so on. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: MCF8316D

FG_DIV = 0001b (Elec cycle) FG_DIV = 0011b (Elec cycle/3) FG_DIV = 0100b (Elec cycle/4) FG_DIV = 0010b (Elec cycle/2) FG_DIV = 0000b (Elec cycle*3) Figure 6-58. FG Frequency Divider

6.3.23.2 FG during Open and Closed Loop States

During closed loop operation, the driving speed (FG output frequency) and the actual motor speed are synchronized. During open-loop operation, however, FG may not reflect the actual motor speed. The MCF8316D provides three options for controlling the FG output during open loop, as shown in Figure 6-59. The selection of these options is configured through FG_SEL. If FG_SEL is set to,

• 00b: When in open loop, the FG output is based on the driving frequency.
• 01b: When in open loop, the FG output will be driven high.
• 10b: The FG output will reflect the driving frequency during open loop operation in the first motor start-up cycle after power-on, sleep/standby; FG will be held high during open loop operation in subsequent start-up cycles. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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First start-up after power-up or wake-up from sleep Any subsequent start-up without power recycle or entering sleep state Figure 6-59. FG Behavior During Open Loop

6.3.23.3 FG during Fault and Idle States

MCF8316D provides the option of configuring FG output during fault and idle (motor stopped due to zero speed command) states. FG output during fault state is configured by FG_FAULT_CONFIG and FG output during idle state is configured by FG_IDLE_CONFIG - FG can be configured as a low or high signal during fault and can also be configured as a low or high signal during idle state. This allows the use of FG signal to uniquely determine the motor operating condition (fault, idle, spinning). For example, FG output during fault can be configured as a low signal and FG output during idle state can be configured as a high signal and FG during motor spinning can be configured to be at mechanical speed - a low FG output indicates MCF8316D encountered a fault condition, a high FG output indicates motor is in idle state and a FG signal at 50% duty indicates motor spinning at a speed equal to FG frequency. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: MCF8316D

Motor is considered to be in stationary/idle state when back-EMF sensed at OUTx is less than STAT_DETECT_THR. STAT_DETECT_THR should be set sufficiently high to avoid spurious FG toggles due to noise in OUTx pins when motor is in stationary/idle state.

6.3.24 Protections

The MCF8316D is protected from a host of fault events including motor lock, VM undervoltage, AVDD undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table 6-6 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults. Note 1. Actionable faults (latched or retry) are always reported on nFAULT pin (as logic low). 2. Actionable faults (latched or retry) are reported on ALARM pin (as logic high) when ALARM_PIN_EN is set to 1b. 3. Report only faults are reported on nFAULT (as logic low) only when ALARM_PIN_EN is set to 0b. When ALARM_PIN_EN is set to 1b, report only faults are reported only on ALARM pin (as logic high) while nFAULT stays high (external or internal pull-up). 4. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses. 5. Recovery refers only to state of FETs (Hi-Z or active) after the fault condition is removed. Automatic indicates that the device automatically recovers (and FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) to make the FETs active again. 6. Actionable (latched or retry) faults can take up to 200-ms after fault response (FETs in Hi-Z) to be reported on nFAULT pin (as logic low), ALARM pin (as logic high) and fault status registers. 7. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared. 8. The fault state is latched when the cumulative number of automatic retry attempts (AUTO_RETRY_TIMES ≠ 000b) for all faults configured in automatic retry mode is reached. In this case, it is necessary to write 1b to CLR_FLT_RETRY_COUNT bit when writing 1b to CLR_FLT bit in ALGO_CTRL1 register to reset the retry counter to zero while clearing the latched fault state. Table 6-6. Fault Action and Response FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY VM undervoltage VVM < VUVLO (falling) — — Hi-Z Disabled Automatic: VVM > VUVLO (rising) AVDD undervoltage VAVDD < VAVDD_UV (falling) — — Hi-Z Disabled Automatic: VAVDD > VAVDD_UV (rising) Buck undervoltage (BUCK_UV) VFB_BK < VBK_UV (falling) — — Active/Hi-Z Active/Disabled Automatic: VFB_BK > VBK_UV (rising) Charge pump undervoltage (VCP_UV) VCP < VCPUV (falling) — nFAULT and GATE_DRIVER_FA ULT_STATUS register Hi-Z Active Automatic: VVCP > VCPUV (rising) Over Voltage Protection (OVP) VVM > VOVP (rising) OVP_EN = 0b None Active Active No action OVP_EN = 1b nFAULT and GATE_DRIVER_FA ULT_STATUS register Hi-Z Active Automatic: VVM < VOVP (falling) Over Current Protection (OCP) IPHASE > IOCP OCP_MODE = 00b nFAULT and GATE_DRIVER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT OCP_MODE = 01b nFAULT and GATE_DRIVER_FA ULT_STATUS register Hi-Z Active Retry: tRETRY MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-6. Fault Action and Response (continued) FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY Buck Overcurrent Protection (BUCK_OCP) IBK > IBK_OCP — — Hi-Z Disabled Automatic Motor Lock (MTR_LCK ) Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 000b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT MTR_LCK_MODE = 001b nFAULT and CONTROLLER_FA ULT_STATUS register Low- side brake Active Latched: CLR_FLT MTR_LCK_MODE = 010b nFAULT and CONTROLLER_FA ULT_STATUS register High- side brake Active Latched: CLR_FLT MTR_LCK_MODE = 011b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Retry: tLCK_RETRY MTR_LCK_MODE = 100b nFAULT and CONTROLLER_FA ULT_STATUS register Low- side brake Active Retry: tLCK_RETRY MTR_LCK_MODE = 101b nFAULT and CONTROLLER_FA ULT_STATUS register High- side brake Active Retry: tLCK_RETRY MTR_LCK_MODE = 110b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action MTR_LCK_MODE = 111b None Active Active No action Hardware Lock- Detection Current Limit (HW_LOCK_LIMIT) VSOX > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MOD E = 000b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT HW_LOCK_ILIMIT_MOD E = 001b nFAULT and CONTROLLER_FA ULT_STATUS register Low-side brake Active Latched: CLR_FLT HW_LOCK_ILIMIT_MOD E = 010b nFAULT and CONTROLLER_FA ULT_STATUS register High-side brake Active Latched: CLR_FLT HW_LOCK_ILIMIT_MOD E = 011b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Retry: tLCK_RETRY HW_LOCK_ILIMIT_MOD E = 100b nFAULT and CONTROLLER_FA ULT_STATUS register Low-side brake Active Retry: tLCK_RETRY HW_LOCK_ILIMIT_MOD E = 101b nFAULT and CONTROLLER_FA ULT_STATUS register High-side brake Active Retry: tLCK_RETRY HW_LOCK_ILIMIT_MOD E= 110b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action HW_LOCK_ILIMIT_MOD E = 111b None Active Active No action www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: MCF8316D

Table 6-6. Fault Action and Response (continued) FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY Software Lock- Detection Current Limit (LOCK_LIMIT) VSOX > LOCK_ILIMIT LOCK_ILIMIT_MODE = 000b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT LOCK_ILIMIT_MODE = 001b nFAULT and CONTROLLER_FA ULT_STATUS register Low-side brake Active Latched: CLR_FLT LOCK_ILIMIT_MODE = 010b nFAULT and CONTROLLER_FA ULT_STATUS register High-side brake Active Latched: CLR_FLT LOCK_ILIMIT_MODE = 011b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Retry: tLCK_RETRY LOCK_ILIMIT_MODE = 100b nFAULT and CONTROLLER_FA ULT_STATUS register Low-side brake Active Retry: tLCK_RETRY LOCK_ILIMIT_MODE = 101b nFAULT and CONTROLLER_FA ULT_STATUS register High-side brake Active Retry: tLCK_RETRY LOCK_ILIMIT_MODE= 110b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action LOCK_ILIMIT_MODE = 111b None Active Active No action IPD Timeout Fault (IPD_T1_FAULT and IPD_T2_FAULT) IPD TIME > 500ms (approx.), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_E N = 0b — Active Active No action IPD_TIMEOUT_FAULT_E N = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Retry: tLCK_RETRY IPD Frequency Fault (IPD_FREQ_FAULT IPD pulse before the current decay in previous IPD pulse IPD_FREQ_FAULT_EN = 0b — Active Active No action IPD_FREQ_FAULT_EN = nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Retry: tLCK_RETRY MPET IPD Fault (MPET_IPD_FAULT Same as IPD Timeout Fault during MPET R, L measurement nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT MPET Back-EMF Fault (MPET_BEMF_FA ULT) Motor Back EMF < STAT_DETECT_THR during MPET Ke and mechanical parameters measurement nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT Maximum VM (overvoltage) fault VVM > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT MAX_VM_MODE = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Automatic: (VVM < MAX_VM_MOTOR - VOLTAGE_HYSTERESIS)V Minimum VM (undervoltage) fault VVM < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT MIN_VM_MODE = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Automatic: (VVM > MIN_VM_MOTOR + VOLTAGE_HYSTERESIS)V External Watchdog Watchdog tickle does not arrive before configured time interval when EXT_WDT_EN =1b. Refer Section 6.5.5 EXT_WDT_FAULT_MOD E = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action EXT_WDT_FAULT_MOD E = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-6. Fault Action and Response (continued) FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY EEPROM Fault Indicates EEPROM contents error/mismatch; content evaluation happens whenever a EEPROM read is issued EEP_FAULT_MODE = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT EEP_FAULT_MODE = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action I2C CRC Fault Indicates error in I2C transaction as a CRC mismatch CRC_ERR_MODE = 0b nFAULT and CONTROLLER_FA ULT_STATUS register Hi-Z Active Latched: CLR_FLT CRC_ERR_MODE = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_E N = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation Speed Loop Saturation Indication of speed loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_E N = 1b nFAULT and CONTROLLER_FA ULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation Thermal warning (OTW) TJ > TOTW OTW_REP = 0b — Active Active No action OTW_REP = 1b nFAULT and GATE_DRIVER_FA ULT_STATUS register Active Active No action FET thermal shutdown (TSD_FET) TJ > TTSD_FET — nFAULT and GATE_DRIVER_FA ULT_STATUS register Hi-Z Active Automatic: TJ < TTSD_FET – TTSD_FET_HYS www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: MCF8316D

6.3.24.1 VM Supply Undervoltage Lockout

If at any time the input supply voltage on the VM pin falls lower than the V UVLO threshold (VM UVLO falling threshold), all the integrated FETs, driver charge-pump and digital logic are disabled as shown in Figure 6-60. MCF8316D goes into reset state whenever VM UVLO event occurs. VUVLO (min) falling VUVLO (max) falling VUVLO (max) rising VUVLO (min) rising VVM DEVICE ON DEVICE OFF DEVICE ON Time Figure 6-60. VM Supply Undervoltage Lockout

6.3.24.2 AVDD Undervoltage Lockout (AVDD_UV)

If at any time the voltage on the AVDD pin falls lower than the V AVDD_UV threshold, all the integrated FETs, driver charge-pump and digital logic controller are disabled. Since internal circuitry in MCF8316D is powered through the AVDD regulator, MCF8316D goes into reset state whenever AVDD UV event occurs.

6.3.24.3 BUCK Under Voltage Lockout (BUCK_UV)

If at any time the voltage on the FB_BK pin falls lower than the V BK_UVLO threshold, a buck UV fault is recognized - MCF8316D continues to attempt regulating the FB_BK voltage to set value. Since internal circuitry in MCF8316D is powered through the buck regulator, MCF8316D may go into reset state if FB_BK voltage drops low enough to trigger UV on the internal circuits.

6.3.24.4 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin (charge pump) falls lower than the V CPUV threshold, all the integrated FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and VCP_UV bits are set to 1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the VCP undervoltage condition clears. The VCP_UV bit stays set until cleared through the CLR_FLT bit.

6.3.24.5 Overvoltage Protection (OVP)

If at any time input supply voltage on the VM pins rises higher than V OVP, all the integrated FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to 1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit. Setting the OVP_EN to 0b disables this protection feature. The OVP threshold can be set to 22-V or 34-V based on the OVP_SEL bit. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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VOVP (min) falling VOVP (max) falling VOVP (max) rising VOVP (min) rising VVM nFAULT DEVICE ON DEVICE OFF DEVICE ON Time Figure 6-61. Over Voltage Protection

6.3.24.6 Overcurrent Protection (OCP)

MOSFET overcurrent event is sensed by monitoring the current flowing through the FETs. If the current across a FET exceeds the IOCP threshold for longer than the deglitch time tOCP, an OCP event is recognized and action is taken according to OCP_MODE. The IOCP threshold is set through the OCP_LVL, tOCP is set through OCP_DEG and the OCP_MODE can be configured in two different modes: latched shutdown and automatic retry.

6.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)

When an OCP event happens in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the OCP condition clears and a clear fault command is issued through the CLR_FLT bit. IOCP tOCP nFAULT Time IOUTx nFAULT Pulled High Fault Condition nFAULT Released Peak Current due to deglitch time Clear Fault Figure 6-62. Overcurrent Protection - Latched Shutdown Mode

6.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)

When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the fault status registers. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: MCF8316D

Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t RETRY (TRETRY) time elapses. The DRIVER_FAULT, OCP and corresponding FET's OCP bits are reset to 0b after the tRETRY period expires. IOCP tOCP nFAULT Time IOUTx nFAULT Pulled High Fault Condition nFAULT Released Peak Current due to deglitch time tRETRY Figure 6-63. Overcurrent Protection - Automatic Retry Mode

6.3.24.7 Buck Overcurrent Protection

The buck overcurrent event is sensed by monitoring the current flowing through high-side MOSFET of the buck regulator. If the current through the high-side MOSFET exceeds the I BK_OCP threshold for a time longer than the deglitch time (t OCP), a buck OCP event is recognized and the buck regulator MOSFETs are disabled (Hi-Z). MCF8316D goes into reset state whenever buck OCP event occurs, since the internal circuitry in MCF8316D is powered from the buck regulator output.

6.3.24.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)

The hardware lock detection current limit function provides a configurable threshold for limiting the current to prevent damage to the system. The MCF8316D continuously motor phase currents are using comparators. If at any time, any phase current exceeds HW_LOCK_ILIMIT threshold for a time longer than t HW_LOCK_ILIMIT, a HW_LOCK_ILIMIT event is recognized and action is taken according to the HW_LOCK_ILIMIT_MODE. The current threshold is set by HW_LOCK_ILIMIT and the deglitch time, t HW_LCK_ILIMIT is set by HW_LOCK_ILIMIT_DEG. HW_LOCK_ILIMIT_MODE can be set in four different modes: HW_LOCK_ILIMIT latched shutdown, HW_LOCK_ILIMIT automatic retry, HW_LOCK_ILIMIT report only, and HW_LOCK_ILIMIT disabled.

6.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown

When a HW_LOCK_ILIMIT event happens in this mode, the status of MOSFET will be configured by HW_LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during HW_LOCK_ILIMIT:

• HW_LOCK_ILIMIT_MODE = 000b: All MOSFETs are turned OFF.
• HW_LOCK_ILIMIT_MODE = 001b: All low-side MOSFETs are turned ON.
• HW_LOCK_ILIMIT_MODE = 010b: All high-side MOSFETs are turned ON. The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the HW_LOCK_ILIMIT condition clears and a clear fault command is issued through the CLR_FLT bit. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery

When a HW_LOCK_ILIMIT event happens in this mode, the status of MOSFET will be configured by HW_LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFET during HW_LOCK_ILIMIT:

• HW_LOCK_ILIMIT_MODE = 011b: All MOSFETs are turned OFF.
• HW_LOCK_ILIMIT_MODE = 100b: All low-side MOSFETs are turned ON
• HW_LOCK_ILIMIT_MODE = 101b: All high-side MOSFETs are turned ON The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t LCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT and HW_LOCK_ILIMIT bits are reset to 0b after the tLCK_RETRY period expires.

6.3.24.8.3 HW_LOCK_ILIMIT Report Only

No protective action is taken when a HW_ LOCK_ILIMIT event happens in this mode (HW_LOCK_ILIMIT_MODE = 110b). The hardware lock detection current limit event is reported by setting the CONTROLLER_FAULT and HW_LOCK_ILIMIT bits to 1b in the fault status registers. The gate drivers continue to operate. The external controller manages this condition by acting appropriately. The reporting clears when the HW_LOCK_ILIMIT condition clears and a clear fault command is issued through the CLR_FLT bit.

6.3.24.8.4 HW_LOCK_ILIMIT Disabled

No action is taken when a HW_LOCK_ILIMIT event happens in this mode (HW_LOCK_ILIMIT_MODE = 111b).

6.3.24.9 Lock Detection Current Limit (LOCK_ILIMIT)

The lock detection current limit function provides a configurable threshold for limiting the current to prevent damage to the system. The MCF8316D continuously monitors the motor phase currents through the ADC. If at any time, any phase current exceeds LOCK_ILIMIT for a time longer than t LCK_ILIMIT, a LOCK_ILIMIT event is recognized and action is taken according to LOCK_ILIMIT_MODE. The current threshold is set by LOCK_ILIMIT and the deglitch time, t LCK_ILIMIT is set by LOCK_ILIMIT_DEG. LOCK_ILIMIT_MODE can be set in four different modes: LOCK_ILIMIT latched shutdown, LOCK_ILIMIT automatic retry, LOCK_ILIMIT report only and LOCK_ILIMIT disabled.

6.3.24.9.1 LOCK_ILIMIT Latched Shutdown

When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:

• LOCK_ILIMIT_MODE = 000b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 001b: All low-side MOSFETs are turned ON.
• LOCK_ILIMIT_MODE = 010b: All high-side MOSFETs are turned ON. The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the LOCK_ILIMIT condition clears and a clear fault command is issued through the CLR_FLT bit.

6.3.24.9.2 LOCK_ILIMIT Automatic Recovery

When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:

• LOCK_ILIMIT_MODE = 011b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 100b: All low-side MOSFETs are turned ON
• LOCK_ILIMIT_MODE = 101b: All high-side MOSFETs are turned ON The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the t LCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT and LOCK_ILIMIT bits are reset to 0b after the tLCK_RETRY period expires. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: MCF8316D

6.3.24.9.3 LOCK_ILIMIT Report Only

No protective action is taken when a LOCK_ILIMIT event happens in this mode (LOCK_ILIMIT_MODE = 110b). The lock detection current limit event is reported by setting the CONTROLLER_FAULT and LOCK_ILIMIT bits to 1b in the fault status registers. The gate drivers continue to operate. The external controller manages this condition by acting appropriately. The reporting clears when the LOCK_ILIMIT condition clears and a clear fault command is issued through the CLR_FLT bit.

6.3.24.9.4 LOCK_ILIMIT Disabled

No action is taken when a LOCK_ILIMIT event happens in this mode (LOCK_ILIMIT_MODE = 111b).

6.3.24.10 Motor Lock Detection

The MCF8316D provides different lock detect mechanisms to determine if the motor is in a locked state. Multiple detection mechanisms work together to ensure the lock condition is detected quickly and reliably. In addition to detecting if there is a locked motor condition, the MCF8316D can also identify and take action if there is no motor connected to the system. Each of the lock detect mechanisms and the no-motor detection can be disabled by their respective register bits (LOCK1/2/3_EN).

6.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)

MCF8316D monitors the speed continuously and at any time the speed exceeds LOCK_ABN_SPEED, an ABN_SPEED lock event is recognized and action is taken according to the MTR_LCK_MODE. The threshold is set through the LOCK_ABN_SPEED register. ABN_SPEED lock can be enabled/disabled by LOCK1_EN.

6.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)

MCF8316D estimates back-EMF in order to run motor optimally in closed loop. This estimated back-EMF is compared against the expected back-EMF calculated using the estimated speed and the BEMF constant. Whenever motor is stalled the estimated back-EMF is inaccurate due to lower back-EMF at low speed. When the difference between estimated and expected back-EMF exceeds ABNORMAL_BEMF_THR for ABNORMAL_BEMF_PERSISTENT_TIME, an abnormal BEMF fault is triggered and action is taken according to the MTR_LCK_MODE. ABN_BEMF lock can be enabled/disabled by LOCK2_EN.

6.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)

The MCF8316D continuously monitors phase currents on all three phases; if any phase current stays below NO_MTR_THR for 500ms, a NO_MTR event is recognized. The response to the NO_MTR event is configured through MTR_LCK_MODE. NO_MTR lock can be enabled/disabled by LOCK3_EN. Note

• No motor fault is disabled when motor speed is < 2Hz.
• No motor fault is unavailable (even when enabled) during motor start-up (IPD or align or double align) state - it is available (when enabled) in open and closed loop states
• No motor fault detection during closed loop can be disabled by setting NO_MTR_FLT_ CLOSEDLOOP _DIS to 1b.

6.3.24.11 Motor Lock (MTR_LCK)

The MCF8316D continuously checks for different motor lock conditions (see Motor Lock Detection) during motor operation. When one of the enabled lock condition happens, a MTR_LCK event is recognized and action is taken according to the MTR_LCK_MODE. All locks can be enabled or disabled individually and retry times can be configured through LCK_RETRY. MTR_LCK_MODE bit can operate in four different modes: MTR_LCK latched shutdown, MTR_LCK automatic retry, MTR_LCK report only and MTR_LCK disabled. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.3.24.11.1 MTR_LCK Latched Shutdown

When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE and nFAULT is driven low. Status of MOSFETs during MTR_LCK:

• MTR_LCK_MODE = 000b: All MOSFETs are turned OFF.
• MTR_LCK_MODE = 001b: All low-side MOSFETs are turned ON.
• MTR_LCK_MODE = 010b: All high-side MOSFETs are turned ON. The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the MTR_LCK condition clears and a clear fault command is issued through the CLR_FLT bit.

6.3.24.11.2 MTR_LCK Automatic Recovery

When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE and nFAULT is driven low. Status of MOSFETs during MTR_LCK:

• MTR_LCK_MODE = 011b: All MOSFETs are turned OFF.
• MTR_LCK_MODE = 100b: All low-side MOSFETs are turned ON.
• MTR_LCK_MODE = 101b: All high-side MOSFETs are turned ON. The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tLCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are reset to 0b after the tLCK_RETRY period expires.

6.3.24.11.3 MTR_LCK Report Only

No protective action is taken when a MTR_LCK event happens in this mode (MTR_LCK_MODE = 110b). The motor lock event is reported by setting the CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits to 1b in the fault status registers. The gate drivers continue to operate. The external controller manages this condition by acting appropriately. The reporting clears when the MTR_LCK condition clears and a clear fault command is issued through the CLR_FLT bit.

6.3.24.11.4 MTR_LCK Disabled

No action is taken when a MTR_LCK event happens in this mode (MTR_LCK_MODE = 111b).

6.3.24.12 EEPROM Fault

MCF8316D provides an EEPROM fault detection feature to prevent device operation when there is EEPROM data mismatch due to an interrupted EEPROM write (UVLO during EEPROM write), EEPROM aging etc., MCF8316D implements a CRC and parity check whenever an EEPROM read command is issued - if there is a CRC or parity mismatch, an EEPROM fault is recognized and action taken according to EEP_FAULT_MODE. If EEP_FAULT_MODE is set to 0b, nFAULT is pulled low, the FETs are in Hi-Z and the CONTROLLER_FAULT and EEPROM_ERR_STATUS bits are set to 1b until the fault condition is cleared by writing 1b to CLR_FLT. If EEP_FAULT_MODE is set to 1b, this fault is reported on nFAULT pin and CONTROLLER_FAULT, EEPROM_ERR_STATUS bits are set to 1b but the device operation (FETs) continues normally. The fault reporting can be cleared (nFAULT pin is released, CONTROLLER_FAULT, EEPROM_ERR_STATUS set to 0b) by writing 1b to CLR_FLT. Note

• An EEPROM read command is internally issued by the device at every power-up/wake-up to load the configurations from EEPROM into the shadow/RAM registers.
• A successful EEPROM write can fix EEPROM data mismatch. When an EEPROM write is successfully completed, MCF8316D automatically updates the internal CRC for the new EEPROM values - this updated CRC will be used during subsequent EEPROM read commands to check for EEPROM data mismatch.
• An EEPROM write can happen even when the device is in fault state. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: MCF8316D

6.3.24.13 I2C CRC Fault

MCF8316D provides I 2C CRC fault detection feature to detect errors in an I 2C transaction. MCF8316D implements a CRC check on the entire I 2C packet when I 2C CRC is enabled - if there is a CRC mismatch, an I2C CRC fault is recognized and action taken according to CRC_ERR_MODE. If CRC_ERR_MODE is set to 0b, nFAULT is pulled low, the FETs are in Hi-Z and the CONTROLLER_FAULT and I2C_CRC_FAULT_STATUS bits are set to 1b until the fault condition is cleared by writing 1b to CLR_FLT. If EEP_FAULT_MODE is set to 1b, this fault is reported on nFAULT pin and CONTROLLER_FAULT, I2C_CRC_FAULT_STATUS bits are set to 1b but the device operation (FETs) continues normally. The fault reporting can be cleared (nFAULT pin is released, CONTROLLER_FAULT, I2C_CRC_FAULT_STATUS set to 0b) by writing 1b to CLR_FLT.

6.3.24.14 Minimum VM (Undervoltage) Protection

MCF8316D provides a configurable VM undervoltage protection. The VM level at which MCF8316D triggers the undervoltage fault is set by MIN_VM_MOTOR and the fault response to VM undervoltage is set by MIN_VM_MODE. If MIN_VM_MODE is set to 0b, VM undervoltage fault (at MIN_VM_MOTOR) is latched and the FETs are in Hi-Z until the fault condition is cleared by writing 1b to CLR_FLT bit. If MIN_VM_MODE is set to 1b, VM undervoltage fault (at MIN_VM_MOTOR) automatically clears and the device starts motor operation once VM > (MIN_VM_MOTOR + VOLTAGE_HYSTERESIS).

6.3.24.15 Maximum VM (Overvoltage) Protection

MCF8316D provides a configurable VM overvoltage protection. The VM level at which MCF8316D triggers the overvoltage fault is set by MAX_VM_MOTOR and the fault response to VM overvoltage is set by MAX_VM_MODE. If MAX_VM_MODE is set to 0b, VM overvoltage fault (at MAX_VM_MOTOR) is latched and the FETs are in Hi-Z until the fault condition is cleared by writing 1b to CLR_FLT bit. If MAX_VM_MODE is set to 1b, VM overvoltage fault (at MAX_VM_MOTOR) automatically clears and the device starts motor operation once VM < (MAX_VM_MOTOR - VOLTAGE_HYSTERESIS).

6.3.24.16 MPET Faults

An error during resistance and inductance measurement is reported using MPET_IPD_FAULT. The MPET_IPD_FAULT gets triggered when the IPD timer overflows due to unsuccessful attempt to ramp up the current to the threshold value, same as explained in Section 6.3.24.17. The fault typically gets triggered when there is no motor connected to MCF8316D or when the MPET IPD current threshold is set high for motors with high resistance. An error during BEMF constant measurement is reported using MPET_BEMF_FAULT. This fault gets triggered when the measured back EMF is less than the threshold set in STAT_DETECT_THR. One example of such fault scenario can be the motor stall while running in open loop due to incorrect open loop configuration used.

6.3.24.17 IPD Faults

The MCF8316D uses 12-bit timers to estimate the time during the current ramp up and ramp down during IPD, when the motor start-up is configured as IPD (MTR_STARTUP is set to 10b). During IPD, the algorithm checks for a successful current ramp-up to IPD_CURR_THR, starting with an IPD clock of 10MHz; if unsuccessful (timer overflow before current reaches IPD_CURR_THR), IPD is repeated with lower frequency clocks of 1MHz, 100kHz, and 10kHz sequentially. If the IPD timer overflows (current does not reach IPD_CURR_THR) with all the four clock frequencies, then the IPD_T1_FAULT gets triggered. Similarly the algorithm checks for a successful current decay to zero during IPD current ramp down using all the mentioned IPD clock frequencies. If the IPD timer overflows (current does not ramp down to zero) in all the four attempts, then the IPD_T2_FAULT gets triggered. The user can enable IPD timeout (IPD timer overflow) by setting IPD_TIMEOUT_FAULT_EN to 1b. IPD gives incorrect results if the next IPD pulse is commanded before the complete decay of current due to present IPD pulse. The MCF8316D can generate a fault called IPD_FREQ_FAULT during such a scenario by setting IPD_FREQ_FAULT_EN to 1b. The IPD_FREQ_FAULT maybe triggered if the IPD frequency is too high for the IPD current limit and the IPD release mode or if the motor inductance is too high for the IPD frequency, IPD current limit and IPD release mode. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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On the occurrence of any IPD fault, MCF8316D stops the IPD based start-up process and FETs are in Hi-Z. MCF8316D automatically retries IPD based start-up after tLCK_RETRY elapses.

6.3.24.18 FET Thermal Warning (OTW)

If the FET temperature exceeds the FET thermal warning limit (T OTW), nFAULT is pulled low and the OT and OTW bits in the gate driver status register are set to 1b. The reporting of OTW (on nFAULT and status bits) can be enabled by setting OTW_REP to 1b. The device performs no additional action and continues to function. The nFAULT pin is pulled low and OTW bit remains set until cleared through the CLR_FLT bit and the die temperature is lower than thermal warning limit. (TOTW - TOTW_HYS).

6.3.24.19 FET Thermal Shutdown (TSD_FET)

If the FET temperature exceeds the FET thermal shutdown limit (TTSD_FET), all the FETs are disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the DRIVER_FAULT, OT and OTS bit in the status register are set to 1b. Normal operation resumes (driver operation and the nFAULT pin is released) when the die temperature decreases below the hysteresis point of the thermal shutdown limit (T TSD_FET - TTSD_FET_HYS). The OTS bit stays latched high indicating that a thermal event occurred until a clear fault command is issued through the CLR_FLT bit. This protection feature cannot be disabled. Note If die temperature increases to T TSD_BUCK, MCF8316D will undergo a reset and all fault status bits in this case will be reset to 0b. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: MCF8316D

6.4 Device Functional Modes

6.4.1 Functional Modes

6.4.1.1 Sleep Mode

In sleep mode, the MOSFETs, sense amplifiers, buck regulator, charge pump, AVDD LDO regulator and the I2C bus are disabled. The device can be configured to enter sleep (instead of standby) mode by configuring DEV_MODE to 1b. SPEED pin and I 2C speed command determine entry and exit from sleep state as described in Table 6-8.

6.4.1.2 Standby Mode

The device can be configured to operate as a standby device by setting DEV_MODE to 0b. In standby mode, the charge pump, AVDD LDO, buck regulator and I 2C bus are active while the motor is in stopped state waiting for a suitable non-zero speed command. SPEED pin (analog, PWM or frequency based speed input) or I 2C speed command (I2C based speed input) determines entry and exit from standby state as described in Table 6-8. The thresholds for entering and exiting standby mode in different input modes are as follows, Table 6-7. Standby Mode Entry/Exit Thresholds Input Source (SPEED_MODE) Standby entry/exit thresholds REF_PROFILE_CONFIG = 00b REF_PROFILE_CONFIG ≠ 00b Analog (00b) VEN_SB 1% x VANA_FS 1% x VANA_FS VEX_SB 5% x VANA_FS 5% x VANA_FS PWM (01b) DutyEX_SB/EN_SB Maximum of (1%, DUTY_HYS) 0% I2C (10b) DIGITAL_SPEED_CTRLEX_SB/ EN_SB Maximum of (1%, DUTY_HYS) x 32767 Frequency (11b) FreqEX_SB/EN_SB Maximum of (1%, DUTY_HYS) x INPUT_MAXIMUM_FREQ (subject to minimum of 3Hz) < 3Hz Table 6-8. Conditions to Enter or Exit Sleep/Standby Modes SPEED COMMAND MODE ENTER STANDBY CONDITION EXIT FROM STANDBY CONDITION ENTER SLEEP CONDITION EXIT FROM SLEEP CONDITION Analog VSPEED < VEN_SB VSPEED > VEX_SB VSPEED < VEN_SL for tDET_SL_ANA VSPEED > VEX_SL for tDET_ANA PWM DutySPEED < DutyEN_SB DutySPEED > DutyEX_SB VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM I2C DIGITAL_SPEED_CTRL < DIGITAL_SPEED_CTRLEN_SB DIGITAL_SPEED_CTRL > DIGITAL_SPEED_CTRLEX_S B DIGITAL_SPEED_CTRL is set to 0b for SLEEP_ENTRY_TIME and VSPEED < VIL VSPEED > VIH for tDET_PWM Frequency FreqSPEED < FreqEN_SB FreqSPEED > FreqEX_SB VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM Note VSPEED : SPEED pin input voltage, Duty SPEED : SPEED pin input PWM duty, Freq SPEED : SPEED pin input frequency

6.4.1.3 Fault Reset (CLR_FLT)

In the case of latched faults, the device goes into a partial shutdown state to help protect the power MOSFETs and system. When the fault condition clears, the device can go to the operating state again by setting the CLR_FLT to 1b. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.5 External Interface

6.5.1 DRVOFF Functionality

When DRVOFF pin is driven high, all six MOSFETs are put in Hi-Z state, irrespective of speed command. If motor speed command is non-zero when DRVOFF is driven high, device may encounter a fault like no motor or abnormal BEMF. Whenever DRVOFF is driven high, it should be held high for a minimum of 10s for safe operation.

6.5.2 DAC outputs

MCF8316D has two 12-bit DACs which output analog voltage equivalent of digital variables on the DACOUT1 and DACOUT2 pins. The maximum DAC output voltage is 3-V. Signals available on DACOUT pins are useful in tracking internal variables in real-time and can be used for tuning speed controller or motor acceleration time. The address for variables to be tracked on DACOUT1 and DACOUT2 are configured using DACOUT1_VAR_ADDR and DACOUT2_VAR_ADDR respectively. DACOUT1 is available on pin 36 and DACOUT2 can be configured on pin 38 by setting DAC_SOx_SEL to 00b. DACOUT2 is also available on pin 37. DAC_ENABLE should be configured to 1b for pins 36, 37 to function as DAC outputs.

6.5.3 Current Sense Output

MCF8316D can provide the built-in current sense amplifiers' output on the SOX pin. SOX output is available on pin 38 and can be configured by DAC_SOx_SEL.

6.5.4 Oscillator Source

MCF8316D has a built-in oscillator that is used as the clock source for all digital peripherals and timing measurements. Default configuration for MCF8316D is to use the internal oscillator and it is sufficient to drive the motor without need for any external crystal or clock sources. In case MCF8316D does not meet accuracy requirements of timing measurement or speed loop, then MCF8316D has an option to support an external clock reference. In order to improve EMI performance, MCF8316D provides the option of modulating the clock frequency by enabling Spread Spectrum Modulation (SSM) through SPREAD_SPECTRUM_MODULATION_DIS.

6.5.4.1 External Clock Source

Speed loop accuracy of MCF8316D over the operating temperature range can be improved by providing a more accurate clock reference on EXT_CLK pin as shown in Figure 6-64. EXT_CLK will be used to calibrate the internal clock oscillator - this will help match the accuracy of the internal clock oscillator to that of the external clock. External clock source can be selected by setting EXT_CLK_EN to 1b. The external clock source frequency can be configured through EXT_CLK_CONFIG. Internal Oscillator (60 MHz) CalibrateEXT_CLK Figure 6-64. External Clock Reference Note External clock is optional and can be used when higher clock accuracy is needed. MCF8316D will always power up using the internal oscillator in all modes. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: MCF8316D

6.5.5 External Watchdog

MCF8316D provides an external watchdog feature - EXT_WDT_EN bit should be set to 1b to enable the external watchdog. When this feature is enabled, the device waits for a tickle (low to high transition in EXT_WD pin, WATCHDOG_TICKLE set to 1b in I2C mode) from the external watchdog input for a configured time interval; if the time interval between two consecutive tickles is higher than the configured time, a watchdog fault is triggered. The watchdog fault response can be configured using EXT_WDT_FAULT_MODE either as a report only fault or as a latched fault with MOSFETs in Hi-Z state. The latched fault can be cleared by writing 1b to CLR_FLT. When a watchdog timeout occurs, WATCHDOG_FAULT bit is set to 1b. In case, the next tickle arrives before the configured time interval elapses, the watchdog timer is reset and it begins to wait for the next tickle. This can be used to continuously monitor the health of an external MCU (which is the external watchdog input) and put the MCF8316D MOSFETs in Hi-Z, in case the external MCU is in a fault/hang state. The external watchdog input is selected using EXT_WDT_INPUT_MODE and can either be the EXT_WD pin or the I 2C interface. The time interval between two tickles to trigger a watchdog fault is configured by EXT_WDT_CONFIG; there are 4 time settings - 100, 200, 500 and 1000ms for the EXT_WD pin based watchdog and 4 time settings - 1, 2, 5 and 10s for the I2C based watchdog. Note Watchdog should be disabled by setting EXT_WDT_EN to 0b before changing EXT_WDT_CONFIG configuration. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.6 EEPROM access and I2C interface

6.6.1 EEPROM Access

MCF8316D has 1024 bits (16 rows of 64 bits each) of EEPROM, which are used to store the motor configuration parameters. Erase operations are row-wise (all 64 bits are erased in a single erase operation), but 32-bit write and read operations are supported. EEPROM can be written and read using the I 2C serial interface but erase cannot be performed using I 2C serial interface. The shadow/RAM registers corresponding to the EEPROM are located at addresses 0x000080-0x0000AE. Note MCF8316D allows EEPROM write and read operations only when the motor is not spinning.

6.6.1.1 EEPROM Write

• EEPROM write should be issued only when device is in idle or fault state (motor not driven by device). VM should be ≥ 6V throughout the EEPROM write process to ensure that all power rails (AVDD, FB_BK and DVDD) stay within datasheet specifications and EEPROM write is never interrupted due to any UVLO condition.
• TI does not recommend writing to EEPROM during every power-up/wake-up due to aging/write cycle limitations on number of EEPROM writes (20000 write cycles at TJ = 85oC). Repetitive register settings change can be done at shadow/RAM registers (0x000080-0x0000AE); only default configurations need to be written to EEPROM (at first power-up) In MCF8316D, EEPROM write procedure is as follows, 1. Write register 0x000080 (ISD_CONFIG) with ISD and reverse drive configuration like resync enable, reverse drive enable, stationary detect threshold, reverse drive handoff threshold etc. 2. Write register 0x000082 (REV_DRIVE_CONFIG) with reverse drive and active brake configuration like reverse drive open loop acceleration, active brake current limit, Kp, Ki values etc. 3. Write register 0x000084 (MOTOR_STARTUP1) with motor start-up configuration like start-up method, IPD parameters, align parameters etc. 4. Write register 0x000086 (MOTOR_STARTUP2) with motor start-up configuration like open loop acceleration, open loop current limit, first cycle frequency etc. 5. Write register 0x000088 (CLOSED_LOOP1) with motor control configuration like closed loop acceleration, overmodulation enable, PWM frequency, FG signal parameters etc. 6. Write register 0x00008A (CLOSED_LOOP2) with motor control configuration like motor winding resistance and inductance, motor stop options, brake speed threshold etc. 7. Write register 0x00008C (CLOSED_LOOP3) with motor control configuration like motor BEMF constant, current loop Kp, Ki etc. 8. Write register 0x00008E (CLOSED_LOOP4) with motor control configuration like speed loop Kp, Ki and maximum speed. 9. Write register 0x000090 (FAULT_CONFIG1) with fault control configuration software and hardware current limits, lock current limit and actions, retry times etc. 10. Write register 0x000092 (FAULT_CONFIG2) with fault control configuration like hardware current limit actions, OV, UV limits and actions, abnormal speed level, no motor threshold etc. 11. Write registers 0x000094 – 0x00009E (SPEED_PROFILES1-6) with speed profile configuration like profile type, duty cycle, speed clamp level, duty cycle clamp level etc. 12. Write register 0x0000A0 (INT_ALGO_1) with miscellaneous configuration like ISD run time and timeout, MPET parameters etc. 13. Write register 0x0000A2 (INT_ALGO_2) with miscellaneous configuration like additional MPET parameters, IPD high resolution enable, active brake current slew rate, closed loop slow acceleration etc. 14. Write registers 0x0000A4 (PIN_CONFIG1) with pin configuration for speed input mode (analog or PWM), BRAKE pin mode etc. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: MCF8316D

1. Write registers 0x0000A6 and 0x0000A8 (DEVICE_CONFIG1 and DEVICE_CONFIG2) with device configuration like DAC/SOX, I2C target address, dynamic CSA gain enable, dynamic voltage gain enable, clock source select, speed range select etc. 16. Write register 0x0000AA (PERI_CONFIG1) with peripheral configuration like dead time, bus current limit, DIR input, SSM enable etc. 17. Write registers 0x0000AC and 0x0000AE (GD_CONFIG1 and GD_CONFIG2) with gate driver configuration like slew rate, CSA gain, OCP level, mode, OVP enable, level, buck voltage level, buck current limit etc. 18. Write 0x8A500000 into register 0x0000EA to write the shadow/RAM register (0x000080-0x0000AE) values into the EEPROM. 19. Wait for 750ms for the EEPROM write operation to complete. 20. After 750ms, read 0x0000EA register to ensure it has been reset to 0x0. This confirms that the EEPROM write process has been completed successfully. Steps 1-17 can be selectively executed based on registers/parameters that need to be modified. After all shadow/RAM registers have been updated with the required values, steps 18-20 should be executed to write the contents of the shadow/RAM registers into the EEPROM.

6.6.1.2 EEPROM Read

In MCF8316D, EEPROM read procedure is as follows, 1. Write 0x40000000 into register 0x0000EA to read the EEPROM data into the shadow/RAM registers (0x000080-0x0000AE). 2. Wait for 100ms for the EEPROM read operation to complete. 3. Read the shadow/RAM register values, one or two registers at a time, using the I2C read command as explained in Section 6.6.2. Shadow/RAM register addresses are in the range of 0x000080-0x0000AE. Register address increases in steps of 2 for 32-bit read operation (since each address is a 16-bit location).

6.6.1.3 EEPROM Security

MCF8316D provides configurable read and write protection to EEPROM registers. The level of protection can be configured using EEPROM_LOCK_MODE as per following list,

• 00b : EEPROM read and write are allowed without a passcode
• 01b : EEPROM read and write need a valid passcode
• 10b : EEPROM read needs a valid passcode; EEPROM write is locked permanently
• 11b : EEPROM read and write are locked permanently Passcode is a 15-bit field in the EEPROM denoted by EEPROM_LOCK_KEY in the DEVICE_CONFIG1 register. EEPROM_LOCK_KEY is write accessible (when EEPROM_LOCK_MODE is set to 00b or 01b) but not read accessible. When passcode based read/write protection is enabled (EEPROM_LOCK_MODE set to 01b or 10b), user has to write the passcode set in EEPROM_LOCK_KEY to USER_EEPROM_KEY bitfield in 0xF8 register after every power-up/wake-up before sending the first EEPROM read/write transaction over I 2C. One valid passcode write after power-up/wake-up is sufficient for all subsequent EEPROM read/write transactions as long as there is no power reset, sleep mode entry, digital reset or incorrect passcode write. If an invalid passcode is written, the subsequent EEPROM read/write transactions are rejected - MCF8316D does not respond to the read/ write requests. The read/write protection is applicable to EEPROM as well as the corresponding shadow/RAM locations. The EEPROM_LOCK_MODE as well as the passcode are part of the EEPROM registers and hence same level of read/write protection applies to these bit fields as configured by EEPROM_LOCK_MODE.

6.6.2 I2C Serial Interface

MCF8316D interfaces with an external MCU over an I 2C serial interface. MCF8316D is an I 2C target to be interfaced with a controller. External MCU can use this interface to read/write from/to any non-reserved register in MCF8316D. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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For reliable communication, a 100-µs delay should be used between every byte transferred over the I2C bus.

6.6.2.1 I2C Data Word

The I2C data word format is shown in Table 6-9. Table 6-9. I2C Data Word Format TARGET_ID R/W CONTROL WORD DATA CRC-8 A6 - A0 W0 CW23 - CW0 D15 / D31/ D63 - D0 C7 - C0 Target ID and R/W Bit : The first byte includes the 7-bit I 2C target ID, followed by the read/write command bit. Every packet in MCF8316D the communication protocol starts with writing a 24-bit control word and hence the R/W bit is always 0. 24-bit Control Word: The Target Address is followed by a 24-bit control bit. The control word format is shown in Table 6-10. Table 6-10. 24-bit Control Word Format OP_R/W CRC_EN DLEN MEM_SEC MEM_PAGE MEM_ADDR CW23 CW22 CW21- CW20 CW19 - CW16 CW15 - CW12 CW11 - CW0 Each field in the control word is explained in detail below. OP_R/W – Read/Write : R/W bit gives information on whether this is a read (1b) operation or write (0b) operation. For write operation, MCF8316D will expect data bytes to be sent after the 24-bit control word. For read operation, MCF8316D will expect an I 2C read request with repeated start or normal start after the 24-bit control word. CRC_EN – Cyclic Redundancy Check(CRC) Enable : MCF8316D supports CRC to verify the data integrity. This bit controls whether the CRC feature is enabled or not. DLEN – Data Length : DLEN field determines the length of the data that will be sent by external MCU to MCF8316D. MCF8316D protocol supports three data lengths: 16-bit, 32-bit and 64-bit. Table 6-11. Data Length Configuration DLEN Value Data Length 00b 16-bit 01b 32-bit 10b 64-bit 11b Reserved MEM_SEC – Memory Section: Each memory location in MCF8316D is addressed using three separate entities in the control word – Memory Section, Memory Page, Memory Address. Memory Section is a 4-bit field which denotes the memory section to which the memory location belongs like RAM, ROM etc. MEM_PAGE – Memory Page : Memory page is a 4-bit field which denotes the memory page to which the memory location belongs. MEM_ADDR – Memory Address : Memory address is the last 12-bits of the address. The complete 22-bit address is constructed internally by MCF8316D using all three fields – Memory Section, Memory Page, Memory Address. For memory locations 0x000000-0x000800, memory section is 0x0, memory page is 0x0 and memory address is the lowest 12 bits(0x000 for 0x000000, 0x080 for 0x000080 and 0x800 for 0x000800). All relevant memory locations (EEPROM and RAM variables) have MEM_SEC and MEM_PAGE values both corresponding to 0x0. All other MEM_SEC, MEM_PAGE values are reserved and not for external use. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: MCF8316D

Data Bytes: For a write operation to MCF8316D, the 24-bit control word is followed by data bytes. The DLEN field in the control word should correspond with the number of bytes sent in this section. In case of mismatch between number of data bytes and DLEN, the write operation is discarded. CRC Byte: If the CRC feature is enabled in the control word, CRC byte has to be sent at the end of a write

6.6.2.2 I2C Write Transaction

MCF8316D write transaction over I2C involves the following sequence (see Figure 6-65). 1. I2C start condition. 2. Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK in yellow box indicates that MCF8316D has processed the received target ID which has matched with it's I2C target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID of MCF8316D, then the transaction is ignored. and no ACK is sent by MCF8316D. 3. The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control word is 0b as it is a write transaction. ACK in blue boxes correspond to acknowledgements sent by MCF8316D to the controller that the previous byte (of control word) has been received and next byte can be sent. 4. The 24-bit control word is then followed by the data bytes. The number of data bytes sent by the controller depends on the DLEN field in the control word. b. 16-bit/32-bit write – The data sent is written to the address mentioned in control word. c. 64-bit Write – 64-bit is treated as two successive 32-bit writes. The address mentioned in control word is taken as Addr_1. Addr_2 is internally calculated by MCF8316D by incrementing Addr_1 by 0x2. A total of 8 data bytes are sent. The first 4 bytes (sent in LSB first) are written to Addr_1 and the next 4 bytes are written to Addr_2. d. ACK in blue boxes (after every data byte) correspond to the acknowledgement sent by MCF8316D to the controller that the previous data byte has been received and next data byte can be sent. 5. If CRC is enabled, the packet ends with a CRC byte. CRC is calculated for the entire packet (Target ID + W bit, Control Word, Data Bytes). MCF8316D will send an ACK on receiving the CRC byte. 6. I2C Stop condition from the controller to terminate the transaction. S TARGET ID [6:0] CONTROL WORD [23:16]0 ACK DATA BYTE P Write – without CRC 2 / 4 / 8 DATA BYTES ACK CONTROL WORD [15:8] ACK CONTROL WORD [7:0] ACK ACK DATA BYTE S TARGET ID [6:0] CONTROL WORD [23:16]0 ACK DATA BYTE P Write – with CRC 2 / 4 / 8 DATA BYTES ACK CONTROL WORD [15:8] ACK CONTROL WORD [7:0] ACK ACK CRCDATA BYTE ACK CRC includes {TARGET ID,0}, CONTROL WORD[23:0], DATA BYTES ACK ACK Figure 6-65. I2C Write Transaction Sequence

6.6.2.3 I2C Read Transaction

MCF8316D read transaction over I2C involves the following sequence (see Figure 6-66). 1. I2C Start condition from the controller to initiate the transaction. 2. Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK (in yellow box) indicates that MCF8316D has processed the received target ID which has matched with it's I2C target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID of MCF8316D, then the transaction is ignored and no ACK is sent by MCF8316D. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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1. The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control word is set to 1b as it is a read transaction. ACK (in blue boxes) correspond to acknowledgements sent by MCF8316D to the controller that the previous byte (of control word) has been received and next byte can be sent. 4. The control word is followed by a Repeated Start (RS, start without a preceding stop) or normal Start (P followed by S) to initiate the data (to be read back) transfer from MCF8316D to I2C controller. RS or S is followed by the 7-bit target ID along with R/W bit set to 1b to initiate the read transaction. MCF8316D sends an ACK (in grey box after RS) to the controller to acknowledge the receipt of read transaction request. 5. Post acknowledgement of read transaction request, MCF8316D sends the data bytes on SDA one byte at a time. The number of data bytes sent by MCF8316D depends on the DLEN field in the control word. details. b. 16-bit/32-bit Read – The data from the address mentioned in control word is sent back to the controller. c. 64-bit Read – 64-bit is treated as two successive 32-bit reads. The address mentioned in control word is taken as Addr_1. Addr_2 is internally calculated by MCF8316D by incrementing Addr_1 by 0x2. A total of 8 data bytes are sent by MCF8316D. The first 4 bytes (sent in LSB first) are read from Addr_1 and the next 4 bytes are read from Addr_2. d. ACK in orange boxes correspond to acknowledgements sent by the controller to MCF8316D that the previous byte has been received and next byte can be sent. 6. If CRC is enabled in the control word, then MCF8316D sends an additional CRC byte at the end. Controller has to read the CRC byte and then send the last ACK (in orange). CRC is calculated for the entire packet (Target ID + W bit, Control Word, Target ID + R bit, Data Bytes). 7. I2C Stop condition from the controller to terminate the transaction. S TARGET ID [6:0] CONTROL WORD [23:16]0 ACK DATA BYTE P Read – without CRC 2 / 4 / 8 DATA BYTES RS TARGET ID [6:0] 1 CRC includes {TARGET ID,0}, CONTROL WORD[23:0], {TARGET ID,1}, DATA BYTES ACK CONTROL WORD [15:8] ACK CONTROL WORD [7:0] ACK ACK ACK DATA BYTE S TARGET ID [6:0] CONTROL WORD [23:16]0 ACK DATA BYTE P Read – with CRC 2 / 4 / 8 DATA BYTES RS TARGET ID [6:0] 1ACK CONTROL WORD [15:8] ACK CONTROL WORD [7:0] ACK ACK ACK CRCDATA BYTE ACK ACK ACK Figure 6-66. I2C Read Transaction Sequence

6.6.2.4 I2C Communication Protocol Packet Examples

All values used in this example section are in hex format. I2C target ID used in the examples is 0x60. Example for 32-bit Write Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x45 (Sample value; does not match with the actual CRC calculation) Table 6-12. Example for 32-bit Write Operation Packet Start Byte Control Word 0 Control Word 1 Control Word 2 Data Bytes CRC Target ID I2C Write OP_R/ W CRC_E N DLEN MEM_S EC MEM_P AGE MEM_A DDR MEM_A DDR DB0 DB1 DB2 DB3 CRC Byte A6-A0 W0 CW23 CW22 CW21- CW20 CW19- CW16 CW15- CW12 CW11- CW8 CW7- CW0 D7-D0 D7-D0 D7-D0 D7-D0 C7-C0 0x60 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x80 0xCD 0xAB 0x34 0x12 0x45 0xC0 0x50 0x00 0x80 0xCD 0xAB 0x34 0x12 0x45 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: MCF8316D

Example for 64-bit Write Operation : Address - 0x00000080, Data Address 0x00000080 - Data 0x01234567, Data Address 0x00000082 – Data 0x89ABCDEF, CRC Byte – 0x45 (Sample value; does not match with the actual CRC calculation) Table 6-13. Example for 64-bit Write Operation Packet Start Byte Control Word 0 Control Word 1 Control Word Data Bytes CRC Target ID I2C Write OP_R/W CRC_EN DLEN MEM_SEC MEM_PAGE MEM_ADDR MEM_ADDR DB0 - DB7 CRC Byte A6-A0 W0 CW23 CW22 CW21- CW20 CW19- CW16 CW15- CW12 CW11-CW8 CW7-CW0 [D7-D0] x 8 C7-C0 0x60 0x0 0x0 0x1 0x2 0x0 0x0 0x0 0x80 0x67452301EFCDAB89 0x45 0xC0 0x60 0x00 0x80 0x67452301EFCDAB89 0x45 Example for 32-bit Read Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x56 (Sample value; does not match with the actual CRC calculation) Table 6-14. Example for 32-bit Read Operation Packet Start Byte Control Word 0 Control Word 1 Control Word 2 Start Byte Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Target ID I2C Write R/W CRC_ EN DLEN MEM_ SEC MEM_ PAGE MEM_ ADDR MEM_ ADDR Target ID I2C Read DB0 DB1 DB2 DB3 CRC Byte A6-A0 W0 CW23 CW22 CW21- CW20 CW19- CW16 CW15- CW12 CW11- CW8 CW7- CW0 A6-A0 W0 D7-D0 D7-D0 D7-D0 D7-D0 C7-C0 0x60 0x0 0x1 0x1 0x1 0x0 0x0 0x0 0x80 0x60 0x1 0xCD 0xAB 0x34 0x12 0x56 0xC0 0xD0 0x00 0x80 0xC1 0xCD 0xAB 0x34 0x12 0x56

6.6.2.5 I2C Clock Stretching

The I2C peripheral in MCF8316D implements clock stretching under certain conditions when there are pending I2C interrupts waiting to be processed. During clock stretching, MCF8316D pulls SCL low and the I 2C bus is unavailable for use by other devices. The following is a list of conditions under which clock stretching can occur: 1. Start interrupt pending: There are two scenarios when a start interrupt can result in clock stretching, a. When target ID is a match, I2C peripheral in MCF8316D raises a start interrupt request. Until this start interrupt request is processed, clock is stretched. Upon processing this request, clock is released and an ACK (marked in yellow or grey in Figure 6-65 and Figure 6-66) is sent to the controller for continuing with the transaction. b. If Start (followed by target ID match) for a new transaction is received when a receive interrupt from previous transaction is yet to be processed, clock is stretched until both the receive interrupt and start interrupt are processed in chronological order. This process ensures that previous transaction is executed correctly before initiating the next transaction. 2. Receive interrupt pending: When a receive interrupt is waiting to be processed and the receive register is full which occurs when two successive bytes (data or control) have been received by MCF8316D (separated by one ACK shown as blue boxes in Figure 6-65 and Figure 6-66) without the receive interrupt generated by the first byte being processed. Upon receive of second byte, clock is stretched until receive interrupt generated by the first byte is processed. 3. Transmit buffer is empty: In case of a transmit interrupt pending (to send data back to controller), if the transmit buffer is waiting to be populated with data to be read back to the controller, clock stretching is done until the transmit buffer is populated with requested data. After the buffer is populated, clock is released and data is sent to controller. Note I2C clock stretching is timed out after 5 ms by MCF8316D to allow I2C bus access for other devices on the same bus. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.6.2.6 CRC Byte Calculation

An 8-bit CCIT polynomial (x8 + x2+ x + 1) and CRC initial value 0xFF is used for CRC computation. CRC Calculation in Write Operation: When the external MCU writes to MCF8316D, if the CRC is enabled, the external MCU has to compute an 8-bit CRC byte and add the CRC byte at the end of the data. MCF8316D will compute CRC using the same polynomial internally and if there is a mismatch, the write request is discarded. Input data for CRC calculation by external MCU for write operation are listed below: 1. Target ID + write bit. 2. Control word – 3 bytes 3. Data bytes – 2/4/8 bytes CRC Calculation in Read Operation : When the external MCU reads from MCF8316D, if the CRC is enabled, MCF8316D sends the CRC byte at the end of the data. The CRC computation in read operation involves the start byte, control words sent by external MCU along with data bytes sent by MCF8316D. Input data for CRC calculation by external MCU to verify the data sent by MCF8316D are listed below : 1. Target ID + write bit 2. Control word – 3 bytes 3. Target ID + read bit 4. Data bytes – 2/4/8 bytes www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: MCF8316D

6.7 EEPROM (Non-Volatile) Register Map

6.7.1 Algorithm_Configuration Registers

Table 6-15 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in Table 6-15 should be considered as reserved locations and the register contents should not be modified. Table 6-15. ALGORITHM_CONFIGURATION Registers Offset Acronym Register Name Section 80h ISD_CONFIG ISD Configuration Section 6.7.1.1 82h REV_DRIVE_CONFIG Reverse Drive Configuration Section 6.7.1.2 84h MOTOR_STARTUP1 Motor Startup Configuration1 Section 6.7.1.3 86h MOTOR_STARTUP2 Motor Startup Configuration2 Section 6.7.1.4 88h CLOSED_LOOP1 Close Loop Configuration1 Section 6.7.1.5 8Ah CLOSED_LOOP2 Close Loop Configuration2 Section 6.7.1.6 8Ch CLOSED_LOOP3 Close Loop Configuration3 Section 6.7.1.7 8Eh CLOSED_LOOP4 Close Loop Configuration4 Section 6.7.1.8 94h REF_PROFILES1 Reference Profile Configuration1 Section 6.7.1.9 96h REF_PROFILES2 Reference Profile Configuration2 Section 6.7.1.10 98h REF_PROFILES3 Reference Profile Configuration3 Section 6.7.1.11 9Ah REF_PROFILES4 Reference Profile Configuration4 Section 6.7.1.12 9Ch REF_PROFILES5 Reference Profile Configuration5 Section 6.7.1.13 9Eh REF_PROFILES6 Reference Profile Configuration6 Section 6.7.1.14 Complex bit access types are encoded to fit into small table cells. Table 6-16 shows the codes that are used for access types in this section. Table 6-16. Algorithm_Configuration Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in Figure 6-67 and described in Table 6-17. Return to the Summary Table. Register to configure initial speed detect settings Figure 6-67. ISD_CONFIG Register 31 30 29 28 27 26 25 24 PARITY ISD_EN BRAKE_EN HIZ_EN RVS_DR_EN RESYNC_EN FW_DRV_RESYN_THR R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 FW_DRV_RESYN_THR BRK_MODE BRK_CONFIG BRK_CURR_THR BRK_TIME R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 BRK_TIME HIZ_TIME STAT_DETECT _THR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 STAT_DETECT_THR REV_DRV_HANDOFF_THR REV_DRV_OPEN_LOOP_CURR ENT R/W-0h R/W-0h R/W-0h Table 6-17. ISD_CONFIG Register Field Descriptions Bit Field Type Reset Description

31 PARITY R/W 0h Parity bit

30 ISD_EN R/W 0h ISD enable

0h = Disable 1h = Enable

29 BRAKE_EN R/W 0h ISD brake enable

0h = Disable 1h = Enable

28 HIZ_EN R/W 0h ISD Hi-Z enable

0h = Disable 1h = Enable

27 RVS_DR_EN R/W 0h Reverse drive enable

0h = Disable 1h = Enable

26 RESYNC_EN R/W 0h Resynchronization enable

0h = Disable 1h = Enable www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: MCF8316D

Table 6-17. ISD_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 25-22 FW_DRV_RESYN_THR R/W 0h Minimum speed threshold to resynchronize to close loop (% of MAX_SPEED) 0h = 5% 1h = 10% 2h = 15% 3h = 20% 4h = 25% 5h = 30% 6h = 35% 7h = 40% 8h = 45% 9h = 50% Ah = Not Applicable Bh = Not Applicable Ch = Not Applicable Dh = Not Applicable Eh = Not Applicable Fh = Not Applicable

21 BRK_MODE R/W 0h Brake mode

0h = All three high side FETs turned ON 1h = All three low side FETs turned ON

20 BRK_CONFIG R/W 0h Brake configuration

0h = Brake time is used to come out of Brake state 1h = Brake current threshold and Brake time is used to come out of Brake state 19-17 BRK_CURR_THR R/W 0h Brake current threshold 0h = 0.1 A 1h = 0.2 A 2h = 0.3 A 3h = 0.5 A 4h = 1.0 A 5h = 2.0 A 6h = Not Applicable 7h = Not Applicable MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-17. ISD_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 16-13 BRK_TIME R/W 0h Brake time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s 12-9 HIZ_TIME R/W 0h Hi-Z time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 2 s Ah = 3 s Bh = 4 s Ch = 5 s Dh = 7.5 s Eh = 10 s Fh = 15 s 8-6 STAT_DETECT_THR R/W 0h BEMF threshold to detect if motor is stationary 0h = 50 mV 1h = 75 mV 2h = 100 mV 3h = 250 mV 4h = 500 mV 5h = 750 mV 6h = 1000 mV 7h = 1500 mV www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: MCF8316D

Table 6-17. ISD_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 5-2 REV_DRV_HANDOFF_T HR R/W 0h Speed threshold used to transition to open loop during reverse drive (% of MAX_SPEED) 0h = 2.5% 1h = 5% 2h = 7.5% 3h = 10% 4h = 12.5% 5h = 15% 6h = 20% 7h = 25% 8h = 30% 9h = 40% Ah = 50% Bh = Not Applicable Ch = Not Applicable Dh = Not Applicable Eh = Not Applicable Fh = Not Applicable 1-0 REV_DRV_OPEN_LOOP _CURRENT R/W 0h Open loop current limit during reverse drive 0h = 1.5 A 1h = 2.5 A 2h = 3.5 A 3h = 5.0 A MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.2 REV_DRIVE_CONFIG Register (Offset = 82h) [Reset = 00000000h]

REV_DRIVE_CONFIG is shown in Figure 6-68 and described in Table 6-18. Return to the Summary Table. Register to configure reverse drive settings Figure 6-68. REV_DRIVE_CONFIG Register 31 30 29 28 27 26 25 24 PARITY REV_DRV_OPEN_LOOP_ACCEL_A1 REV_DRV_OPEN_LOOP_ACCEL_A2 R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 REV_DRV_OP EN_LOOP_AC CEL_A2 ACTIVE_BRAKE_CURRENT_LIMIT ACTIVE_BRAKE_KP R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 ACTIVE_BRAKE_KP ACTIVE_BRAKE_KI R/W-0h R/W-0h 7 6 5 4 3 2 1 0 ACTIVE_BRAKE_KI R/W-0h Table 6-18. REV_DRIVE_CONFIG Register Field Descriptions Bit Field Type Reset Description 30-27 REV_DRV_OPEN_LOOP _ACCEL_A1 R/W 0h Open loop acceleration coefficient A1 during reverse drive 0h = 0.1 Hz/s 1h = 0.5 Hz/s 2h = 1 Hz/s 3h = 2.5 Hz/s 4h = 5 Hz/s 5h = 10 Hz/s 6h = 25 Hz/s 7h = 50 Hz/s 8h = 75 Hz/s 9h = 100 Hz/s Ah = 250 Hz/s Bh = 500 Hz/s Ch = 750 Hz/s Dh = 1000 Hz/s Eh = 5000 Hz/s Fh = 10000 Hz/s www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: MCF8316D

Table 6-18. REV_DRIVE_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 26-23 REV_DRV_OPEN_LOOP _ACCEL_A2 R/W 0h Open loop acceleration coefficient A2 during reverse drive 0h = 0.0 Hz/s2 1h = 0.5 Hz/s2 2h = 1 Hz/s2 3h = 2.5 Hz/s2 4h = 5 Hz/s2 5h = 10 Hz/s2 6h = 25 Hz/s2 7h = 50 Hz/s2 8h = 75 Hz/s2 9h = 100 Hz/s2 Ah = 250 Hz/s2 Bh = 500 Hz/s2 Ch = 750 Hz/s2 Dh = 1000 Hz/s2 Eh = 5000 Hz/s2 Fh = 10000 Hz/s2 22-20 ACTIVE_BRAKE_CURRE NT_LIMIT R/W 0h Bus current limit during active braking 0h = 0.5 A 1h = 1.0 A 2h = 2.0 A 3h = 3.0 A 4h = 4.0 A 5h = 5.0 A 6h = 6.0 A 7h = 7.0 A 19-10 ACTIVE_BRAKE_KP R/W 0h 10-bit value for active braking loop Kp. Kp = ACTIVE_BRAKE_KP / 9-0 ACTIVE_BRAKE_KI R/W 0h 10-bit value for active braking loop Ki. Ki = ACTIVE_BRAKE_KI / 29 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.3 MOTOR_STARTUP1 Register (Offset = 84h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in Figure 6-69 and described in Table 6-19. Return to the Summary Table. Register to configure motor startup settings1 Figure 6-69. MOTOR_STARTUP1 Register 31 30 29 28 27 26 25 24 PARITY MTR_STARTUP ALIGN_SLOW_RAMP_RATE ALIGN_TIME R/W-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 ALIGN_TIME ALIGN_OR_SLOW_CURRENT_ILIMIT IPD_CLK_FRE Q R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 IPD_CLK_FREQ IPD_CURR_THR IPD_RLS_MOD E R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 IPD_ADV_ANGLE IPD_REPEAT RESERVED IQ_RAMP_EN ACTIVE_BRAK E_EN REV_DRV_CO NFIG R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h Table 6-19. MOTOR_STARTUP1 Register Field Descriptions Bit Field Type Reset Description 30-29 MTR_STARTUP R/W 0h Motor start-up method 0h = Align 1h = Double Align 2h = IPD 3h = Slow first cycle 28-25 ALIGN_SLOW_RAMP_RA TE R/W 0h Align, slow first cycle and open loop current ramp rate 0h = 0.1 A/s 1h = 1 A/s 2h = 5 A/s 3h = 10 A/s 4h = 15 A/s 5h = 25 A/s 6h = 50 A/s 7h = 100 A/s 8h = 150 A/s 9h = 200 A/s Ah = 250 A/s Bh = 500 A/s Ch = 1000 A/s Dh = 2000 A/s Eh = 5000 A/s Fh = No Limit A/s www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: MCF8316D

Table 6-19. MOTOR_STARTUP1 Register Field Descriptions (continued) Bit Field Type Reset Description 24-21 ALIGN_TIME R/W 0h Align time 0h = 10 ms 1h = 50 ms 2h = 100 ms 3h = 200 ms 4h = 300 ms 5h = 400 ms 6h = 500 ms 7h = 750 ms 8h = 1 s 9h = 1.5 s Ah = 2 s Bh = 3 s Ch = 4 s Dh = 5 s Eh = 7.5 s Fh = 10 s 20-17 ALIGN_OR_SLOW_CUR RENT_ILIMIT R/W 0h Align or slow first cycle current limit 0h = 0.125 A 1h = 0.25 A 2h = 0.5 A 3h = 1.0 A 4h = 1.5 A 5h = 2.0 A 6h = 2.5 A 7h = 3.0 A 8h = 3.5 A 9h = 4.0 A Ah = 4.5 A Bh = 5.0 A Ch = 5.5 A Dh = 6.0 A Eh = 7.0 A Fh = 8.0 A 16-14 IPD_CLK_FREQ R/W 0h IPD clock frequency 0h = 50 Hz 1h = 100 Hz 2h = 250 Hz 3h = 500 Hz 4h = 1000 Hz 5h = 2000 Hz 6h = 5000 Hz 7h = 10000 Hz MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-19. MOTOR_STARTUP1 Register Field Descriptions (continued) Bit Field Type Reset Description 13-9 IPD_CURR_THR R/W 0h IPD current threshold 0h = 0.25 A 1h = 0.5 A 2h = 0.75 A 3h = 1.0 A 4h = 1.25 A 5h = 1.5 A 6h = 2.0 A 7h = 2.5 A 8h = 3.0 A 9h = 3.667 A Ah = 4.0 A Bh = 4.667 A Ch = 5.0 A Dh = 5.333 A Eh = 6.0 A Fh = 6.667 A 10h = 7.333 A 11h = 8.0 A 12h = Not Applicable 13h = Not Applicable 14h = Not Applicable 15h = Not Applicable 16h = Not Applicable 17h = Not Applicable 18h = Not Applicable 19h = Not Applicable 1Ah = Not Applicable 1Bh = Not Applicable 1Ch = Not Applicable 1Dh = Not Applicable 1Eh = Not Applicable 1Fh = Not Applicable

8 IPD_RLS_MODE R/W 0h IPD release mode

0h = Brake 1h = Tristate 7-6 IPD_ADV_ANGLE R/W 0h IPD advance angle 0h = 0° 1h = 30° 2h = 60° 3h = 90° www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: MCF8316D

Table 6-19. MOTOR_STARTUP1 Register Field Descriptions (continued) Bit Field Type Reset Description 5-4 IPD_REPEAT R/W 0h Number of times IPD is executed 0h = 1 time 1h = 2 times 2h = 3 times 3h = 4 times

3 RESERVED R 0h Reserved

2 IQ_RAMP_EN R/W 0h Iq reference ramp down during transition from open loop to closed

0h = Disable Iq ramp down 1h = Enable Iq ramp down

1 ACTIVE_BRAKE_EN R/W 0h Enable active braking

0h = Disable Active Brake 1h = Enable Active Brake

0 REV_DRV_CONFIG R/W 0h Choose between forward and reverse drive setting for reverse drive

0h = Open loop current, A1, A2 based on forward drive 1h = Open loop current, A1, A2 based on reverse drive MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.4 MOTOR_STARTUP2 Register (Offset = 86h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in Figure 6-70 and described in Table 6-20. Return to the Summary Table. Register to configure motor startup settings2 Figure 6-70. MOTOR_STARTUP2 Register 31 30 29 28 27 26 25 24 PARITY OL_ILIMIT OL_ACC_A1 R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 OL_ACC_A1 OL_ACC_A2 AUTO_HANDO FF_EN OPN_CL_HANDOFF_THR R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 OPN_CL_HANDOFF_THR ALIGN_ANGLE R/W-0h R/W-0h 7 6 5 4 3 2 1 0 SLOW_FIRST_CYC_FREQ FIRST_CYCLE _FREQ_SEL THETA_ERROR_RAMP_RATE R/W-0h R/W-0h R/W-0h Table 6-20. MOTOR_STARTUP2 Register Field Descriptions Bit Field Type Reset Description 30-27 OL_ILIMIT R/W 0h Open loop current limit 0h = 0.125 A 1h = 0.25 A 2h = 0.5 A 3h = 1.0 A 4h = 1.5 A 5h = 2.0 A 6h = 2.5 A 7h = 3.0 A 8h = 3.5 A 9h = 4.0 A Ah = 4.5 A Bh = 5.0 A Ch = 5.5 A Dh = 6.0 A Eh = 7.0 A Fh = 8.0 A www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: MCF8316D

Table 6-20. MOTOR_STARTUP2 Register Field Descriptions (continued) Bit Field Type Reset Description 26-23 OL_ACC_A1 R/W 0h Open loop acceleration coefficient A1 0h = 0.1 Hz/s 1h = 0.5 Hz/s 2h = 1 Hz/s 3h = 2.5 Hz/s 4h = 5 Hz/s 5h = 10 Hz/s 6h = 25 Hz/s 7h = 50 Hz/s 8h = 75 Hz/s 9h = 100 Hz/s Ah = 250 Hz/s Bh = 500 Hz/s Ch = 750 Hz/s Dh = 1000 Hz/s Eh = 5000 Hz/s Fh = 10000 Hz/s 22-19 OL_ACC_A2 R/W 0h Open loop acceleration coefficient A2 0h = 0.0 Hz/s2 1h = 0.5 Hz/s2 2h = 1 Hz/s2 3h = 2.5 Hz/s2 4h = 5 Hz/s2 5h = 10 Hz/s2 6h = 25 Hz/s2 7h = 50 Hz/s2 8h = 75 Hz/s2 9h = 100 Hz/s2 Ah = 250 Hz/s2 Bh = 500 Hz/s2 Ch = 750 Hz/s2 Dh = 1000 Hz/s2 Eh = 5000 Hz/s2 Fh = 10000 Hz/s2

18 AUTO_HANDOFF_EN R/W 0h Auto handoff enable

0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR) 1h = Enable Auto Handoff MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-20. MOTOR_STARTUP2 Register Field Descriptions (continued) Bit Field Type Reset Description 17-13 OPN_CL_HANDOFF_TH R R/W 0h Open to closed loop handoff threshold (% of MAX_SPEED) 0h = 1% 1h = 2% 2h = 3% 3h = 4% 4h = 5% 5h = 6% 6h = 7% 7h = 8% 8h = 9% 9h = 10% Ah = 11% Bh = 12% Ch = 13% Dh = 14% Eh = 15% Fh = 16% 10h = 17% 11h = 18% 12h = 19% 13h = 20% 14h = 22.5% 15h = 25% 16h = 27.5% 17h = 30% 18h = 32.5% 19h = 35% 1Ah = 37.5% 1Bh = 40% 1Ch = 42.5% 1Dh = 45% 1Eh = 47.5% 1Fh = 50% www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: MCF8316D

Table 6-20. MOTOR_STARTUP2 Register Field Descriptions (continued) Bit Field Type Reset Description 12-8 ALIGN_ANGLE R/W 0h Align angle 0h = 0° 1h = 10° 2h = 20° 3h = 30° 4h = 45° 5h = 60° 6h = 70° 7h = 80° 8h = 90° 9h = 110° Ah = 120° Bh = 135° Ch = 150° Dh = 160° Eh = 170° Fh = 180° 10h = 190° 11h = 210° 12h = 225° 13h = 240° 14h = 250° 15h = 260° 16h = 270° 17h = 280° 18h = 290° 19h = 315° 1Ah = 330° 1Bh = 340° 1Ch = 350° 1Dh = Not Applicable 1Eh = Not Applicable 1Fh = Not Applicable MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-20. MOTOR_STARTUP2 Register Field Descriptions (continued) Bit Field Type Reset Description 7-4 SLOW_FIRST_CYC_FRE Q R/W 0h Frequency of first cycle in open loop start-up (% of MAX_SPEED) 0h = 0.1% 1h = 0.3% 2h = 0.5% 3h = 0.7% 4h = 1.0% 5h = 1.5% 6h = 2.0% 7h = 2.5% 8h = 3.0% 9h = 4.0% Ah = 5.0% Bh = 7.5% Ch = 10.0% Dh = 15% Eh = 20% Fh = 25%

3 FIRST_CYCLE_FREQ_S

R/W 0h First cycle frequency in open loop for align, double align and IPD start-up 0h = 0 Hz 1h = Defined by SLOW_FIRST_CYC_FREQ 2-0 THETA_ERROR_RAMP_ RATE R/W 0h Ramp rate for reducing difference between estimated theta and open loop theta 0h = 0.01 deg/ms 1h = 0.05 deg/ms 2h = 0.1 deg/ms 3h = 0.15 deg/ms 4h = 0.2 deg/ms 5h = 0.5 deg/ms 6h = 1 deg/ms 7h = 2 deg/ms www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: MCF8316D

6.7.1.5 CLOSED_LOOP1 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in Figure 6-71 and described in Table 6-21. Return to the Summary Table. Register to configure close loop settings1 Figure 6-71. CLOSED_LOOP1 Register 31 30 29 28 27 26 25 24 PARITY OVERMODULA TION_ENABLE CL_ACC RESERVED R/W-0h R/W-0h R/W-0h R-0h 23 22 21 20 19 18 17 16 CL_DEC PWM_FREQ_OUT R/W-0h R/W-0h 15 14 13 12 11 10 9 8 PWM_FREQ_O UT PWM_MODE FG_SEL FG_DIV R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 FG_CONFIG FG_BEMF_THR AVS_EN DEADTIME_CO MP_EN RESERVED LOW_SPEED_ RECIRC_BRAK E_EN R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h Table 6-21. CLOSED_LOOP1 Register Field Descriptions Bit Field Type Reset Description

30 OVERMODULATION_EN

R/W 0h Enable overmodulation 0h = Disable overmodulation 1h = Enable overmodulation MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-21. CLOSED_LOOP1 Register Field Descriptions (continued) Bit Field Type Reset Description 29-25 CL_ACC R/W 0h Closed loop acceleration (Speed mode: Hz/s Power mode: deciWatts/s Torque mode: centiA/s duty cycle mode: milliUnit/s) deciWatt: 0.1W centiA: 0.01A milliUnit: 0.001% 0h = 0.5 1h = 1 2h = 2.5 3h = 5 4h = 7.5 5h = 10 6h = 20 7h = 40 8h = 60 9h = 80 Ah = 100 Bh = 200 Ch = 300 Dh = 400 Eh = 500 Fh = 600 10h = 700 11h = 800 12h = 900 13h = 1000 14h = 2000 15h = 4000 16h = 6000 17h = 8000 18h = 10000 19h = 20000 1Ah = 30000 1Bh = 40000 1Ch = 50000 1Dh = 60000 1Eh = 70000 1Fh = No limit

24 RESERVED R 0h Reserved

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Table 6-21. CLOSED_LOOP1 Register Field Descriptions (continued) Bit Field Type Reset Description 23-19 CL_DEC R/W 0h Closed loop deceleration (Speed mode: Hz/s Power mode: deciWatts/s Torque mode: centiA/s duty cycle mode: milliUnit/s) If AVS is enabled in speed or power mode, the current is clamped to 0 only if negative iqRef is set by outer PI (speed/power) loop deciWatt: 0.1W centiA: 0.01A milliUnit: 0.001% 0h = 0.5 1h = 1 2h = 2.5 3h = 5 4h = 7.5 5h = 10 6h = 20 7h = 40 8h = 60 9h = 80 Ah = 100 Bh = 200 Ch = 300 Dh = 400 Eh = 500 Fh = 600 10h = 700 11h = 800 12h = 900 13h = 1000 14h = 2000 15h = 4000 16h = 6000 17h = 8000 18h = 10000 19h = 20000 1Ah = 30000 1Bh = 40000 1Ch = 50000 1Dh = 60000 1Eh = 70000 1Fh = No limit MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-21. CLOSED_LOOP1 Register Field Descriptions (continued) Bit Field Type Reset Description 18-15 PWM_FREQ_OUT R/W 0h PWM output frequency 0h = 10 kHz 1h = 15 kHz 2h = 20 kHz 3h = 25 kHz 4h = 30 kHz 5h = 35 kHz 6h = 40 kHz 7h = 45 kHz 8h = 50 kHz 9h = 55 kHz Ah = 60 kHz Bh = Not Applicable Ch = Not Applicable Dh = Not Applicable Eh = Not Applicable Fh = Not Applicable

14 PWM_MODE R/W 0h PWM modulation

0h = Continuous Space Vector Modulation 1h = Discontinuous Space Vector Modulation 13-12 FG_SEL R/W 0h FG select 0h = Output FG in ISD, open loop and closed loop 1h = Output FG in only closed loop 2h = Output FG in open loop for the first try. 3h = Not Applicable 11-8 FG_DIV R/W 0h FG division factor 0h = 3x electrical speed 1h = Divide by 1 (2-pole motor mechanical speed) 2h = Divide by 2 (4-pole motor mechanical speed) 3h = Divide by 3 (6-pole motor mechanical speed) 4h = Divide by 4 (8-pole motor mechanical speed) ... Fh = Divide by 15 (30-pole motor mechanical speed) 7 FG_CONFIG R/W 0h FG output configuration. BEMF threshold defined by FG_BEMF_THR 0h = FG active as long as motor is driven 1h = FG active till BEMF drops below BEMF threshold www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: MCF8316D

Table 6-21. CLOSED_LOOP1 Register Field Descriptions (continued) Bit Field Type Reset Description 6-4 FG_BEMF_THR R/W 0h FG output BEMF threshold 0h = +/- 1mV 1h = +/- 2mV 2h = +/- 5mV 3h = +/- 10mV 4h = +/- 20mV 5h = +/- 30mV 6h = Not Applicable 7h = Not Applicable

3 AVS_EN R/W 0h AVS enable

0h = Disable 1h = Enable

2 DEADTIME_COMP_EN R/W 0h Deadtime compensation enable

0h = Disable 1h = Enable

1 RESERVED R 0h Reserved

0 LOW_SPEED_RECIRC_B

RAKE_EN R/W 0h Stop mode applied when stop mode is recirculation brake and motor in align or open loop state 0h = Hi-z 1h = Low Side Brake MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.6 CLOSED_LOOP2 Register (Offset = 8Ah) [Reset = 00000000h]

CLOSED_LOOP2 is shown in Figure 6-72 and described in Table 6-22. Return to the Summary Table. Register to configure close loop settings2 Figure 6-72. CLOSED_LOOP2 Register 31 30 29 28 27 26 25 24 PARITY MTR_STOP MTR_STOP_BRK_TIME R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 ACT_SPIN_THR BRAKE_SPEED_THRESHOLD R/W-0h R/W-0h 15 14 13 12 11 10 9 8 MOTOR_RES R/W-0h 7 6 5 4 3 2 1 0 MOTOR_IND R/W-0h Table 6-22. CLOSED_LOOP2 Register Field Descriptions Bit Field Type Reset Description 30-28 MTR_STOP R/W 0h Motor stop mode 0h = Hi-z 1h = Recirculation Stop 2h = Low side braking 3h = High side braking 4h = Active spin down 5h = Not Applicable 6h = Not Applicable 7h = Not Applicable www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: MCF8316D

Table 6-22. CLOSED_LOOP2 Register Field Descriptions (continued) Bit Field Type Reset Description 27-24 MTR_STOP_BRK_TIME R/W 0h Brake time during motor stop 0h = 1 ms 1h = 1 ms 2h = 1 ms 3h = 1 ms 4h = 1 ms 5h = 5 ms 6h = 10 ms 7h = 50 ms 8h = 100 ms 9h = 250 ms Ah = 500 ms Bh = 1000 ms Ch = 2500 ms Dh = 5000 ms Eh = 10000 ms Fh = 15000 ms 23-20 ACT_SPIN_THR R/W 0h Speed threshold for active spin down (% of MAX_SPEED) 0h = 100 % 1h = 90 % 2h = 80 % 3h = 70 % 4h = 60% 5h = 50 % 6h = 45 % 7h = 40 % 8h = 35 % 9h = 30 % Ah = 25 % Bh = 20 % Ch = 15 % Dh = 10 % Eh = 5 % Fh = 2.5 % MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-22. CLOSED_LOOP2 Register Field Descriptions (continued) Bit Field Type Reset Description 19-16 BRAKE_SPEED_THRES HOLD R/W 0h Speed threshold for BRAKE pin and Motor stop (Low side Braking or High Side Braking or Align Braking) (% of MAX_SPEED) 0h = 100 % 1h = 90 % 2h = 80 % 3h = 70 % 4h = 60% 5h = 50 % 6h = 45 % 7h = 40 % 8h = 35 % 9h = 30 % Ah = 25 % Bh = 20 % Ch = 15 % Dh = 10 % Eh = 5 % Fh = 2.5 % 15-8 MOTOR_RES R/W 0h 8-bit values for motor phase resistance. See Table 6-2 for values of phase resistance 7-0 MOTOR_IND R/W 0h 8-bit values for motor phase inductance. See Table 6-3 for values of phase inductance www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: MCF8316D

6.7.1.7 CLOSED_LOOP3 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP3 is shown in Figure 6-73 and described in Table 6-23. Return to the Summary Table. Register to configure close loop settings3 Figure 6-73. CLOSED_LOOP3 Register 31 30 29 28 27 26 25 24 PARITY MOTOR_BEMF_CONST R/W-0h R/W-0h 23 22 21 20 19 18 17 16 MOTOR_BEMF _CONST CURR_LOOP_KP R/W-0h R/W-0h 15 14 13 12 11 10 9 8 CURR_LOOP_KP CURR_LOOP_KI R/W-0h R/W-0h 7 6 5 4 3 2 1 0 CURR_LOOP_KI SPD_LOOP_KP R/W-0h R/W-0h Table 6-23. CLOSED_LOOP3 Register Field Descriptions Bit Field Type Reset Description 30-23 MOTOR_BEMF_CONST R/W 0h 8-bit values for motor BEMF Constant. See Table 6-4 for values of BEMF constant 22-13 CURR_LOOP_KP R/W 0h 10-bit value for current Iq and Id loop Kp. Kp = 8LSB of CURR_LOOP_KP / 10^2MSB of CURR_LOOP_KP. Set to 0 for auto calculation of current Kp and Ki 12-3 CURR_LOOP_KI R/W 0h 10-bit value for current Iq and Id loop Ki. Ki = 1000 * 8LSB of CURR_LOOP_KI / 10^2MSB of CURR_LOOP_KI. Set to 0 for auto calculation of current Kp and Ki 2-0 SPD_LOOP_KP R/W 0h 3 MSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.8 CLOSED_LOOP4 Register (Offset = 8Eh) [Reset = 00000000h]

CLOSED_LOOP4 is shown in Figure 6-74 and described in Table 6-24. Return to the Summary Table. Register to configure close loop settings4 Figure 6-74. CLOSED_LOOP4 Register 31 30 29 28 27 26 25 24 PARITY SPD_LOOP_KP R/W-0h R/W-0h 23 22 21 20 19 18 17 16 SPD_LOOP_KI R/W-0h 15 14 13 12 11 10 9 8 SPD_LOOP_KI MAX_SPEED R/W-0h R/W-0h 7 6 5 4 3 2 1 0 MAX_SPEED R/W-0h Table 6-24. CLOSED_LOOP4 Register Field Descriptions Bit Field Type Reset Description 30-24 SPD_LOOP_KP R/W 0h 7 LSB bits for speed loop Kp. Kp = 0.01 * 8LSB of SPD_LOOP_KP / 10^2MSB of SPD_LOOP_KP 23-14 SPD_LOOP_KI R/W 0h 10 bit value for speed loop Ki. Ki = 0.1 * 8LSB of SPD_LOOP_KI / 10^2MSB of SPD_LOOP_KI 13-0 MAX_SPEED R/W 0h 14-bit value for setting maximum motor speed in electrical Hz. Maximum motor electrical speed (Hz): {MAX_SPEED/6} For example: if MAX_SPEED is 0x2710, then maximum motor speed (Hz) = 10000(0x2710)/6 = 1666 Hz www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: MCF8316D

6.7.1.9 REF_PROFILES1 Register (Offset = 94h) [Reset = 00000000h]

REF_PROFILES1 is shown in Figure 6-75 and described in Table 6-25. Return to the Summary Table. Register to configure Reference profile1 Figure 6-75. REF_PROFILES1 Register 31 30 29 28 27 26 25 24 PARITY REF_PROFILE_CONFIG DUTY_ON1 R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 DUTY_ON1 DUTY_OFF1 R/W-0h R/W-0h 15 14 13 12 11 10 9 8 DUTY_OFF1 DUTY_CLAMP1 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 DUTY_CLAMP1 DUTY_A R/W-0h R/W-0h Table 6-25. REF_PROFILES1 Register Field Descriptions Bit Field Type Reset Description 30-29 REF_PROFILE_CONFIG R/W 0h Configuration for reference profiles 0h = Reference/Equation 1h = Linear Profile 2h = Staircase Profile 3h = Forward-Reverse Profile 28-21 DUTY_ON1 R/W 0h Turn-on duty cycle (%) = {(DUTY_ON1/256)*100} 20-13 DUTY_OFF1 R/W 0h Turn-off duty cycle (%) = {(DUTY_OFF1/256)*100} 12-5 DUTY_CLAMP1 R/W 0h Duty cycle for clamping speed (%) = {(DUTY_CLAMP1/256)*100} 4-0 DUTY_A R/W 0h 5 MSB bits for duty cycle A MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.10 REF_PROFILES2 Register (Offset = 96h) [Reset = 00000000h]

REF_PROFILES2 is shown in Figure 6-76 and described in Table 6-26. Return to the Summary Table. Register to configure Reference profile2 Figure 6-76. REF_PROFILES2 Register 31 30 29 28 27 26 25 24 PARITY DUTY_A DUTY_B R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 DUTY_B DUTY_C R/W-0h R/W-0h 15 14 13 12 11 10 9 8 DUTY_C DUTY_D R/W-0h R/W-0h 7 6 5 4 3 2 1 0 DUTY_D DUTY_E R/W-0h R/W-0h Table 6-26. REF_PROFILES2 Register Field Descriptions Bit Field Type Reset Description 30-28 DUTY_A R/W 0h 3 LSB bits for duty cycle A Duty cycle A (%) = {(DUTY_A/256)*100} 27-20 DUTY_B R/W 0h Duty cycle B (%) = {(DUTY_B/256)*100} 19-12 DUTY_C R/W 0h Duty cycle C (%) = {(DUTY_C/256)*100} 11-4 DUTY_D R/W 0h Duty cycle D (%) = {(DUTY_D/256)*100} 3-0 DUTY_E R/W 0h 4 MSB bits for Duty cycle E www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: MCF8316D

6.7.1.11 REF_PROFILES3 Register (Offset = 98h) [Reset = 00000000h]

REF_PROFILES3 is shown in Figure 6-77 and described in Table 6-27. Return to the Summary Table. Register to configure Reference profile3 Figure 6-77. REF_PROFILES3 Register 31 30 29 28 27 26 25 24 PARITY DUTY_E DUTY_ON2 R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 DUTY_ON2 DUTY_OFF2 R/W-0h R/W-0h 15 14 13 12 11 10 9 8 DUTY_OFF2 DUTY_CLAMP2 R/W-0h R/W-0h 7 6 5 4 3 2 1 0 DUTY_CLAMP2 DUTY_HYS RESERVED R/W-0h R/W-0h R-0h Table 6-27. REF_PROFILES3 Register Field Descriptions Bit Field Type Reset Description 30-27 DUTY_E R/W 0h 4 LSB bits for Duty cycle E Duty cycle E (%) = {(DUTY_E/256)*100} 26-19 DUTY_ON2 R/W 0h Turn-on duty cycle (%) = {(DUTY_ON2/256)*100} 18-11 DUTY_OFF2 R/W 0h Turn-off duty cycle (%) = {(DUTY_OFF2/256)*100} 10-3 DUTY_CLAMP2 R/W 0h Duty cycle for clamping speed (%) = {(DUTY_CLAMP1/256)*100} 2-1 DUTY_HYS R/W 0h Duty hysteresis for speed reference mode 0h = 0% 1h = 1% 2h = 2% 3h = 3%

0 RESERVED R 0h Reserved

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6.7.1.12 REF_PROFILES4 Register (Offset = 9Ah) [Reset = 00000000h]

REF_PROFILES4 is shown in Figure 6-78 and described in Table 6-28. Return to the Summary Table. Register to configure Reference profile4 Figure 6-78. REF_PROFILES4 Register 31 30 29 28 27 26 25 24 PARITY REF_OFF1 R/W-0h R/W-0h 23 22 21 20 19 18 17 16 REF_OFF1 REF_CLAMP1 R/W-0h R/W-0h 15 14 13 12 11 10 9 8 REF_CLAMP1 REF_A R/W-0h R/W-0h 7 6 5 4 3 2 1 0 REF_A REF_B R/W-0h R/W-0h Table 6-28. REF_PROFILES4 Register Field Descriptions Bit Field Type Reset Description 30-23 REF_OFF1 R/W 0h Turn off reference (% of Maximum Reference) = {(REF_OFF1/256)*100} 22-15 REF_CLAMP1 R/W 0h Clamp Ref 1 (% of Maximum Reference) = {(REF_CLAMP1/256)*100} 14-7 REF_A R/W 0h Ref A (% of Maximum Reference) = {(REF_A/256)*100} 6-0 REF_B R/W 0h 7 MSB of REF_B configuration www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: MCF8316D

6.7.1.13 REF_PROFILES5 Register (Offset = 9Ch) [Reset = 00000000h]

REF_PROFILES5 is shown in Figure 6-79 and described in Table 6-29. Return to the Summary Table. Register to configure Reference profile5 Figure 6-79. REF_PROFILES5 Register 31 30 29 28 27 26 25 24 PARITY REF_B REF_C R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 REF_C REF_D R/W-0h R/W-0h 15 14 13 12 11 10 9 8 REF_D REF_E R/W-0h R/W-0h 7 6 5 4 3 2 1 0 REF_E MIN_DUTY VOLTAGE_MODE_CONFIG DUTY_COMMA ND_FILTER RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R-0h Table 6-29. REF_PROFILES5 Register Field Descriptions Bit Field Type Reset Description 30 REF_B R/W 0h 1 LSB of REF_B configuration. Ref B(% of Maximum Reference) = {(REF_B/256)*100} 29-22 REF_C R/W 0h Ref C (% of Maximum Reference) = {(REF_C/256)*100} 21-14 REF_D R/W 0h Ref D (% of Maximum Reference) = {(REF_D/256)*100} 13-6 REF_E R/W 0h Ref E(% of Maximum Reference) = {(REF_E/256)*100} 5-4 MIN_DUTY R/W 0h Minimum input duty to start driving the motor 0h = 1 % 1h = 3 % 2h = 5 % 3h = 10 % 3-2 VOLTAGE_MODE_CONFI G R/W 0h Voltage mode configuration for reference profiles 0h = User defined reference modes throughout the duty range 1h = Voltage mode if input duty > DUTY_C + DUTY_HYST; configured reference mode if input duty < DUTY_C - DUTY_HYST 2h = configured reference mode if input duty > DUTY_C + DUTY_HYST; voltage mode if input duty < DUTY_C - DUTY_HYST 3h = Not Applicable

1 DUTY_COMMAND_FILTE

R R/W 0h Speed pin input filter 0h = Filter on Speed pin is disabled 1h = Filter on Speed pin is enabled (0.4%) SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.1.14 REF_PROFILES6 Register (Offset = 9Eh) [Reset = 00000000h]

REF_PROFILES6 is shown in Figure 6-80 and described in Table 6-30. Return to the Summary Table. Register to configure Reference profile6 Figure 6-80. REF_PROFILES6 Register 31 30 29 28 27 26 25 24 PARITY REF_OFF2 R/W-0h R/W-0h 23 22 21 20 19 18 17 16 REF_OFF2 REF_CLAMP2 R/W-0h R/W-0h 15 14 13 12 11 10 9 8 REF_CLAMP2 RESERVED R/W-0h R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 6-30. REF_PROFILES6 Register Field Descriptions Bit Field Type Reset Description 30-23 REF_OFF2 R/W 0h Turn off Ref (% of Maximum Reference)) = {(REF_OFF2/256)*100} 22-15 REF_CLAMP2 R/W 0h Clamp Ref 2 (% of Maximum Reference) = {(REF_CLAMP2/256)*100} 14-0 RESERVED R 0h Reserved

6.7.2 Fault_Configuration Registers

Table 6-31 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in Table 6-31 should be considered as reserved locations and the register contents should not be modified. Table 6-31. FAULT_CONFIGURATION Registers Offset Acronym Register Name Section 90h FAULT_CONFIG1 Fault Configuration1 Section 6.7.2.1 92h FAULT_CONFIG2 Fault Configuration2 Section 6.7.2.2 Complex bit access types are encoded to fit into small table cells. Table 6-32 shows the codes that are used for access types in this section. Table 6-32. Fault_Configuration Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: MCF8316D

Table 6-32. Fault_Configuration Access Type Codes (continued) Access Type Code Description -n Value after reset or the default value MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.2.1 FAULT_CONFIG1 Register (Offset = 90h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in Figure 6-81 and described in Table 6-33. Return to the Summary Table. Register to configure fault settings1 Figure 6-81. FAULT_CONFIG1 Register 31 30 29 28 27 26 25 24 PARITY ILIMIT HW_LOCK_ILIMIT R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 HW_LOCK_ILI MIT LOCK_ILIMIT EEP_FAULT_M ODE LOCK_ILIMIT_MODE R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 LOCK_ILIMIT_ MODE LOCK_ILIMIT_DEG LCK_RETRY R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 LCK_RETRY CRC_ERR_MO DE MTR_LCK_MODE IPD_TIMEOUT _FAULT_EN IPD_FREQ_FA ULT_EN SATURATION_ FLAGS_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 6-33. FAULT_CONFIG1 Register Field Descriptions Bit Field Type Reset Description 30-27 ILIMIT R/W 0h Current limit for Iq axis (torque) current reference in closed loop 0h = 0.125 A 1h = 0.25 A 2h = 0.5 A 3h = 1.0 A 4h = 1.5 A 5h = 2.0 A 6h = 2.5 A 7h = 3.0 A 8h = 3.5 A 9h = 4.0 A Ah = 4.5 A Bh = 5.0 A Ch = 5.5 A Dh = 6.0 A Eh = 7.0 A Fh = 8.0 A www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: MCF8316D

Table 6-33. FAULT_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 26-23 HW_LOCK_ILIMIT R/W 0h Comparator based lock detection current threshold 0h = 0.125 A 1h = 0.25 A 2h = 0.5 A 3h = 1.0 A 4h = 1.5 A 5h = 2.0 A 6h = 2.5 A 7h = 3.0 A 8h = 3.5 A 9h = 4.0 A Ah = 4.5 A Bh = 5.0 A Ch = 5.5 A Dh = 6.0 A Eh = 7.0 A Fh = 8.0 A 22-19 LOCK_ILIMIT R/W 0h ADC based lock detection current threshold 0h = 0.125 A 1h = 0.25 A 2h = 0.5 A 3h = 1.0 A 4h = 1.5 A 5h = 2.0 A 6h = 2.5 A 7h = 3.0 A 8h = 3.5 A 9h = 4.0 A Ah = 4.5 A Bh = 5.0 A Ch = 5.5 A Dh = 6.0 A Eh = 7.0 A Fh = 8.0 A

18 EEP_FAULT_MODE R/W 0h Fault response type for EEPROM fault

0h = Latched Fault 1h = Report only fault MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-33. FAULT_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 17-15 LOCK_ILIMIT_MODE R/W 0h Lock current limit mode 0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active 6h = Ilimit lock detection current limit is in report only but no action is taken; nFAULT active 7h = ILIMIT LOCK is disabled 14-11 LOCK_ILIMIT_DEG R/W 0h Lock current limit detection deglitch time 0h = No deglitch 1h = 0.1 ms 2h = 0.2 ms 3h = 0.5 ms 4h = 1 ms 5h = 2.5 ms 6h = 5 ms 7h = 7.5 ms 8h = 10 ms 9h = 25 ms Ah = 50 ms Bh = 75 ms Ch = 100 ms Dh = 200 ms Eh = 500 ms Fh = 1000 ms www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: MCF8316D

Table 6-33. FAULT_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 10-7 LCK_RETRY R/W 0h Lock detection retry time 0h = 300 ms 1h = 500 ms 2h = 1 s 3h = 2 s 4h = 3 s 5h = 4 s 6h = 5 s 7h = 6 s 8h = 7 s 9h = 8 s Ah = 9 s Bh = 10 s Ch = 11 s Dh = 12 s Eh = 13 s Fh = 14 s

6 CRC_ERR_MODE R/W 0h CRC (in I2C communication) error mode

0h = CRC error on I2C causes latched fault; nFAULT active; Gate driver is tristated 1h = CRC error on I2C causes report only but no action is taken; nFAULT is active 5-3 MTR_LCK_MODE R/W 0h Motor lock mode 0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active 6h = Motor lock detection current limit is in report only but no action is taken; nFAULT active 7h = MTR LOCK is disabled MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-33. FAULT_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description

2 IPD_TIMEOUT_FAULT_E

N R/W 0h IPD timeout fault enable 0h = Disable 1h = Enable

1 IPD_FREQ_FAULT_EN R/W 0h IPD frequency fault enable

0h = Disable 1h = Enable

0 SATURATION_FLAGS_E

N R/W 0h Enable indication of current loop and speed loop saturation 0h = Disable 1h = Enable www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: MCF8316D

6.7.2.2 FAULT_CONFIG2 Register (Offset = 92h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in Figure 6-82 and described in Table 6-34. Return to the Summary Table. Register to configure fault settings2 Figure 6-82. FAULT_CONFIG2 Register 31 30 29 28 27 26 25 24 PARITY LOCK1_EN LOCK2_EN LOCK3_EN LOCK_ABN_SPEED ABNORMAL_B EMF_THR R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 ABNORMAL_BEMF_THR NO_MTR_THR HW_LOCK_ILIMIT_MODE R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 HW_LOCK_ILIMIT_DEG VOLTAGE_HYSTERESIS MIN_VM_MOTOR R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 MIN_VM_MOD E MAX_VM_MOTOR MAX_VM_MOD E AUTO_RETRY_TIMES R/W-0h R/W-0h R/W-0h R/W-0h Table 6-34. FAULT_CONFIG2 Register Field Descriptions Bit Field Type Reset Description

30 LOCK1_EN R/W 0h Lock 1 (Abnormal Speed) Enable

0h = Disable 1h = Enable

29 LOCK2_EN R/W 0h Lock 2 (Abnormal BEMF) Enable

0h = Disable 1h = Enable

28 LOCK3_EN R/W 0h Lock 3 (No Motor) Enable

0h = Disable 1h = Enable 27-25 LOCK_ABN_SPEED R/W 0h Abnormal speed lock threshold (% of MAX_SPEED) 0h = 130% 1h = 140% 2h = 150% 3h = 160% 4h = 170% 5h = 180% 6h = 190% 7h = 200% MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-34. FAULT_CONFIG2 Register Field Descriptions (continued) Bit Field Type Reset Description 24-22 ABNORMAL_BEMF_THR R/W 0h Abnormal BEMF lock threshold (% of expected BEMF) 0h = 40% 1h = 45% 2h = 50% 3h = 55% 4h = 60% 5h = 65% 6h = 67.5% 7h = 70% 21-19 NO_MTR_THR R/W 0h No motor lock threshold 0h = 0.0375 A 1h = 0.075 A 2h = 0.1A 3h = 0.125 A 4h = 0.25 A 5h = 0.5 A 6h = 0.75 A 7h = 1.0 A 18-16 HW_LOCK_ILIMIT_MODE R/W 0h Hardware lock current limit mode 0h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low side brake mode (All low side FETs are turned ON) 2h = Hardware Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high side brake mode (All high side FETs are turned ON) 3h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFAULT active 4h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFAULT active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in high side brake mode (All high side FETs are turned ON); nFAULT active 6h = Hardware Ilimit lock detection current limit is in report only but no action is taken; nFAULT active 7h = HARDWARE ILIMIT LOCK is disabled www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: MCF8316D

Table 6-34. FAULT_CONFIG2 Register Field Descriptions (continued) Bit Field Type Reset Description 15-13 HW_LOCK_ILIMIT_DEG R/W 0h Hardware lock current limit detection deglitch time 0h = No deglitch 1h = 1 µs 2h = 2 µs 3h = 3 µs 4h = 4 µs 5h = 5 µs 6h = 6 µs 7h = 7 µs 12-11 VOLTAGE_HYSTERESIS R/W 0h Hysteresis for controller overvoltage and undervoltage faults. Fault triggered at threshold, cleared at threshold ± hysteresis (+ for UV, - for OV). 0h = 0.5V 1h = 1V 2h = 2V 3h = 3V 10-8 MIN_VM_MOTOR R/W 0h Controller under voltage fault threshold - minimum DC bus voltage for running motor 0h = No Limit 1h = 6 V 2h = 7 V 3h = 8 V 4h = 10 V 5h = 14 V 6h = 16 V 7h = 18 V

7 MIN_VM_MODE R/W 0h DC bus (controller) undervoltage fault recovery mode

0h = Latch on Undervoltage 1h = Automatic clear if voltage in bounds 6-4 MAX_VM_MOTOR R/W 0h Controller over voltage fault threshold - maximum DC bus voltage for running motor 0h = No Limit 1h = 18 V 2h = 20 V 3h = 22 V 4h = 28 V 5h = 30 V 6h = 32 V 7h = 34 V

3 MAX_VM_MODE R/W 0h DC bus (controller) overvoltage fault recovery mode

0h = Latch on Overvoltage 1h = Automatic clear if voltage in bounds MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-34. FAULT_CONFIG2 Register Field Descriptions (continued) Bit Field Type Reset Description 2-0 AUTO_RETRY_TIMES R/W 0h Number of automatic retry attempts 0h = No Limit 1h = 2 2h = 3 3h = 5 4h = 7 5h = 10 6h = 15 7h = 20

6.7.3 Hardware_Configuration Registers

Table 6-35 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 6-35 should be considered as reserved locations and the register contents should not be modified. Table 6-35. HARDWARE_CONFIGURATION Registers Offset Acronym Register Name Section A4h PIN_CONFIG Hardware Pin Configuration Section 6.7.3.1 A6h DEVICE_CONFIG1 Device configuration1 Section 6.7.3.2 A8h DEVICE_CONFIG2 Device configuration2 Section 6.7.3.3 AAh PERI_CONFIG1 Peripheral Configuration1 Section 6.7.3.4 ACh GD_CONFIG1 Gate Driver Configuration1 Section 6.7.3.5 AEh GD_CONFIG2 Gate Driver Configuration2 Section 6.7.3.6 Complex bit access types are encoded to fit into small table cells. Table 6-36 shows the codes that are used for access types in this section. Table 6-36. Hardware_Configuration Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: MCF8316D

6.7.3.1 PIN_CONFIG Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG is shown in Figure 6-83 and described in Table 6-37. Return to the Summary Table. Register to configure hardware pins Figure 6-83. PIN_CONFIG Register 31 30 29 28 27 26 25 24 PARITY PWM_DITHER_STEP VDC_FILTER LEAD_ANGLE R/W-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 LEAD_ANGLE MAX_POWER R/W-0h R/W-0h 15 14 13 12 11 10 9 8 MAX_POWER FG_IDLE_CONFIG FG_FAULT_CO NFIG R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 FG_FAULT_CO NFIG ALARM_PIN_E N BRAKE_PIN_M ODE ALIGN_BRAKE _ANGLE_SEL BRAKE_INPUT SPEED_MODE R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 6-37. PIN_CONFIG Register Field Descriptions Bit Field Type Reset Description 30-29 PWM_DITHER_STEP R/W 0h PWM dither slew rate 0h = 1 1h = 2 2h = 5 3h = 10 28-27 VDC_FILTER R/W 0h Vdc(VM) filter coefficient 0h = Disable 1h = Enable with default filter cut-off frequency 2h = Enable with filter cut-off frequency 100Hz 3h = Enable with filter cut-off frequency 1000Hz MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-37. PIN_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 26-22 LEAD_ANGLE R/W 0h Lead angle. In voltage mode, positive value indicates the applied voltage is leading the BEMF, negative value indicates applied voltage is lagging the BEMF. In other modes, positive means negative id reference, negative means positive id reference 0h = 0 deg 1h = 3 deg 2h = 6 deg 3h = 9 deg 4h = 12 deg 5h = 15 deg 6h = 18 deg 7h = 21 deg 8h = 24 deg 9h = 27 deg Ah = 30 deg Bh = 33 deg Ch = 36 deg Dh = 39 deg Eh = 42 deg Fh = 45 deg 10h = -48 deg 11h = -45 deg 12h = -42 deg 13h = -39 deg 14h = -36 deg 15h = -33 deg 16h = -30 deg 17h = -27 deg 18h = -24 deg 19h = -21 deg 1Ah = -18 deg 1Bh = -15 deg 1Ch = -12 deg 1Dh = -9 deg 1Eh = -6 deg 1Fh = -3 deg 21-11 MAX_POWER R/W 0h Maximum power for power loop or power limit. Max power in Watts = (MAX_POWER / 211) * 100 10-9 FG_IDLE_CONFIG R/W 0h FG configuration during motor stopped/idle state 0h = FG continues and end state depends on FG_CONFIG and last state before motor stops 1h = FG is pulled High 2h = FG is pulled Low 3h = FG is pulled High www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: MCF8316D

Table 6-37. PIN_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 8-7 FG_FAULT_CONFIG R/W 0h FG configuration during fault state. BEMF threshold defined by FG_BEMF_THR if FG_CONFIG 1 0h = Use last FG signal when motor was driven 1h = FG is pulled High 2h = FG is pulled Low 3h = FG active till BEMF drops below BEMF threshold

6 ALARM_PIN_EN R/W 0h Enable Alarm pin

0h = Disable 1h = Enable

5 BRAKE_PIN_MODE R/W 0h Brake pin mode

0h = Low side Brake 1h = Align Brake

4 ALIGN_BRAKE_ANGLE_

R/W 0h Select align brake angle 0h = Use last commutation angle before entering align braking 1h = Use ALIGN_ANGLE configuration for align braking 3-2 BRAKE_INPUT R/W 0h Brake pin override 0h = Hardware Pin BRAKE 1h = Override pin and brake / align according to BRAKE_PIN_MODE 2h = Override pin and do not brake / align 3h = Hardware Pin BRAKE 1-0 SPEED_MODE R/W 0h Configure motor control input source 0h = Controlled by analog voltage on SPEED pin 1h = Controlled by duty cycle (PWM) on SPEED pin 2h = Controlled by DIGITAL_SPEED_CTRL value (I2C) 3h = Controlled by frequency on SPEED pin MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.3.2 DEVICE_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]

DEVICE_CONFIG1 is shown in Figure 6-84 and described in Table 6-38. Return to the Summary Table. Register to configure device Figure 6-84. DEVICE_CONFIG1 Register 31 30 29 28 27 26 25 24 PARITY RESERVED DAC_SOx_SEL PWM_DITHER _MODE I2C_TARGET_ADDR R/W-0h R-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 I2C_TARGET_ADDR EEPROM_LOCK_KEY R/W-0h W-0h 15 14 13 12 11 10 9 8 EEPROM_LOCK_KEY W-0h 7 6 5 4 3 2 1 0 EEPROM_LOCK_KEY SLEW_RATE_I2C_PINS PULLUP_ENAB LE BUS_VOLT W-0h R/W-0h R/W-0h R/W-0h Table 6-38. DEVICE_CONFIG1 Register Field Descriptions Bit Field Type Reset Description

30 RESERVED R 0h Reserved

29-28 DAC_SOx_SEL R/W 0h Select between DACOUT2 and SOx channels 0h = DACOUT2 1h = SOA 2h = SOB 3h = SOC

27 PWM_DITHER_MODE R/W 0h PWM dither mode

0h = Triangular Mode 1h = Random Mode 26-20 I2C_TARGET_ADDR R/W 0h I2C target address 19-5 EEPROM_LOCK_KEY W 0h EEPROM lock/unlock key when EEPROM R/W protection is enabled. This bitfield will always read 0 when read. 4-3 SLEW_RATE_I2C_PINS R/W 0h Slew rate control for I2C pins 0h = 4.8 mA 1h = 3.9 mA 2h = 1.86 mA 3h = 30.8 mA

2 PULLUP_ENABLE R/W 0h Internal pull-up enable for nFAULT and FG pins

0h = Disable 1h = Enable www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: MCF8316D

Table 6-38. DEVICE_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 BUS_VOLT R/W 0h Maximum DC bus voltage configuration 0h = 15 V 1h = 30 V 2h = 40 V 3h = Not Applicable MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.3.3 DEVICE_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG2 is shown in Figure 6-85 and described in Table 6-39. Return to the Summary Table. Register to configure device Figure 6-85. DEVICE_CONFIG2 Register 31 30 29 28 27 26 25 24 PARITY INPUT_MAXIMUM_FREQ R/W-0h R/W-0h 23 22 21 20 19 18 17 16 INPUT_MAXIMUM_FREQ R/W-0h 15 14 13 12 11 10 9 8 SLEEP_ENTRY_TIME DYNAMIC_CSA _GAIN_EN DYNAMIC_VOL TAGE_GAIN_E N DEV_MODE PWM_DITHER_DEPTH EXT_CLK_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 EXT_CLK_CONFIG EXT_WDT_EN EXT_WDT_CONFIG EXT_WDT_INP UT_MODE EXT_WDT_FA ULT_MODE R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 6-39. DEVICE_CONFIG2 Register Field Descriptions Bit Field Type Reset Description 30-16 INPUT_MAXIMUM_FREQ R/W 0h Input frequency on speed pin for input reference mode as "controlled by frequency of SPEED pin" that corresponds to 100% duty cycle. Duty cycle = Input frequency / INPUT_MAXIMUM_FREQ 15-14 SLEEP_ENTRY_TIME R/W 0h Device enters sleep mode when input source (SPEED_MODE) is held at or below the sleep entry threshold for SLEEP_ENTRY_TIME 0h = Sleep Entry when SPEED pin remains low for 50 µs 1h = Sleep Entry when SPEED pin remains low for 200 µs 2h = Sleep Entry when SPEED pin remains low for 20 ms 3h = Sleep Entry when SPEED pin remains low for 200 ms

13 DYNAMIC_CSA_GAIN_E

N R/W 0h Adjust CSA gain automatically for optimal current resolution at all current levels 0h = Disable 1h = Enable

12 DYNAMIC_VOLTAGE_GA

IN_EN R/W 0h Adjust voltage gain automatically for optimal voltage resolution at all voltage levels 0h = Disable 1h = Enable

11 DEV_MODE R/W 0h Device mode select

0h = Standby Mode 1h = Sleep Mode www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: MCF8316D

Table 6-39. DEVICE_CONFIG2 Register Field Descriptions (continued) Bit Field Type Reset Description 10-9 PWM_DITHER_DEPTH R/W 0h PWM dither depth 0h = PWM dither disabled 1h = 5% 2h = 7.5% 3h = 10%

8 EXT_CLK_EN R/W 0h Enable external clock mode

0h = Disable 1h = Enable 7-5 EXT_CLK_CONFIG R/W 0h External clock frequency configuration 0h = 8 kHz 1h = 16 kHz 2h = 32 kHz 3h = 64 kHz 4h = 128 kHz 5h = 256 kHz 6h = 512 kHz 7h = 1024 kHz

4 EXT_WDT_EN R/W 0h Enable external watchdog

0h = Disable 1h = Enable 3-2 EXT_WDT_CONFIG R/W 0h Time between watchdog tickles (GPIO/I2C) 0h = 100ms/1s 1h = 200ms/2s 2h = 500ms/5s 3h = 1000ms/10s

1 EXT_WDT_INPUT_MODE R/W 0h External watchdog input source

0h = Watchdog tickle over I2C 1h = Watchdog tickle over GPIO

0 EXT_WDT_FAULT_MOD

E R/W 0h External watchdog fault mode 0h = Report only 1h = Latch with MOSFETs in Hi-Z MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.7.3.4 PERI_CONFIG1 Register (Offset = AAh) [Reset = 00000000h]

PERI_CONFIG1 is shown in Figure 6-86 and described in Table 6-40. Return to the Summary Table. Register to peripheral1 Figure 6-86. PERI_CONFIG1 Register 31 30 29 28 27 26 25 24 PARITY SPREAD_SPE CTRUM_MODU LATION_DIS RESERVED NO_MTR_FLT_ CLOSEDLOOP _DIS ABNORMAL_BEMF_PERSISTE NT_TIME FLUX_WEAK_REF R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 INPUT_REFERENCE_WINDOW BUS_POWER_ LIMIT_ENABLE DIR_INPUT DIR_CHANGE_ MODE SPEED_LIMIT_ ENABLE ACTIVE_BRAK E_SPEED_DEL TA_LIMIT_ENT RY R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY ACTIVE_BRAKE_MOD_INDEX_LIMIT SPEED_RANG E_SEL INPUT_REFER ENCE_MODE R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 INPUT_REFER ENCE_MODE EEPROM_LOCK_MODE RESERVED R/W-0h R/W-0h R-0h Table 6-40. PERI_CONFIG1 Register Field Descriptions Bit Field Type Reset Description

30 SPREAD_SPECTRUM_M

ODULATION_DIS R/W 0h Disable Spread Spectrum Modulation (SSM) 0h = SSM is Enabled 1h = SSM is Disabled

29 RESERVED R 0h Reserved

28 NO_MTR_FLT_CLOSEDL

OOP_DIS R/W 0h Disable No Motor fault in closed loop 0h = Enable no motor fault in closed loop if LOCK2_EN is set to 0x1 1h = Disable No Motor fault in closed loop 27-26 ABNORMAL_BEMF_PER SISTENT_TIME R/W 0h Deglitch time for Abnormal BEMF fault detection 0h = 2 electrical cycles 1h = 500 ms 2h = 1000 ms 3h = 2000 ms 25-24 FLUX_WEAK_REF R/W 0h Reference for flux weakening controller 0h = 70% 1h = 80% 2h = 90% 3h = 95% www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: MCF8316D

Table 6-40. PERI_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 23-22 INPUT_REFERENCE_WI NDOW R/W 0h Disables all control loops when output reaches within the window 0h = Reference window disabled 1h = Reference window of 5% 2h = Reference window of 10% 3h = Reference window of 15%

21 BUS_POWER_LIMIT_EN

R/W 0h Enable bus power limit. Limits input DC bus power to MAX_POWER in all input reference modes except power mode 0h = Disable power limit 1h = Enable power limit 20-19 DIR_INPUT R/W 0h DIR pin override 0h = Hardware Pin DIR 1h = Override DIR pin with clockwise rotation OUTA-OUTB- OUTC 2h = Override DIR pin with counter clockwise rotation OUTA- OUTC-OUTB 3h = Hardware Pin DIR

18 DIR_CHANGE_MODE R/W 0h Response to change of DIR pin status

0h = Follow motor stop options and ISD routine on detecting DIR change 1h = Change the direction through Reverse Drive while continuously driving the motor 17 SPEED_LIMIT_ENABLE R/W 0h Enable motor speed limit. Limits motor speed to MAX_SPEED in all input reference modes except speed mode 0h = Disable speed limit 1h = Enable speed limit 16-13 ACTIVE_BRAKE_SPEED _DELTA_LIMIT_ENTRY R/W 0h Difference between final speed and present speed below which active braking will be applied 0h = Not Applicable 1h = 5% 2h = 10% 3h = 15% 4h = 20% 5h = 25% 6h = 30% 7h = 35% 8h = 40% 9h = 45% Ah = 50% Bh = 60% Ch = 70% Dh = 80% Eh = 90% Fh = 100% MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-40. PERI_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description 12-10 ACTIVE_BRAKE_MOD_I NDEX_LIMIT R/W 0h Modulation index limit below which active braking will be applied 0h = 0% 1h = 40% 2h = 50% 3h = 60% 4h = 70% 5h = 80% 6h = 90% 7h = 100%

9 SPEED_RANGE_SEL R/W 0h Frequency range selection for PWM duty mode reference input

0h = 325Hz to 100kHz 1h = 10Hz to 325Hz 8-7 INPUT_REFERENCE_MO DE R/W 0h Input reference mode used for close loop operation 0h = Control speed (Input is speed reference, scaled to MAX_SPEED) 1h = Control power (Input is power reference, scaled to MAX_POWER) 2h = Control Torque (Input is current reference, scaled to ILIMIT) 3h = Control Modulation Index (Input is modulation index scaled to 100%) 6-5 EEPROM_LOCK_MODE R/W 0h EEPROM lock mode 0h = EEPROM read and write allowed without a passcode 1h = EEPROM read and write need a valid passcode 2h = EEPROM read needs a valid passcode, write is locked permanently 3h = EEPROM read and write is locked permanently 4-0 RESERVED R 0h Reserved www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: MCF8316D

6.7.3.5 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]

GD_CONFIG1 is shown in Figure 6-87 and described in Table 6-41. Return to the Summary Table. Register to configure gated driver settings1 Figure 6-87. GD_CONFIG1 Register 31 30 29 28 27 26 25 24 PARITY RESERVED RESERVED SLEW_RATE RESERVED R/W-0h R-0h R-0h R/W-0h R-0h 23 22 21 20 19 18 17 16 RESERVED RESERVED RESERVED RESERVED OVP_SEL OVP_EN RESERVED OTW_REP R-0h R-0h R-0h R-0h R/W-0h R/W-0h R-0h R/W-0h 15 14 13 12 11 10 9 8 RESERVED RESERVED OCP_DEG RESERVED OCP_LVL OCP_MODE R-0h R-0h R/W-0h R-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CSA_GAIN R-0h R-0h R-0h R-0h R-0h R-0h R/W-0h Table 6-41. GD_CONFIG1 Register Field Descriptions Bit Field Type Reset Description 30-29 RESERVED R 0h Reserved

28 RESERVED R 0h Reserved

27-26 SLEW_RATE R/W 0h Slew rate 0h = Not Applicable 1h = Not Applicable 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs 25-24 RESERVED R 0h Reserved

23 RESERVED R 0h Reserved

22 RESERVED R 0h Reserved

21 RESERVED R 0h Reserved

20 RESERVED R 0h Reserved

19 OVP_SEL R/W 0h Overvoltage level

0h = VM overvoltage level is 34-V 1h = VM overvoltage level is 22-V

18 OVP_EN R/W 0h Enable overvoltage

0h = Overvoltage protection is disabled 1h = Overvoltage protection is enabled

17 RESERVED R 0h Reserved

16 OTW_REP R/W 0h Overtemperature warning reporting

0h = Over temperature warning reporting is disabled 1h = Over temperature warning reporting is enabled

15 RESERVED R 0h Reserved

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Table 6-41. GD_CONFIG1 Register Field Descriptions (continued) Bit Field Type Reset Description

14 RESERVED R 0h Reserved

13-12 OCP_DEG R/W 0h OCP deglitch time 0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.6 µs 2h = OCP deglitch time is 1.2 µs 3h = OCP deglitch time is 1.6 µs

11 RESERVED R 0h Reserved

10 OCP_LVL R/W 0h Overcurrent level

0h = OCP level is 16 A (Typical) 1h = OCP level is 24 A (Typical) 9-8 OCP_MODE R/W 0h OCP fault mode 0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retry after 500ms 2h = Not Applicable 3h = Not Applicable

7 RESERVED R 0h Reserved

6 RESERVED R 0h Reserved

5 RESERVED R 0h Reserved

4 RESERVED R 0h Reserved

2 RESERVED R 0h Reserved

1-0 CSA_GAIN R/W 0h Current sense amplifier's gain (used only if DYNAMIC_CSA_GAIN_EN = 0x0) 0h = CSA gain is 0.15 V/A 1h = CSA gain is 0.3 V/A 2h = CSA gain is 0.6 V/A 3h = CSA gain is 1.2 V/A www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: MCF8316D

6.7.3.6 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]

GD_CONFIG2 is shown in Figure 6-88 and described in Table 6-42. Return to the Summary Table. Register to configure gated driver settings2 Figure 6-88. GD_CONFIG2 Register 31 30 29 28 27 26 25 24 PARITY RESERVED RESERVED RESERVED BUCK_PS_DIS R/W-0h R-0h R-0h R-0h R/W-0h 23 22 21 20 19 18 17 16 BUCK_CL BUCK_SEL BUCK_DIS MIN_ON_TIME RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R-0h 15 14 13 12 11 10 9 8 RESERVED RESERVED R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 6-42. GD_CONFIG2 Register Field Descriptions Bit Field Type Reset Description 29-26 RESERVED R 0h Reserved

25 RESERVED R 0h Reserved

24 BUCK_PS_DIS R/W 0h Buck power sequencing disable

0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled

23 BUCK_CL R/W 0h Buck current limit

0h = Buck regulator current limit is set to 600 mA 1h = Buck regulator current limit is set to 150 mA 22-21 BUCK_SEL R/W 0h Buck output voltage 0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V

20 BUCK_DIS R/W 0h Buck disable

0h = Buck regulator is enabled 1h = Buck regulator is disabled MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-42. GD_CONFIG2 Register Field Descriptions (continued) Bit Field Type Reset Description 19-17 MIN_ON_TIME R/W 0h Minimum ON time for low side MOSFET 0h = 0 µs 1h = Automatic based on slew rate 2h = 0.5 µs 3h = 0.75 µs 4h = 1 µs 5h = 1.25 µs 6h = 1.5 µs 7h = 2 µs 16-13 RESERVED R 0h Reserved 12-0 RESERVED R 0h Reserved

6.7.4 Internal_Algorithm_Configuration Registers

Table 6-43 lists the memory-mapped registers for the Internal_Algorithm_Configuration registers. All register offset addresses not listed in Table 6-43 should be considered as reserved locations and the register contents should not be modified. Table 6-43. INTERNAL_ALGORITHM_CONFIGURATION Registers Offset Acronym Register Name Section A0h INT_ALGO_1 Internal Algorithm Configuration1 Section 6.7.4.1 A2h INT_ALGO_2 Internal Algorithm Configuration2 Section 6.7.4.2 Complex bit access types are encoded to fit into small table cells. Table 6-44 shows the codes that are used for access types in this section. Table 6-44. Internal_Algorithm_Configuration Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: MCF8316D

6.7.4.1 INT_ALGO_1 Register (Offset = A0h) [Reset = 00000000h]

INT_ALGO_1 is shown in Figure 6-89 and described in Table 6-45. Return to the Summary Table. Register to configure internal algorithm parameters1 Figure 6-89. INT_ALGO_1 Register 31 30 29 28 27 26 25 24 PARITY ACTIVE_BRAKE_SPEED__DEL TA_LIMIT_EXIT SPEED_PIN_GLITCH_FILTER FAST_ISD_EN ISD_STOP_TIME R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 23 22 21 20 19 18 17 16 ISD_RUN_TIME ISD_TIMEOUT AUTO_HANDOFF_MIN_BEMF BRAKE_CURR ENT_PERSIST R/W-0h R/W-0h R/W-0h R/W-0h 15 14 13 12 11 10 9 8 BRAKE_CURR ENT_PERSIST RESERVED R/W-0h R-0h 7 6 5 4 3 2 1 0 RESERVED REV_DRV_OPEN_LOOP_DEC R-0h R/W-0h Table 6-45. INT_ALGO_1 Register Field Descriptions Bit Field Type Reset Description 30-29 ACTIVE_BRAKE_SPEED __DELTA_LIMIT_EXIT R/W 0h Difference between final speed and present speed below which active braking will be stopped 0h = 2.5% 1h = 5% 2h = 7.5% 3h = 10% 28-27 SPEED_PIN_GLITCH_FIL TER R/W 0h Glitch filter applied on speed pin input 0h = No Glitch Filter 1h = 0.2 µs 2h = 0.5 µs 3h = 1.0 µs

26 FAST_ISD_EN R/W 0h Enable fast speed detection during ISD

0h = Disable fast ISD 1h = Enable fast ISD 25-24 ISD_STOP_TIME R/W 0h Persistence time for declaring motor is in stopped state during ISD 0h = 1 ms 1h = 5 ms 2h = 50 ms 3h = 100 ms MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-45. INT_ALGO_1 Register Field Descriptions (continued) Bit Field Type Reset Description 23-22 ISD_RUN_TIME R/W 0h Persistence time for declaring motor is in running state during ISD 0h = 1 ms 1h = 5 ms 2h = 50 ms 3h = 100 ms 21-20 ISD_TIMEOUT R/W 0h Timeout in case ISD is unable to reliably detect speed or direction 0h = 500ms 1h = 750 ms 2h = 1000 ms 3h = 2000 ms 19-17 AUTO_HANDOFF_MIN_B EMF R/W 0h Minimum BEMF for handoff. Applicable when auto handoff is enabled. 0h = 0 mV 1h = 50 mV 2h = 100 mV 3h = 250 mV 4h = 500 mV 5h = 1000 mV 6h = 1250 mV 7h = 1500 mV 16-15 BRAKE_CURRENT_PER SIST R/W 0h Persistence time for current below threshold during current based ISD brake 0h = 50 ms 1h = 100 ms 2h = 250 ms 3h = 500 ms 14-3 RESERVED R 0h Reserved 2-0 REV_DRV_OPEN_LOOP _DEC R/W 0h % of open loop acceleration to be applied during open loop deceleration in reverse drive 0h = 50% 1h = 60% 2h = 70% 3h = 80% 4h = 90% 5h = 100% 6h = 125% 7h = 150% www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: MCF8316D

6.7.4.2 INT_ALGO_2 Register (Offset = A2h) [Reset = 00000000h]

INT_ALGO_2 is shown in Figure 6-90 and described in Table 6-46. Return to the Summary Table. Register to configure internal algorithm parameters2 Figure 6-90. INT_ALGO_2 Register 31 30 29 28 27 26 25 24 PARITY FLUX_WEAK_KP R/W-0h R/W-0h 23 22 21 20 19 18 17 16 FLUX_WEAK_KP FLUX_WEAK_KI R/W-0h R/W-0h 15 14 13 12 11 10 9 8 FLUX_WEAK_KI FLUX_WEAK_ ENABLE CL_SLOW_ACC R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 CL_SLOW_ACC ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATE ISD_BEMF_FIL T_ENABLE CIRCULAR_CU RRENT_LIMIT_ ENABLE IPD_HIGH_RE SOLUTION_EN R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 6-46. INT_ALGO_2 Register Field Descriptions Bit Field Type Reset Description 30-21 FLUX_WEAK_KP R/W 0h 10-bit value for flux weakening loop Kp. Kp = 8LSB of 0.1 * FLUX_WEAK_KP / 10^2MSB of FLUX_WEAK_KP. 20-11 FLUX_WEAK_KI R/W 0h 10-bit value for current Iq and Id loop Ki. Ki = 10 * 8LSB of FLUX_WEAK_KI / 10^2MSB of FLUX_WEAK_KI.

10 FLUX_WEAK_ENABLE R/W 0h Enable flux weakening

0h = Flux Weakening is disabled 1h = Flux Weakening is enabled MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-46. INT_ALGO_2 Register Field Descriptions (continued) Bit Field Type Reset Description 9-6 CL_SLOW_ACC R/W 0h Close loop acceleration when estimator is not yet fully aligned (only in speed mode) and acceleration/deacceleration during power/speed limit (Speed mode: Hz/s Power mode: deciWatts/s Torque mode: centiA/s duty cycle mode: milliUnit/s) deciWatt: 0.1W centiA: 0.01A milliUnit: 0.001% 0h = 0.1 Hz/s 1h = 1 Hz/s 2h = 2 Hz/s 3h = 3 Hz/s 4h = 5 Hz/s 5h = 10 Hz/s 6h = 20 Hz/s 7h = 30 Hz/s 8h = 40 Hz/s 9h = 50 Hz/s Ah = 100 Hz/s Bh = 200 Hz/s Ch = 500 Hz/s Dh = 750 Hz/s Eh = 1000 Hz/s Fh = 2000 Hz/s 5-3 ACTIVE_BRAKE_BUS_C URRENT_SLEW_RATE R/W 0h Bus current slew rate during active braking 0h = 10 A/s 1h = 50 A/s 2h = 100 A/s 3h = 250 A/s 4h = 500 A/s 5h = 1000 A/s 6h = 5000 A/s 7h = No Limit A/s

2 ISD_BEMF_FILT_ENABL

E R/W 0h Enable BEMF filter during ISD. 0h = Disable 1h = Enable

1 CIRCULAR_CURRENT_L

IMIT_ENABLE R/W 0h Configuration for ILIMIT vs. peak phase current 0h = Circular current limit is disabled: ILIMIT * sqrt(2) can be peak phase current 1h = Circular current limit is enabled: ILIMIT is peak phase current

0 IPD_HIGH_RESOLUTION

_EN R/W 0h IPD high resolution enable 0h = Disable 1h = Enable www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: MCF8316D

6.8 RAM (Volatile) Register Map

6.8.1 Fault_Status Registers

Table 6-47 lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not listed in Table 6-47 should be considered as reserved locations and the register contents should not be modified. Table 6-47. FAULT_STATUS Registers Offset Acronym Register Name Section E0h GATE_DRIVER_FAULT_STATUS Fault Status Register Section 6.8.1.1 E2h CONTROLLER_FAULT_STATUS Fault Status Register Section 6.8.1.2 32Ch EEPROM_FAULT_STATUS Section 6.8.1.3 Complex bit access types are encoded to fit into small table cells. Table 6-48 shows the codes that are used for access types in this section. Table 6-48. Fault_Status Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]

GATE_DRIVER_FAULT_STATUS is shown in Figure 6-91 and described in Table 6-49. Return to the Summary Table. Status of various gate driver faults Figure 6-91. GATE_DRIVER_FAULT_STATUS Register 31 30 29 28 27 26 25 24 DRIVER_FAUL T RESERVED RESERVED OCP RESERVED OVP RESERVED RESERVED R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 23 22 21 20 19 18 17 16 OTW OTS OCP_HC OCP_LC OCP_HB OCP_LB OCP_HA OCP_LA R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 15 14 13 12 11 10 9 8 RESERVED RESERVED BUCK_OCP BUCK_UV VCP_UV RESERVED RESERVED RESERVED R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 6-49. GATE_DRIVER_FAULT_STATUS Register Field Descriptions Bit Field Type Reset Description

31 DRIVER_FAULT R 0h Logic OR of gate driver fault status bits

28 OCP R 0h Over current protection status

0h = No overcurrent condition is detected 1h = Overcurrent condition is detected

27 RESERVED R 0h Reserved

26 OVP R 0h Supply (VM) overvoltage protection status

0h = No overvoltage condition is detected on VM 1h = Overvoltage condition is detected on VM

23 OTW R 0h Overtemperature warning status

0h = No overtemperature warning is detected 1h = Overtemperature warning is detected

22 OTS R 0h Overtemperature shutdown status

0h = No overtemperature shutdown is detected 1h = Overtemperature shutdown is detected

21 OCP_HC R 0h Overcurrent status on high-side switch of OUTC

0h = No overcurrent detected on high-side switch of OUTC 1h = Overcurrent detected on high-side switch of OUTC www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: MCF8316D

Table 6-49. GATE_DRIVER_FAULT_STATUS Register Field Descriptions (continued) Bit Field Type Reset Description

20 OCP_LC R 0h Overcurrent status on low-side switch of OUTC

0h = No overcurrent detected on low-side switch of OUTC 1h = Overcurrent detected on low-side switch of OUTC

19 OCP_HB R 0h Overcurrent status on high-side switch of OUTB

0h = No overcurrent detected on high-side switch of OUTB 1h = Overcurrent detected on high-side switch of OUTB

18 OCP_LB R 0h Overcurrent status on low-side switch of OUTB

0h = No overcurrent detected on low-side switch of OUTB 1h = Overcurrent detected on low-side switch of OUTB

17 OCP_HA R 0h Overcurrent status on high-side switch of OUTA

0h = No overcurrent detected on high-side switch of OUTA 1h = Overcurrent detected on high-side switch of OUTA

16 OCP_LA R 0h Overcurrent status on low-side switch of OUTA

0h = No overcurrent detected on low-side switch of OUTA 1h = Overcurrent detected on low-side switch of OUTA

13 BUCK_OCP R 0h Buck regulator overcurrent status

0h = No buck regulator overcurrent is detected 1h = Buck regulator overcurrent is detected

12 BUCK_UV R 0h Buck regulator undervoltage status

0h = No buck regulator undervoltage is detected 1h = Buck regulator undervoltage is detected

11 VCP_UV R 0h Charge pump undervoltage status

0h = No charge pump undervoltage is detected 1h = Charge pump undervoltage is detected

10 RESERVED R 0h Reserved

9 RESERVED R 0h Reserved

8 RESERVED R 0h Reserved

7-0 RESERVED R 0h Reserved MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.1.2 CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]

CONTROLLER_FAULT_STATUS is shown in Figure 6-92 and described in Table 6-50. Return to the Summary Table. Status of various controller faults Figure 6-92. CONTROLLER_FAULT_STATUS Register 31 30 29 28 27 26 25 24 CONTROLLER _FAULT RESERVED IPD_FREQ_FA ULT IPD_T1_FAULT IPD_T2_FAULT RESERVED MPET_IPD_FA ULT MPET_BEMF_ FAULT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 23 22 21 20 19 18 17 16 ABN_SPEED ABN_BEMF NO_MTR MTR_LCK LOCK_LIMIT HW_LOCK_LIM IT MTR_UNDER_ VOLTAGE MTR_OVER_V OLTAGE R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h 15 14 13 12 11 10 9 8 SPEED_LOOP _SATURATION CURRENT_LO OP_SATURATI ON MAX_SPEED_ SATURATION BUS_POWER_ LIMIT_SATURA TION EEPROM_WRI TE_LOCK_SET EEPROM_REA D_LOCK_SET RESERVED R-0h R-0h R-0h R-0h R-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED I2C_CRC_FAU LT_STATUS EEPROM_ERR _STATUS BOOT_STL_FA ULT WATCHDOG_F AULT CPU_RESET_F AULT_STATUS WWDT_FAULT _STATUS RESERVED R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 6-50. CONTROLLER_FAULT_STATUS Register Field Descriptions Bit Field Type Reset Description

31 CONTROLLER_FAULT R 0h Logic OR of controller fault status bits

29 IPD_FREQ_FAULT R 0h IPD frequency fault status

28 IPD_T1_FAULT R 0h IPD T1 fault status

27 IPD_T2_FAULT R 0h IPD T2 fault status

26 RESERVED R 0h Reserved

25 MPET_IPD_FAULT R 0h Indicates error during MPET resistance and inductance

24 MPET_BEMF_FAULT R 0h Indicates error during MPET BEMF constant measurement

23 ABN_SPEED R 0h Indicates Abnormal speed motor lock condition

22 ABN_BEMF R 0h Indicates Abnormal BEMF motor lock condition

21 NO_MTR R 0h Indicates No Motor (loss of phase) fault

20 MTR_LCK R 0h Indicates when one of the motor lock (abnormal BEMF/speed, no

motor) is triggered

19 LOCK_LIMIT R 0h Indicates lock current limit fault

18 HW_LOCK_LIMIT R 0h Indicates hardware lock current limit fault

17 MTR_UNDER_VOLTAGE R 0h Indicates configurable under voltage fault on VM

16 MTR_OVER_VOLTAGE R 0h Indicates configurable over voltage fault on VM

15 SPEED_LOOP_SATURAT

R 0h Indicates speed loop saturation

14 CURRENT_LOOP_SATU

R 0h Indicates current loop saturation www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: MCF8316D

Table 6-50. CONTROLLER_FAULT_STATUS Register Field Descriptions (continued) Bit Field Type Reset Description

13 MAX_SPEED_SATURATI

R 0h Indicates maximum speed limit saturation

12 BUS_POWER_LIMIT_SA

R 0h Indicates maximum (input DC bus) power limit saturation

11 EEPROM_WRITE_LOCK

_SET R 0h Indicates EEPROM write lock is set

10 EEPROM_READ_LOCK_

R 0h Indicates EEPROM read lock is set 9-8 RESERVED R 0h Reserved

6 I2C_CRC_FAULT_STATU

S R 0h Indicates CRC fault in I2C packet

5 EEPROM_ERR_STATUS R 0h Indicates error in EEPROM

4 BOOT_STL_FAULT R 0h Indicates self test fault during boot-up (applicable to MCF8316DUL

only)

3 WATCHDOG_FAULT R 0h Indicates watchdog timeout fault

2 CPU_RESET_FAULT_ST

R 0h Indicates unexpected CPU reset fault (applicable to MCF8316DUL only)

1 WWDT_FAULT_STATUS R 0h Indicates windowed watchdog reset fault (applicable to

MCF8316DUL only) SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.1.3 EEPROM_FAULT_STATUS Register (Offset = 32Ch) [Reset = 0000h]

EEPROM_FAULT_STATUS is shown in Figure 6-93 and described in Table 6-51. Return to the Summary Table. Figure 6-93. EEPROM_FAULT_STATUS Register 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED EEPROM_CRC _FLT_STS RESERVED EEPROM_PARI TY_FLT_STS RESERVED RESERVED R-0h R-0h R-0h R-0h R-0h R-0h Table 6-51. EEPROM_FAULT_STATUS Register Field Descriptions Bit Field Type Reset Description 15-5 RESERVED R 0h Reserved

4 EEPROM_CRC_FLT_STS R 0h EEPROM CRC error fault status

0h = EEPROM CRC Error fault condition is not detected 1h = EEPROM CRC Error fault condition is detected

2 EEPROM_PARITY_FLT_S

R 0h EEPROM parity error fault status 0h = EEPROM Parity error fault condition is not detected 1h = EEPROM Parity error fault condition is detected

6.8.2 System_Status Registers

Table 6-52 lists the memory-mapped registers for the System_Status registers. All register offset addresses not listed in Table 6-52 should be considered as reserved locations and the register contents should not be modified. Table 6-52. SYSTEM_STATUS Registers Offset Acronym Register Name Section E4h ALGO_STATUS System Status Register Section 6.8.2.1 E6h MTR_PARAMS System Status Register Section 6.8.2.2 E8h ALGO_STATUS_MPET System Status Register Section 6.8.2.3 Complex bit access types are encoded to fit into small table cells. Table 6-53 shows the codes that are used for access types in this section. Table 6-53. System_Status Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: MCF8316D

6.8.2.1 ALGO_STATUS Register (Offset = E4h) [Reset = 00000000h]

ALGO_STATUS is shown in Figure 6-94 and described in Table 6-54. Return to the Summary Table. Status of various system and algorithm parameters Figure 6-94. ALGO_STATUS Register 31 30 29 28 27 26 25 24 VOLT_MAG R-0h 23 22 21 20 19 18 17 16 VOLT_MAG R-0h 15 14 13 12 11 10 9 8 DUTY_CMD R-0h 7 6 5 4 3 2 1 0 DUTY_CMD RESERVED SYS_ENABLE_ FLAG RESERVED R-0h R-0h R-0h R-0h Table 6-54. ALGO_STATUS Register Field Descriptions Bit Field Type Reset Description 31-16 VOLT_MAG R 0h 16-bit value indicating applied modulation index. Modulation index applied = (VOLT_MAG * 100 / 32768)% 15-4 DUTY_CMD R 0h 12-bit value indicating input duty command in PWM/Analog/Freq mode DUTY_CMD (%) = (DUTY_CMD/4095 * 100)%.

2 SYS_ENABLE_FLAG R 0h 1 indicates GUI can control the register 0 indicates GUI is still

copying default parameters from shadow memory 1-0 RESERVED R 0h Reserved MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.2.2 MTR_PARAMS Register (Offset = E6h) [Reset = 00000000h]

MTR_PARAMS is shown in Figure 6-95 and described in Table 6-55. Return to the Summary Table. Status of various motor parameters Figure 6-95. MTR_PARAMS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOTOR_R MOTOR_BEMF_CONST R-0h R-0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOTOR_L RESERVED R-0h R-0h Table 6-55. MTR_PARAMS Register Field Descriptions Bit Field Type Reset Description 31-24 MOTOR_R R 0h 8-bit value indicating MPET measured motor resistance 23-16 MOTOR_BEMF_CONST R 0h 8-bit value indicating MPET measured BEMF constant 15-8 MOTOR_L R 0h 8-bit value indicating MPET measured motor inductance 7-0 RESERVED R 0h Reserved www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: MCF8316D

6.8.2.3 ALGO_STATUS_MPET Register (Offset = E8h) [Reset = 00000000h]

ALGO_STATUS_MPET is shown in Figure 6-96 and described in Table 6-56. Return to the Summary Table. Status of various MPET parameters Figure 6-96. ALGO_STATUS_MPET Register 31 30 29 28 27 26 25 24 MPET_R_STAT US MPET_L_STAT US MPET_KE_STA TUS MPET_MECH_ STATUS MPET_PWM_FREQ R-0h R-0h R-0h R-0h R-0h 23 22 21 20 19 18 17 16 RESERVED R-0h 15 14 13 12 11 10 9 8 RESERVED R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 6-56. ALGO_STATUS_MPET Register Field Descriptions Bit Field Type Reset Description

31 MPET_R_STATUS R 0h Indicates status of resistance measurement

0h = Measurement of motor resistance during MPET routine is not completed if resistance measurement is initiated during MPET 1h = Measurement of motor resistance during MPET routine is completed

30 MPET_L_STATUS R 0h Indicates status of inductance measurement

0h = Measurement of motor inductance during MPET routine is not completed if inductance measurement is initiated during MPET 1h = Measurement of motor inductance during MPET routine is completed

29 MPET_KE_STATUS R 0h Indicates status of BEMF constant measurement

0h = Measurement of motor BEMF constant during MPET routine is not completed if BEMF constant measurement is initiated during MPET 1h = Measurement of motor BEMF constant during MPET routine is completed

28 MPET_MECH_STATUS R 0h Indicates status of mechanical parameter measurement

0h = Auto Calculation of Speed loop Kp, Ki values during MPET routine is not completed if mechanical parameters measurement(speed loop kp,ki values) is initiated during MPET 1h = Auto Calculation of Speed loop Kp, Ki values during MPET routine is completed MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-56. ALGO_STATUS_MPET Register Field Descriptions (continued) Bit Field Type Reset Description 27-24 MPET_PWM_FREQ R 0h 4-bit value indicating MPET recommended PWM switching frequency based on electrical time constant. Follows same enum list as PWM_FREQ_OUT 23-0 RESERVED R 0h Reserved

6.8.3 Device_Control Registers

Table 6-57 lists the memory-mapped registers for the Device_Control registers. All register offset addresses not listed in Table 6-57 should be considered as reserved locations and the register contents should not be modified. Table 6-57. DEVICE_CONTROL Registers Offset Acronym Register Name Section EAh ALGO_CTRL1 Device Control Register Section 6.8.3.1 Complex bit access types are encoded to fit into small table cells. Table 6-58 shows the codes that are used for access types in this section. Table 6-58. Device_Control Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: MCF8316D

6.8.3.1 ALGO_CTRL1 Register (Offset = EAh) [Reset = 00000000h]

ALGO_CTRL1 is shown in Figure 6-97 and described in Table 6-59. Return to the Summary Table. Control settings Figure 6-97. ALGO_CTRL1 Register 31 30 29 28 27 26 25 24 EEPROM_WRT EEPROM_REA D CLR_FLT CLR_FLT_RET RY_COUNT EEPROM_WRITE_ACCESS_KEY R/W-0h R/W-0h W-0h W-0h W-0h 23 22 21 20 19 18 17 16 EEPROM_WRITE_ACCESS_KEY FORCED_ALIGN_ANGLE W-0h W-0h 15 14 13 12 11 10 9 8 FORCED_ALIGN_ANGLE WATCHDOG_T ICKLE STL_CMD STL_KEY W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 STL_KEY RESERVED R/W-0h R-0h Table 6-59. ALGO_CTRL1 Register Field Descriptions Bit Field Type Reset Description

31 EEPROM_WRT R/W 0h Write the configuration from RAM/shadow to EEPROM

30 EEPROM_READ R/W 0h Read the default configuration from EEPROM to RAM/shadow

29 CLR_FLT W 0h Clears all faults

28 CLR_FLT_RETRY_COUN

T W 0h Clears automatic fault retry count 27-20 EEPROM_WRITE_ACCE SS_KEY W 0h EEPROM write access key (0xA5) 19-11 FORCED_ALIGN_ANGLE W 0h 9-bit value (in degrees) used during forced align state (applicable when FORCE_ALIGN_EN = 0x1) For example if FORCED_ALIGN_ANGLE value is 225 degrees then angle applied during Forced Align will be 225 degrees, similarly if FORCED_ALIGN_ANGLE value is 395 degrees then angle applied during Forced Align will be 395%360 which is 35 degrees Angle applied = (FORCED_ALIGN_ANGLE % 360)deg 10 WATCHDOG_TICKLE R/W 0h RAM bit to tickle watchdog in I2C mode. 0x1 should be written to this bit by external controller every EXT_WDT_CFG. Device will reset this bit to 0x0.

9 STL_CMD R/W 0h Command to initiate self test (applicable to MCF8316DUL only)

8-1 STL_KEY R/W 0h Key(0xBE) to initiate self test on demand (applicable to MCF8316DUL only)

6.8.4 Algorithm_Control Registers

Table 6-60 lists the memory-mapped registers for the Algorithm_Control registers. All register offset addresses not listed in Table 6-60 should be considered as reserved locations and the register contents should not be modified. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-60. ALGORITHM_CONTROL Registers Offset Acronym Register Name Section ECh ALGO_DEBUG1 Algorithm Control Register Section 6.8.4.1 EEh ALGO_DEBUG2 Algorithm Control Register Section 6.8.4.2 F0h CURRENT_PI Current PI Controller used Section 6.8.4.3 F2h SPEED_PI Speed PI controller used Section 6.8.4.4 F4h DAC_1 DAC1 Control Register Section 6.8.4.5 F6h DAC_2 DAC2 Control Register Section 6.8.4.6 F8h EEPROM_SECURITY EEPROM Security Control Register Section 6.8.4.7 Complex bit access types are encoded to fit into small table cells. Table 6-61 shows the codes that are used for access types in this section. Table 6-61. Algorithm_Control Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: MCF8316D

6.8.4.1 ALGO_DEBUG1 Register (Offset = ECh) [Reset = 00000000h]

ALGO_DEBUG1 is shown in Figure 6-98 and described in Table 6-62. Return to the Summary Table. Algorithm control register for debug Figure 6-98. ALGO_DEBUG1 Register 31 30 29 28 27 26 25 24 OVERRIDE DIGITAL_SPEED_CTRL W-0h W-0h 23 22 21 20 19 18 17 16 DIGITAL_SPEED_CTRL W-0h 15 14 13 12 11 10 9 8 CLOSED_LOO P_DIS FORCE_ALIGN _EN FORCE_SLOW _FIRST_CYCL E_EN FORCE_IPD_E N FORCE_ISD_E N FORCE_ALIGN _ANGLE_SRC_ SEL RESERVED W-0h W-0h W-0h W-0h W-0h W-0h R-0h 7 6 5 4 3 2 1 0 RESERVED R-0h Table 6-62. ALGO_DEBUG1 Register Field Descriptions Bit Field Type Reset Description 31 OVERRIDE W 0h Use to control the reference input mode. If OVERRIDE = 0x1, speed command can be written by the user through I2C interface irrespective of SPEED_MODE setting. 0h = SPEED_CMD using Analog/PWM/Frequency mode 1h = SPEED_CMD using DIGITAL_SPEED_CTRL 30-16 DIGITAL_SPEED_CTRL W 0h Reference input when OVERRIDE is set 0x1 or SPEED_MODE is set to 0x2. Reference input = (DIGITAL_SPEED_CTRL/32768 *100)%

15 CLOSED_LOOP_DIS W 0h Use to disable closed loop operation

0h = Enable closed Loop 1h = Disable closed loop, motor commutation in open loop

14 FORCE_ALIGN_EN W 0h Enable force align state

0h = Disable force align state 1h = Enable force align state, device stays in align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN

13 FORCE_SLOW_FIRST_C

YCLE_EN W 0h Enable force slow first cycle 0h = Disable force slow first Cycle state 1h = Enable force slow first cycle state, device stays in slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE

12 FORCE_IPD_EN W 0h Enable force IPD

0h = Disable force IPD state 1h = Enable force IPD state, device stays in IPD state if MTR_STARTUP is selected as IPD MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-62. ALGO_DEBUG1 Register Field Descriptions (continued) Bit Field Type Reset Description

11 FORCE_ISD_EN W 0h Enable force ISD

0h = Disable force ISD state 1h = Enable force ISD state, device stays in ISD state if ISD_EN is set

10 FORCE_ALIGN_ANGLE_

SRC_SEL W 0h Select force align angle source 0h = Force align angle defined by ALIGN_ANGLE 1h = Force align angle defined by FORCED_ALIGN_ANGLE 9-0 RESERVED R 0h Reserved www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: MCF8316D

6.8.4.2 ALGO_DEBUG2 Register (Offset = EEh) [Reset = 00000000h]

ALGO_DEBUG2 is shown in Figure 6-99 and described in Table 6-63. Return to the Summary Table. Algorithm control register for debug Figure 6-99. ALGO_DEBUG2 Register 31 30 29 28 27 26 25 24 RESERVED FORCE_RECIRCULATE_STOP_SECTOR FORCE_RECIR CULATE_STOP _EN CURRENT_LO OP_DIS FORCE_VD_CURRENT_LOOP_ DIS R-0h W-0h W-0h W-0h W-0h 23 22 21 20 19 18 17 16 FORCE_VD_CURRENT_LOOP_DIS W-0h 15 14 13 12 11 10 9 8 FORCE_VQ_CURRENT_LOOP_DIS W-0h 7 6 5 4 3 2 1 0 FORCE_VQ_CURRENT_LOOP_ DIS MPET_CMD MPET_R MPET_L MPET_KE MPET_MECH MPET_WRITE_ SHADOW W-0h W-0h W-0h W-0h W-0h W-0h W-0h Table 6-63. ALGO_DEBUG2 Register Field Descriptions Bit Field Type Reset Description

31 RESERVED R 0h Reserved

30-28 FORCE_RECIRCULATE_ STOP_SECTOR W 0h Select the specific sector for recirculation stop if FORCE_RECIRCULATE_STOP_EN is set to 0x1 0h = The last sector before stop condition 1h = Sector1 2h = Sector2 3h = Sector3 4h = Sector4 5h = Sector5 6h = Sector6 7h = The last sector before stop condition

27 FORCE_RECIRCULATE_

STOP_EN W 0h Enable force recirculate stop 0h = Enable force recirculate stop 1h = Disable force recirculate stop

26 CURRENT_LOOP_DIS W 0h Use to control the FORCE_VD_CURRENT_LOOP_DIS and

FORCE_VQ_CURRENT_LOOP_DIS. If CURRENT_LOOP_DIS = 0x1, Current loop and speed loop are disabled 0h = Enable current loop 1h = Disable current loop MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-63. ALGO_DEBUG2 Register Field Descriptions (continued) Bit Field Type Reset Description 25-16 FORCE_VD_CURRENT_ LOOP_DIS W 0h Sets Vd when current loop speed loop are disabled If CURRENT_LOOP_DIS = 0b1, then Vd is control using FORCE_VD_CURRENT_LOOP_DIS mdRef = (FORCE_VD_CURRENT_LOOP_DIS /500) if FORCE_VD_CURRENT_LOOP_DIS < 500 (FORCE_VD_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VD_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000 15-6 FORCE_VQ_CURRENT_ LOOP_DIS W 0h Sets Vq when current loop speed loop are disabled If CURRENT_LOOP_DIS = 0b1, then Vq is control using FORCE_VQ_CURRENT_LOOP_DIS mqRef = (FORCE_VQ_CURRENT_LOOP_DIS /500) if FORCE_VQ_CURRENT_LOOP_DIS < 500 (FORCE_VQ_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VQ_CURRENT_LOOP_DIS > 512 Valid values: 0 to 500 and 512 to 1000

5 MPET_CMD W 0h Initiates motor parameter measurement (MPET) routine when set to

4 MPET_R W 0h Enables motor resistance measurement during motor parameter

0h = Disables Motor Resistance measurement during motor parameter measurement routine 1h = Enable Motor Resistance measurement during motor parameter measurement routine

3 MPET_L W 0h Enables motor inductance measurement during motor parameter

0h = Disables Motor Inductance measurement during motor parameter measurement routine 1h = Enable Motor Inductance measurement during motor parameter measurement routine

2 MPET_KE W 0h Enables motor BEMF constant measurement during motor

parameter measurement routine 0h = Disables Motor BEMF constant measurement during motor parameter measurement routine 1h = Enable Motor BEMF constant measurement during motor parameter measurement routine

1 MPET_MECH W 0h Enables motor mechanical parameter measurement during motor

parameter measurement routine 0h = Disables Motor mechanical parameter measurement during motor parameter measurement routine 1h = Enable Motor mechanical parameter measurement during motor parameter measurement routine

0 MPET_WRITE_SHADOW W 0h Write measured parameters to shadow register when set to 0x1

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6.8.4.3 CURRENT_PI Register (Offset = F0h) [Reset = 00000000h]

CURRENT_PI is shown in Figure 6-100 and described in Table 6-64. Return to the Summary Table. Current PI controller used Figure 6-100. CURRENT_PI Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CURRENT_LOOP_KI CURRENT_LOOP_KP R-0h R-0h Table 6-64. CURRENT_PI Register Field Descriptions Bit Field Type Reset Description 31-16 CURRENT_LOOP_KI R 0h 10 bit value for current loop Ki Same Scaling as CURR_LOOP_KI 15-0 CURRENT_LOOP_KP R 0h 10 bit value for current loop Kp Same Scaling as CURR_LOOP_KP MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.4.4 SPEED_PI Register (Offset = F2h) [Reset = 00000000h]

SPEED_PI is shown in Figure 6-101 and described in Table 6-65. Return to the Summary Table. Speed PI controller used Figure 6-101. SPEED_PI Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPEED_LOOP_KI SPEED_LOOP_KP R-0h R-0h Table 6-65. SPEED_PI Register Field Descriptions Bit Field Type Reset Description 31-16 SPEED_LOOP_KI R 0h 10 bit value for Speed loop Ki Same Scaling as SPD_LOOP_KI 15-0 SPEED_LOOP_KP R 0h 10 bit value for Speed loop Kp Same Scaling as SPD_LOOP_KP www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: MCF8316D

6.8.4.5 DAC_1 Register (Offset = F4h) [Reset = 00110000h]

DAC_1 is shown in Figure 6-102 and described in Table 6-66. Return to the Summary Table. DAC1 Control Register Figure 6-102. DAC_1 Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED DACOUT1_ENUM_SCALING DACOUT1_SC ALING R-0h W-8h W-8h 15 14 13 12 11 10 9 8 DACOUT1_SCALING DACOUT1_UNI POLAR DACOUT1_VAR_ADDR W-8h W-0h R/W-0h 7 6 5 4 3 2 1 0 DACOUT1_VAR_ADDR R/W-0h Table 6-66. DAC_1 Register Field Descriptions Bit Field Type Reset Description 31-21 RESERVED R 0h Reserved 20-17 DACOUT1_ENUM_SCALI NG W 8h Multiplication Factor for DACOUT1 Algorithm Variable extracted from the address contained in DACOUT1_VAR_ADDR multiplied with 2DACOUT1_ENUM_SCALING. DACOUT1_ENUM_SCALING comes into effect only if DACOUT1_SCALING is 0x0 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-66. DAC_1 Register Field Descriptions (continued) Bit Field Type Reset Description 16-13 DACOUT1_SCALING W 8h Scaling factor for DACOUT1 Algorithm Variable extracted from the address contained in DACOUT1_VAR_ADDR scaled with DACOUT1_SCALING. Actual voltage depends on DACOUT1_UNIPOLAR. If DACOUT1_UNIPOLAR = 0x1, Actual Value= ((DAC Voltage*Base Value) )/((3* DACOUT1_SCALING)) If DACOUT1_UNIPOLAR = 0x0, Actual Value= (((DAC Voltage-1.5)*Base Value) )/((1.5* DACOUT1_SCALING)) Base Current is 10/8 A, Base Speed is MAX_SPEED in Hz, Base Voltage for DC Bus Voltage is 60V, Base voltage for phase voltages is 60V/ Sqrt(3) Note: For currents recommended DACOUT1_SCALING is 2/8, for Voltages 8/8 and for Speed 7/8 0h = Treated s Enum with max value being 31 1h = 1 / 8 2h = 2 / 8 3h = 3 / 8 4h = 4 / 8 5h = 5 / 8 6h = 6 / 8 7h = 7 / 8 8h = 8 / 8 9h = 9 / 8 Ah = 10 / 8 Bh = 11 / 8 Ch = 12 / 8 Dh = 13 / 8 Eh = 14 / 8 Fh = 15 / 8

12 DACOUT1_UNIPOLAR W 0h Configures output of DACOUT1 If DACOUT1_UNIPOLAR

= 0x1, Actual Value= ((DAC1 Voltage*Base Value) )/((3* DACOUT1_SCALING)) If DACOUT1_UNIPOLAR = 0x0, Actual Value= (((DAC2 Voltage-1.5)*Base Value) )/((1.5* DACOUT1_SCALING)) Base Current is 10/8 A, Base Speed is MAX_SPEED in Hz, Base Voltage for DC Bus Voltage is 60V, Base voltage for phase voltages is 60V/Sqrt(3) 0h = Bipolar (Offset of 1.5 V) 1h = Unipolar (No Offset) 11-0 DACOUT1_VAR_ADDR R/W 0h 12-bit address of variable to be monitored on DACOUT1 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: MCF8316D

6.8.4.6 DAC_2 Register (Offset = F6h) [Reset = 00XX0000h]

DAC_2 is shown in Figure 6-103 and described in Table 6-67. Return to the Summary Table. DAC2 Control Register Figure 6-103. DAC_2 Register 31 30 29 28 27 26 25 24 RESERVED R-0h 23 22 21 20 19 18 17 16 RESERVED DACOUT2_ENUM_SCALING DACOUT2_SCALING R-0h W-Xh W-8h 15 14 13 12 11 10 9 8 DACOUT2_SC ALING DACOUT2_UNI POLAR DACOUT2_VAR_ADDR W-8h W-0h R/W-0h 7 6 5 4 3 2 1 0 DACOUT2_VAR_ADDR R/W-0h Table 6-67. DAC_2 Register Field Descriptions Bit Field Type Reset Description 31-23 RESERVED R 0h Reserved 22-19 DACOUT2_ENUM_SCALI NG W Xh Multiplication Factor for DACOUT2 Algorithm Variable extracted from the address contained in DACOUT2_VAR_ADDR multiplied with 2DACOUT2_ENUM_SCALING. DACOUT2_ENUM_SCALING comes into effect only if DACOUT2_SCALING is 0x0 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-67. DAC_2 Register Field Descriptions (continued) Bit Field Type Reset Description 18-15 DACOUT2_SCALING W 8h Scaling factor for DACOUT2 Algorithm Variable extracted from the address contained in DACOUT2_VAR_ADDR scaled with DACOUT2_SCALING . Actual voltage depends on DACOUT2_UNIPOLAR. If DACOUT2_UNIPOLAR = 0x1, Actual Value= ((DAC2 Voltage*Base Value) )/((3* DACOUT2_SCALING)) If DACOUT2_UNIPOLAR = 0x0, Actual Value= (((DAC2 Voltage-1.5)*Base Value) )/((1.5* DACOUT2_SCALING)) Base Current is 10/8 A, Base Speed is MAX_SPEED in Hz, Base Voltage for DC Bus Voltage is 60V, Base voltage for phase voltages is 60V/ Sqrt(3) Note: For currents recommended DACOUT1_SCALING is 2/8, for Voltages 8/8 and for Speed information 7/8 0h = Treated s Enum with max value being 31 1h = 1 / 8 2h = 2 / 8 3h = 3 / 8 4h = 4 / 8 5h = 5 / 8 6h = 6 / 8 7h = 7 / 8 8h = 8 / 8 9h = 9 / 8 Ah = 10 / 8 Bh = 11 / 8 Ch = 12 / 8 Dh = 13 / 8 Eh = 14 / 8 Fh = 15 / 8

14 DACOUT2_UNIPOLAR W 0h Configures output of DACOUT2 If DACOUT2_UNIPOLAR

= 0x1, Actual Value= ((DAC2 Voltage*Base Value) )/((3* DACOUT2_SCALING)) If DACOUT2_UNIPOLAR = 0x0, Actual Value= (((DAC2 Voltage-1.5)*Base Value) )/((1.5* DACOUT2_SCALING)) Base Current is 10/8 A, Base Speed is MAX_SPEED in Hz, Base Voltage for DC Bus Voltage is 60V, Base voltage for phase voltages is 60V/Sqrt(3) Note: For currents recommended DACOUT1_SCALING is 2/8, for Voltages 8/8 and for Speed information 7/8 0h = Bipolar (Offset of 1.5 V) 1h = Unipolar (No Offset) 13-0 DACOUT2_VAR_ADDR R/W 0h 14-bit address of variable to be monitored on DACOUT2 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: MCF8316D

6.8.4.7 EEPROM_SECURITY Register (Offset = F8h) [Reset = 0000h]

EEPROM_SECURITY is shown in Figure 6-104 and described in Table 6-68. Return to the Summary Table. EEPROM Security Control Register Figure 6-104. EEPROM_SECURITY Register 15 14 13 12 11 10 9 8 RESERVED USER_EEPROM_KEY R-0h R/W-0h 7 6 5 4 3 2 1 0 USER_EEPROM_KEY R/W-0h Table 6-68. EEPROM_SECURITY Register Field Descriptions Bit Field Type Reset Description 14-0 USER_EEPROM_KEY R/W 0h User input key to unlock EEPROM for read/writes. Value in EEPROM_LOCK_KEY should be written here for unlocking EEPROM when EEPROM_LOCK_MODE = 0x1, 0x2

6.8.5 Algorithm_Variables Registers

Table 6-69 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 6-69 should be considered as reserved locations and the register contents should not be modified. Table 6-69. ALGORITHM_VARIABLES Registers Offset Acronym Register Name Section 18Eh ALGORITHM_STATE Current Algorithm State Register Section 6.8.5.1 194h FG_SPEED_FDBK FG Speed Feedback Register Section 6.8.5.2 400h VBETA VBETA Voltage Register Section 6.8.5.3 40Ch BUS_CURRENT Calculated DC Bus Current Register Section 6.8.5.4 444h PHASE_CURRENT_A Measured Current on Phase A Register Section 6.8.5.5 446h PHASE_CURRENT_B Measured Current on Phase B Register Section 6.8.5.6 448h PHASE_CURRENT_C Measured Current on Phase C Register Section 6.8.5.7 46Ch CSA_GAIN_FEEDBACK CSA Gain Register Section 6.8.5.8 477h VOLTAGE_GAIN_FEEDBACK Voltage Gain Register Section 6.8.5.9 47Ch VM_VOLTAGE VM Voltage Register Section 6.8.5.10 484h PHASE_VOLTAGE_VA Phase A Voltage Register Section 6.8.5.11 486h PHASE_VOLTAGE_VB Phase B Voltage Register Section 6.8.5.12 488h PHASE_VOLTAGE_VC Phase C Voltage Register Section 6.8.5.13 4BCh SIN_COMMUTATION_ANGLE Sine of Commutation Angle Section 6.8.5.14 4BEh COS_COMMUTATION_ANGLE Cosine of Commutation Angle Section 6.8.5.15 4DCh IALPHA IALPHA Current Register Section 6.8.5.16 4DEh IBETA IBETA Current Register Section 6.8.5.17 4E0h VALPHA VALPHA Voltage Register Section 6.8.5.18 4ECh ID Measured d-axis Current Register Section 6.8.5.19 4EEh IQ Measured q-axis Current Register Section 6.8.5.20 4F0h VD VD Voltage Register Section 6.8.5.21 4F2h VQ VQ Voltage Register Section 6.8.5.22 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 6-69. ALGORITHM_VARIABLES Registers (continued) Offset Acronym Register Name Section 52Ah IQ_REF_ROTOR_ALIGN Align Current Reference Section 6.8.5.23 540h SPEED_REF_OPEN_LOOP Open Loop Speed Register Section 6.8.5.24 550h IQ_REF_OPEN_LOOP Open Loop Current Reference Section 6.8.5.25 5D2h SPEED_REF_CLOSED_LOOP Speed Reference Register Section 6.8.5.26 612h ID_REF_CLOSED_LOOP Reference for Current Loop Register Section 6.8.5.27 614h IQ_REF_CLOSED_LOOP Reference for Current Loop Register Section 6.8.5.28 6AEh ISD_STATE ISD State Register Section 6.8.5.29 6B8h ISD_SPEED ISD Speed Register Section 6.8.5.30 6EAh IPD_STATE IPD State Register Section 6.8.5.31 72Eh IPD_ANGLE Calculated IPD Angle Register Section 6.8.5.32 772h ED Estimated BEMF EQ Register Section 6.8.5.33 774h EQ Estimated BEMF ED Register Section 6.8.5.34 782h SPEED_FDBK Speed Feedback Register Section 6.8.5.35 786h THETA_EST Estimated rotor Position Register Section 6.8.5.36 Complex bit access types are encoded to fit into small table cells. Table 6-70 shows the codes that are used for access types in this section. Table 6-70. Algorithm_Variables Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: MCF8316D

6.8.5.1 ALGORITHM_STATE Register (Offset = 18Eh) [Reset = 0000h]

ALGORITHM_STATE is shown in Figure 6-105 and described in Table 6-71. Return to the Summary Table. Current Algorithm State Register Figure 6-105. ALGORITHM_STATE Register 15 14 13 12 11 10 9 8 ALGORITHM_STATE R-0h 7 6 5 4 3 2 1 0 ALGORITHM_STATE R-0h Table 6-71. ALGORITHM_STATE Register Field Descriptions Bit Field Type Reset Description 15-0 ALGORITHM_STATE R 0h 16-bit value indicating current state of device 0h = MOTOR_IDLE 1h = MOTOR_ISD 2h = MOTOR_TRISTATE 3h = MOTOR_BRAKE_ON_START 4h = MOTOR_IPD 5h = MOTOR_SLOW_FIRST_CYCLE 6h = MOTOR_ALIGN 7h = MOTOR_OPEN_LOOP 8h = MOTOR_CLOSED_LOOP_UNALIGNED 9h = MOTOR_CLOSED_LOOP_ALIGNED Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING Bh = MOTOR_SOFT_STOP Ch = MOTOR_RECIRCULATE_STOP Dh = MOTOR_BRAKE_ON_STOP Eh = MOTOR_FAULT Fh = MOTOR_MPET_MOTOR_STOP_CHECK 10h = MOTOR_MPET_MOTOR_STOP_WAIT 11h = MOTOR_MPET_MOTOR_BRAKE 12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT 13h = MOTOR_MPET_RL_MEASURE 14h = MOTOR_MPET_KE_MEASURE 15h = MOTOR_MPET_STALL_CURRENT_MEASURE 16h = MOTOR_MPET_TORQUE_MODE 17h = MOTOR_MPET_DONE 18h = MOTOR_MPET_FAULT MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.2 FG_SPEED_FDBK Register (Offset = 194h) [Reset = 00000000h]

FG_SPEED_FDBK is shown in Figure 6-106 and described in Table 6-72. Return to the Summary Table. Speed Feedback from FG Figure 6-106. FG_SPEED_FDBK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FG_SPEED_FDBK R-0h Table 6-72. FG_SPEED_FDBK Register Field Descriptions Bit Field Type Reset Description 31-0 FG_SPEED_FDBK R 0h 32-bit value indicating absolute (unsigned) value of estimated motor speed based on FG Estimated Motor Speed (in Hz) = (FG_SPEED_FDBK / 227) * MAX_SPEED (in Hz) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: MCF8316D

6.8.5.3 VBETA Register (Offset = 400h) [Reset = 00000000h]

VBETA is shown in Figure 6-107 and described in Table 6-73. Return to the Summary Table. VBETA Voltage Register Figure 6-107. VBETA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VBETA R-0h Table 6-73. VBETA Register Field Descriptions Bit Field Type Reset Description 31-0 VBETA R 0h 32-bit signed value indicating applied phase voltage in alpha-beta domain. Negative value represented in two's complement. VBeta (in Volts)) = (VBETA / 227) * 60 / sqrt(3) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.4 BUS_CURRENT Register (Offset = 40Ch) [Reset = 00000000h]

BUS_CURRENT is shown in Figure 6-108 and described in Table 6-74. Return to the Summary Table. Calculated Supply Current Register Figure 6-108. BUS_CURRENT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS_CURRENT R-0h Table 6-74. BUS_CURRENT Register Field Descriptions Bit Field Type Reset Description 31-0 BUS_CURRENT R 0h 32-bit signed value indicating DC bus current. Negative value represented in two's complement. DC bus Current (in Amps) = (BUS_CURRENT / 227) * 10/8 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: MCF8316D

6.8.5.5 PHASE_CURRENT_A Register (Offset = 444h) [Reset = 00000000h]

PHASE_CURRENT_A is shown in Figure 6-109 and described in Table 6-75. Return to the Summary Table. Measured current on Phase A Register Figure 6-109. PHASE_CURRENT_A Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_CURRENT_A R-0h Table 6-75. PHASE_CURRENT_A Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_CURRENT_A R 0h 32-bit signed value indicating measured continuous Phase A current. Negative value represented in two's complement. Phase A current (in Amps) = (PHASE_CURRENT_A / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.6 PHASE_CURRENT_B Register (Offset = 446h) [Reset = 00000000h]

PHASE_CURRENT_B is shown in Figure 6-110 and described in Table 6-76. Return to the Summary Table. Measured current on Phase B Register Figure 6-110. PHASE_CURRENT_B Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_CURRENT_B R-0h Table 6-76. PHASE_CURRENT_B Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_CURRENT_B R 0h 32-bit signed value indicating measured continuous Phase B current. Negative value represented in two's complement. Phase B current (in Amps) = (PHASE_CURRENT_B / 227) * 10/8 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: MCF8316D

6.8.5.7 PHASE_CURRENT_C Register (Offset = 448h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in Figure 6-111 and described in Table 6-77. Return to the Summary Table. Measured current on Phase C Register Figure 6-111. PHASE_CURRENT_C Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_CURRENT_C R-0h Table 6-77. PHASE_CURRENT_C Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_CURRENT_C R 0h 32-bit signed value indicating measured continuous Phase C current. Negative value represented in two's complement. Phase C current (in Amps) = (PHASE_CURRENT_C / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.8 CSA_GAIN_FEEDBACK Register (Offset = 46Ch) [Reset = 0000h]

CSA_GAIN_FEEDBACK is shown in Figure 6-112 and described in Table 6-78. Return to the Summary Table. VM Voltage Register Figure 6-112. CSA_GAIN_FEEDBACK Register 15 14 13 12 11 10 9 8 CSA_GAIN_FEEDBACK R-0h 7 6 5 4 3 2 1 0 CSA_GAIN_FEEDBACK R-0h Table 6-78. CSA_GAIN_FEEDBACK Register Field Descriptions Bit Field Type Reset Description 15-0 CSA_GAIN_FEEDBACK R 0h 16-bit value indicating current sense gain. MIN_CSA_GAIN = 0.15V/A 0h = MIN_CSA_GAIN * 8 1h = MIN_CSA_GAIN * 4 2h = MIN_CSA_GAIN * 2 3h = MIN_CSA_GAIN * 1 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: MCF8316D

6.8.5.9 VOLTAGE_GAIN_FEEDBACK Register (Offset = 477h) [Reset = 0000h]

VOLTAGE_GAIN_FEEDBACK is shown in Figure 6-113 and described in Table 6-79. Return to the Summary Table. Voltage Gain Register Figure 6-113. VOLTAGE_GAIN_FEEDBACK Register 15 14 13 12 11 10 9 8 VOLTAGE_GAIN_FEEDBACK R-0h 7 6 5 4 3 2 1 0 VOLTAGE_GAIN_FEEDBACK R-0h Table 6-79. VOLTAGE_GAIN_FEEDBACK Register Field Descriptions Bit Field Type Reset Description 15-0 VOLTAGE_GAIN_FEEDB ACK R 0h 16-bit value indicating voltage gain 0h = 40V 1h = 30V 2h = 15V MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.10 VM_VOLTAGE Register (Offset = 47Ch) [Reset = 00000000h]

VM_VOLTAGE is shown in Figure 6-114 and described in Table 6-80. Return to the Summary Table. Supply voltage register Figure 6-114. VM_VOLTAGE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VM_VOLTAGE R-0h Table 6-80. VM_VOLTAGE Register Field Descriptions Bit Field Type Reset Description 31-0 VM_VOLTAGE R 0h 32-bit value indicating DC bus voltage DC Bus Voltage (in Volts) = VM_VOLTAGE * 60 / 227 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: MCF8316D

6.8.5.11 PHASE_VOLTAGE_VA Register (Offset = 484h) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in Figure 6-115 and described in Table 6-81. Return to the Summary Table. Phase A Voltage Register Figure 6-115. PHASE_VOLTAGE_VA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_VOLTAGE_VA R-0h Table 6-81. PHASE_VOLTAGE_VA Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_VOLTAGE_VA R 0h 32-bit signed value indicating measured A phase voltage during ISD. Negative value represented in two's complement. Phase A voltage (in Volts) = PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 227) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.12 PHASE_VOLTAGE_VB Register (Offset = 486h) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in Figure 6-116 and described in Table 6-82. Return to the Summary Table. Phase B Voltage Register Figure 6-116. PHASE_VOLTAGE_VB Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_VOLTAGE_VB R-0h Table 6-82. PHASE_VOLTAGE_VB Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_VOLTAGE_VB R 0h 32-bit signed value indicating measured B phase voltage during ISD. Negative value represented in two's complement. Phase B voltage (in Volts) = PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 227) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: MCF8316D

6.8.5.13 PHASE_VOLTAGE_VC Register (Offset = 488h) [Reset = 00000000h]

PHASE_VOLTAGE_VC is shown in Figure 6-117 and described in Table 6-83. Return to the Summary Table. Phase C Voltage Register Figure 6-117. PHASE_VOLTAGE_VC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHASE_VOLTAGE_VC R-0h Table 6-83. PHASE_VOLTAGE_VC Register Field Descriptions Bit Field Type Reset Description 31-0 PHASE_VOLTAGE_VC R 0h 32-bit signed value indicating measured C phase voltage during ISD. Negative value represented in two's complement. Phase C voltage (in Volts) = PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 227) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.14 SIN_COMMUTATION_ANGLE Register (Offset = 4BCh) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in Figure 6-118 and described in Table 6-84. Return to the Summary Table. Sine of Commutation Angle Figure 6-118. SIN_COMMUTATION_ANGLE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIN_COMMUTATION_ANGLE R-0h Table 6-84. SIN_COMMUTATION_ANGLE Register Field Descriptions Bit Field Type Reset Description 31-0 SIN_COMMUTATION_AN GLE R 0h 32-bit signed value indicating sine of rotor Angle. Negative value represented in two's complement. sin(rotor angle) = (SIN_COMMUTATION_ANGLE / 227) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: MCF8316D

6.8.5.15 COS_COMMUTATION_ANGLE Register (Offset = 4BEh) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in Figure 6-119 and described in Table 6-85. Return to the Summary Table. Cosine of Commutation Angle Figure 6-119. COS_COMMUTATION_ANGLE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COS_COMMUTATION_ANGLE R-0h Table 6-85. COS_COMMUTATION_ANGLE Register Field Descriptions Bit Field Type Reset Description 31-0 COS_COMMUTATION_A NGLE R 0h 32-bit signed value indicating cosine of rotor angle. Negative value represented in two's complement. cos(rotor angle) = (COS_COMMUTATION_ANGLE / 227) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.16 IALPHA Register (Offset = 4DCh) [Reset = 00000000h]

IALPHA is shown in Figure 6-120 and described in Table 6-86. Return to the Summary Table. IALPHA Current Register Figure 6-120. IALPHA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IALPHA R-0h Table 6-86. IALPHA Register Field Descriptions Bit Field Type Reset Description 31-0 IALPHA R 0h 32-bit signed value indicating phase current in alpha- beta domain. Negative value represented in two's complement. IAlpha (in Amps) = (IALPHA / 227) * 10/8 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 195 Product Folder Links: MCF8316D

6.8.5.17 IBETA Register (Offset = 4DEh) [Reset = 00000000h]

IBETA is shown in Figure 6-121 and described in Table 6-87. Return to the Summary Table. IBETA Current Register Figure 6-121. IBETA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IBETA R-0h Table 6-87. IBETA Register Field Descriptions Bit Field Type Reset Description 31-0 IBETA R 0h 32-bit signed value indicating phase current in alpha- beta domain. Negative value represented in two's complement. IBeta (in Amps) = (IBETA / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.18 VALPHA Register (Offset = 4E0h) [Reset = 00000000h]

VALPHA is shown in Figure 6-122 and described in Table 6-88. Return to the Summary Table. VALPHA Voltage Register Figure 6-122. VALPHA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VALPHA R-0h Table 6-88. VALPHA Register Field Descriptions Bit Field Type Reset Description 31-0 VALPHA R 0h 32-bit signed value indicating applied phase voltage in alpha-beta domain VAlpha (in Volts) = (VALPHA / 227) * 60 / sqrt(3) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: MCF8316D

6.8.5.19 ID Register (Offset = 4ECh) [Reset = 00000000h]

ID is shown in Figure 6-123 and described in Table 6-89. Return to the Summary Table. Measured d-axis Current Register Figure 6-123. ID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID R-0h Table 6-89. ID Register Field Descriptions Bit Field Type Reset Description 31-0 ID R 0h 32-bit signed value indicating d-axis(flux component) phase current in d-q domain. Negative value represented in two's complement. Flux component phase current (in Amps) = (ID / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.20 IQ Register (Offset = 4EEh) [Reset = 00000000h]

IQ is shown in Figure 6-124 and described in Table 6-90. Return to the Summary Table. Measured q-axis Current Register Figure 6-124. IQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IQ R-0h Table 6-90. IQ Register Field Descriptions Bit Field Type Reset Description 31-0 IQ R 0h 32-bit signed value indicating q-axis(torque component) phase current in d-q domain. Negative value represented in two's complement. Torque component phase current (in Amps) = (IQ / 227) * 10/8 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: MCF8316D

6.8.5.21 VD Register (Offset = 4F0h) [Reset = 00000000h]

VD is shown in Figure 6-125 and described in Table 6-91. Return to the Summary Table. VD Voltage Register Figure 6-125. VD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VD R-0h Table 6-91. VD Register Field Descriptions Bit Field Type Reset Description 31-0 VD R 0h 32-bit signed value indicating applied phase voltage in d-q domain. Negative value represented in two's complement. Vd (in Volts) = MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.22 VQ Register (Offset = 4F2h) [Reset = 00000000h]

VQ is shown in Figure 6-126 and described in Table 6-92. Return to the Summary Table. VQ Voltage Register Figure 6-126. VQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VQ R-0h Table 6-92. VQ Register Field Descriptions Bit Field Type Reset Description 31-0 VQ R 0h 32-bit signed value indicating applied phase voltage in d-q domain. Negative value represented in two's complement. Vq (in Volts) = www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: MCF8316D

6.8.5.23 IQ_REF_ROTOR_ALIGN Register (Offset = 52Ah) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in Figure 6-127 and described in Table 6-93. Return to the Summary Table. Align Current Reference Figure 6-127. IQ_REF_ROTOR_ALIGN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IQ_REF_ROTOR_ALIGN R-0h Table 6-93. IQ_REF_ROTOR_ALIGN Register Field Descriptions Bit Field Type Reset Description 31-0 IQ_REF_ROTOR_ALIGN R 0h 32-bit signed value indicating current reference during align state. Negative value represented in two's complement. Current reference during Align State (in Amps) = (IQ_REF_ROTOR_ALIGN / 227) * MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.24 SPEED_REF_OPEN_LOOP Register (Offset = 540h) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in Figure 6-128 and described in Table 6-94. Return to the Summary Table. Speed at which motor transitions to close loop Figure 6-128. SPEED_REF_OPEN_LOOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPEED_REF_OPEN_LOOP R-0h Table 6-94. SPEED_REF_OPEN_LOOP Register Field Descriptions Bit Field Type Reset Description 31-0 SPEED_REF_OPEN_LO OP R 0h 32-bit signed value indicating open loop speed reference. Negative value represented in two's complement. Speed reference during open loop (in Hz) = (SPEED_REF_OPEN_LOOP / 227) * MAX_SPEED (in Hz) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: MCF8316D

6.8.5.25 IQ_REF_OPEN_LOOP Register (Offset = 550h) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in Figure 6-129 and described in Table 6-95. Return to the Summary Table. Open Loop Current Reference Figure 6-129. IQ_REF_OPEN_LOOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IQ_REF_OPEN_LOOP R-0h Table 6-95. IQ_REF_OPEN_LOOP Register Field Descriptions Bit Field Type Reset Description 31-0 IQ_REF_OPEN_LOOP R 0h 32-bit signed value indicating current reference during open loop. Negative value represented in two's complement. Current reference during open loop (in Amps) = (IQ_REF_OPEN_LOOP / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.26 SPEED_REF_CLOSED_LOOP Register (Offset = 5D2h) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in Figure 6-130 and described in Table 6-96. Return to the Summary Table. Speed Reference Register Figure 6-130. SPEED_REF_CLOSED_LOOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPEED_REF_CLOSED_LOOP R-0h Table 6-96. SPEED_REF_CLOSED_LOOP Register Field Descriptions Bit Field Type Reset Description 31-0 SPEED_REF_CLOSED_L OOP R 0h 32-bit signed value indicating reference for closed loop. Negative value represented in two's complement. In speed control mode, speed reference in closed loop (in Hz)= (SPEED_REF_CLOSED_LOOP/ 227) * MAX_SPEED (in Hz). In power mode, power reference in closed loop (in Watts) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_POWER (in Watts) In current mode, Iq current reference in closed loop (in Amps) = (SPEED_REF_CLOSED_LOOP / 227) * ILIMIT(in Amps) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: MCF8316D

6.8.5.27 ID_REF_CLOSED_LOOP Register (Offset = 612h) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in Figure 6-131 and described in Table 6-97. Return to the Summary Table. Reference for Current Loop Register Figure 6-131. ID_REF_CLOSED_LOOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_REF_CLOSED_LOOP R-0h Table 6-97. ID_REF_CLOSED_LOOP Register Field Descriptions Bit Field Type Reset Description 31-0 ID_REF_CLOSED_LOOP R 0h 32-bit signed value indicating d-axis(flux component) phase current reference in closed loop . Negative value represented in two's complement. Flux component phase current reference in closed loop (in Amps) = (ID / 227) * 10/8 MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.28 IQ_REF_CLOSED_LOOP Register (Offset = 614h) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in Figure 6-132 and described in Table 6-98. Return to the Summary Table. Reference for Current Loop Register Figure 6-132. IQ_REF_CLOSED_LOOP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IQ_REF_CLOSED_LOOP R-0h Table 6-98. IQ_REF_CLOSED_LOOP Register Field Descriptions Bit Field Type Reset Description 31-0 IQ_REF_CLOSED_LOOP R 0h 32-bit signed value indicating q-axis(torque component) phase current reference in closed loop. Negative value represented in two's complement. Torque component phase current reference in closed loop (in Amps) = (IQ / 227) * 10/8 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: MCF8316D

6.8.5.29 ISD_STATE Register (Offset = 6AEh) [Reset = 0000h]

ISD_STATE is shown in Figure 6-133 and described in Table 6-99. Return to the Summary Table. ISD state Register Figure 6-133. ISD_STATE Register 15 14 13 12 11 10 9 8 ISD_STATE R-0h 7 6 5 4 3 2 1 0 ISD_STATE R-0h Table 6-99. ISD_STATE Register Field Descriptions Bit Field Type Reset Description 15-0 ISD_STATE R 0h 16-bit value indicating current ISD state 0h = ISD_INIT 1h = ISD_MOTOR_STOP_CHECK 2h = ISD_ESTIM_INIT 3h = ISD_RUN_MOTOR_CHECK 4h = ISD_MOTOR_DIRECTION_CHECK 5h = ISD_COMPLETE 6h = ISD_FAULT MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.30 ISD_SPEED Register (Offset = 6B8h) [Reset = 00000000h]

ISD_SPEED is shown in Figure 6-134 and described in Table 6-100. Return to the Summary Table. ISD Speed Register Figure 6-134. ISD_SPEED Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISD_SPEED R-0h Table 6-100. ISD_SPEED Register Field Descriptions Bit Field Type Reset Description 31-0 ISD_SPEED R 0h 32-bit value indicating calculated absolute speed during ISD state Speed estimated during ISD (in Hz) = (ISD_SPEED / 227) * MAX_SPEED (in Hz) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: MCF8316D

6.8.5.31 IPD_STATE Register (Offset = 6EAh) [Reset = 0000h]

IPD_STATE is shown in Figure 6-135 and described in Table 6-101. Return to the Summary Table. IPD state Register Figure 6-135. IPD_STATE Register 15 14 13 12 11 10 9 8 IPD_STATE R-0h 7 6 5 4 3 2 1 0 IPD_STATE R-0h Table 6-101. IPD_STATE Register Field Descriptions Bit Field Type Reset Description 15-0 IPD_STATE R 0h 16-bit value indicating current IPD state 0h = IPD_INIT 1h = IPD_VECTOR_CONFIG 2h = IPD_RUN 3h = IPD_SLOW_RISE_CLOCK 4h = IPD_SLOW_FALL_CLOCK 5h = IPD_WAIT_CURRENT_DECAY 6h = IPD_GET_TIMES 7h = IPD_SET_NEXT_VECTOR 8h = IPD_CALC_SECTOR_RISE 9h = IPD_CALC_ROTOR_POSITION Ah = IPD_CALC_ANGLE Bh = IPD_COMPLETE Ch = IPD_FAULT MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.32 IPD_ANGLE Register (Offset = 72Eh) [Reset = 00000000h]

IPD_ANGLE is shown in Figure 6-136 and described in Table 6-102. Return to the Summary Table. Calculated IPD Angle Register Figure 6-136. IPD_ANGLE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPD_ANGLE R-0h Table 6-102. IPD_ANGLE Register Field Descriptions Bit Field Type Reset Description 31-0 IPD_ANGLE R 0h 32-bit signed value indicating measured IPD angle. Negative value represented in two's complement. IPD Angle (in degrees) = (IPD_ANGLE / 227) * 360 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: MCF8316D

6.8.5.33 ED Register (Offset = 772h) [Reset = 00000000h]

ED is shown in Figure 6-137 and described in Table 6-103. Return to the Summary Table. Estimated BEMF EQ Register Figure 6-137. ED Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ED R-0h Table 6-103. ED Register Field Descriptions Bit Field Type Reset Description 31-0 ED R 0h 32-bit signed value indicating estimated Back EMF along the D-Axis (Ed). Negative value represented in two's complement. Ed (in Volts) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.34 EQ Register (Offset = 774h) [Reset = 00000000h]

EQ is shown in Figure 6-138 and described in Table 6-104. Return to the Summary Table. Estimated BEMF ED Register Figure 6-138. EQ Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EQ R-0h Table 6-104. EQ Register Field Descriptions Bit Field Type Reset Description 31-0 EQ R 0h 32-bit signed value indicating estimated Back EMF along the Q-Axis (Eq). Negative value represented in two's complement. Eq (in Volts) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: MCF8316D

6.8.5.35 SPEED_FDBK Register (Offset = 782h) [Reset = 00000000h]

SPEED_FDBK is shown in Figure 6-139 and described in Table 6-105. Return to the Summary Table. Speed Feedback Register Figure 6-139. SPEED_FDBK Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPEED_FDBK R-0h Table 6-105. SPEED_FDBK Register Field Descriptions Bit Field Type Reset Description 31-0 SPEED_FDBK R 0h 32-bit signed value indicating estimated motor speed. Negative value represented in two's complement. Estimated Motor Speed (in Hz) = (SPEED_FDBK / 227) * MAX_SPEED (in Hz) MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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6.8.5.36 THETA_EST Register (Offset = 786h) [Reset = 00000000h]

THETA_EST is shown in Figure 6-140 and described in Table 6-106. Return to the Summary Table. Estimated rotor Position Register Figure 6-140. THETA_EST Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THETA_EST R-0h Table 6-106. THETA_EST Register Field Descriptions Bit Field Type Reset Description 31-0 THETA_EST R 0h 32-bit signed value indicating estimated rotor angle. Angle should be modulo 360 degrees. For example if the estimated Angle value 380 degrees then it means 380%360 = 20 degrees Estimated rotor Angle (in degrees) = (THETA_EST / 227)*360 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 215 Product Folder Links: MCF8316D

7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

The MCF8316D device is used in sensorless 3-phase BLDC motor control. The driver provides a high performance, high-reliability, flexible solution for appliances, fans, pumps, residential and living fans, seat cooling fans, automotive fans and blowers. The following section shows a common application of the MCF8316D device.

7.2 Typical Applications

Figure 7-1 shows the typical schematic of MCF8316D. GND_BK SW_BK FB_BK RBK AVDD AGND VVM VMCP CPH CPL OUTA OUTB OUTC DRVOFF 47 nF CBK 1 µF 0.1 µF >10 µF SDA SCL I2C nFAULT PGND MCF8316D External Load DVDD AGND CAVDD FG RFG BRAKE DIR RSDA AVDD or EXT SUPPLY EXT_CLK EXT_WD SOX Optional Control Interface Optional Serial Interface LBK Replace resistor (RBK) with inductor (LBK) for larger external load or to reduce power dissipaon 1 µF 1 µF CDVDD AVDD or EXT SUPPLY RnFAULT RSCL SPEED/WAKE (PWM/Analog/Freq) DACOUT1 DACOUT2 ALARM Optional external pull-up resistors Figure 7-1. Example Application Schematic Table 7-1 lists the recommended values of the external components for MCF8316D. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Table 7-1. MCF8316D External Components COMPONENTS PIN 1 PIN 2 RECOMMENDED CVM1 VM PGND X7R, 0.1µF, TI recommends a capacitor voltage rating at least twice the operating voltage of the device (VM) CVM2 VM PGND ≥ 10µF, TI recommends a capacitor voltage rating at least twice the operating voltage of the device (VM) CCP CP VM X7R, 1µF, 16V capacitor CFLY CPH CPL X7R, 47nF, TI recommends a capacitor voltage rating at least twice the operating voltage of the device (VM) CAVDD AVDD AGND X7R, 1µF, ≥10V. In order for AVDD to accurately regulate output voltage, capacitor should have effective capacitance between 0.7µF to 1.3µF at 3.3V across operating temperature. CDVDD DVDD DGND X7R, 1µF, ≥ 6.3V. In order for DVDD to accurately regulate output voltage, capacitor should have effective capacitance between 0.7µF to 2.5µF at 1.5V across operating temperature. CBK FB_BK GND_BK X7R, buck-output rated capacitor LBK SW_BK FB_BK Buck-output inductor RFG 1.8 to 5V Supply FG 5.1kΩ, Pull-up resistor RnFAULT 1.8 to 5V Supply nFAULT 5.1kΩ, Pull-up resistor RSDA 1.8 to 3.3V Supply SDA 5.1kΩ, Pull-up resistor RSCL 1.8 to 3.3V Supply SCL 5.1kΩ, Pull-up resistor Recommended application range for MCF8316D is shown in Table 7-2. Table 7-2. Recommended Application Range Parameter Min Max Unit Motor voltage 4.5 35 V Back-EMF constant (see Section 6.3.13.3) 0.6 2000 mV/Hz Motor resistance (see Section 6.3.13.1) 0.006 20 Ω Motor inductance (see Section 6.3.13.2) 0.006 20 mH Motor electrical speed - 1500 Hz Peak motor phase current - 8 A

7.2.1 Application Curves

7.2.1.1 Motor startup

Figure 7-2 shows the FG waveform and the phase current waveform at different motor operations. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: MCF8316D

Figure 7-2. Motor Startup - FG and Phase current

7.2.1.2 MPET

Figure 7-3 shows the phase current waveform during motor parameter measurement. Figure 7-4 shows the IPD current waveform during R, L and Ke measurement. Bottom half of Figure 7-4 shows the IPD current waveform during R and L measurement. R is measured during the rising of phase current and L is measured during the falling of phase current. After R and L measurement, motor spins in open loop. Once the speed reaches MPET open loop speed reference [MPET_OPEN_LOOP_SPEED_REF], motor is coasted. BEMF voltage of all three phases are measured and Ke is calculated. Figure 7-3. MPET - Phase current Figure 7-4. IPD current waveform during Rand L measurement

7.2.1.3 Dead time compensation

Figure 7-5 shows the phase current waveform when dead time compensation is disabled. Fundamental frequency of phase current is 40 Hz. Fast Fourier transform (FFT) of phase current plot shows harmonics at MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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160 Hz and 220 Hz. Figure 7-6 shows the phase current waveform when dead time compensation is enabled. Phase current looks more sinusoidal and the FFT of phase current plot does not have any harmonics. Figure 7-5. Phase current and FFT - Dead time compensation disabled Figure 7-6. Phase current and FFT - Dead time compensation enabled

7.2.1.4 Auto handoff

Figure 7-7 shows the auto handoff feature in MCF8316D where the motor transitions seamlessly from open loop to closed loop. Figure 7-7. Auto-handoff

7.2.1.5 Anti voltage surge (AVS)

When motor speed decelerates at a very high deceleration rate, mechanical energy from the motor returns to the power supply which could result in pumping up the supply voltage, VM. Figure 7-8 shows overshoot in power supply voltage when AVS is disabled. Motor decelerates from 100% duty cycle to 10% duty cycle at a deceleration rate of 70,000 Hz/sec. Figure 7-9 shows no overshoot in power supply voltage when AVS is enabled. www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: MCF8316D

Figure 7-8. Power supply voltage and phase current waveform when AVS is disabled Figure 7-9. Power supply voltage and phase current waveform when AVS is enabled

7.2.1.6 Real time variable tracking using DACOUT

MCF8316D has two 12-bit DAC which outputs analog voltage equivalent of digital variables on DACOUT1 and DACOUT2 pins with resolution of 12 bits and max voltage of 3V. Signals available on DACOUT pins can be used for tuning speed controller or other driver configuration or bus current monitoring. Check algorithm variable registers in datasheet for list of all algorithm variables. The addresses for variables for DACOUT1 and DACOUT2 are configured using register bits DACOUT1_VAR_ADDR and DACOUT2_VAR_ADDR. This is useful in applications which require tracking algorithm variables in real time without having any delay from the communication bus. Pin 37 and 38 should be configured as DACOUT1 and DACOUT2. For example, if the user wants to read phase A current from pin 37, configure pin 37 as DACOUT1 and program the phase A current register address (0x00000440) in Hex in [DACOUT1_VAR_ADDR]. If the user wants to read estimated rotor angle from pin 38, configure pin 38 as DACOUT2 and program the estimated rotor angle register address (0x00000736) in Hex in [DACOUT2_VAR_ADDR]. Figure 7-10 shows the outputs of DACOUT1 and DACOUT2. DACOUT1 is configured to read phase A current and DACOUT2 is configured to read estimated rotor angle. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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Figure 7-10. DACOUT1 and DACOUT2 www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: MCF8316D

8 Power Supply Recommendations

8.1 Bulk Capacitance

Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors, including:

• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method The inductance between the power supply and the motor drive system limits the rate at which current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in VM voltage. When adequate bulk capacitance is used, the VM voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate bulk capacitor. Local Bulk Capacitor Parasitic Wire Inductance Motor Driver Power Supply Motor Drive System VM GND IC Bypass Capacitor Figure 8-1. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply. MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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9 Layout

9.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize parasitic inductance and allow the bulk capacitor to deliver high current. Small-value capacitors should be ceramic, and placed closely to device pins. The high-current device outputs should use wide metal traces. To reduce noise coupling and EMI interference from large transient currents into small-current signal paths, grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to reduce voltage offsets and maintain gate driver performance. The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate the I2 × RDS(on) heat that is generated in the device. To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and improve thermal dissipation from the die surface. Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching. Figure 9-1 shows a layout example for the MCF8316D . Also, for layout example, refer to MCF8316D EVM . www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 223 Product Folder Links: MCF8316D

9.2 Layout Example

Figure 9-1. Recommended Layout Example MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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9.3 Thermal Considerations

The MCF8316D has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C (minimally) disables the device until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient heatsinking, or too high an ambient temperature.

9.3.1 Power Dissipation

The power dissipated in the output FET resistance (RDS(on)) dominates power dissipation in MCF8316D. At start-up and fault conditions, the FET current is much higher than normal operating FET current; remember to take these peak currents and their duration into consideration. The total device power dissipation is the power dissipated in each of the three half-bridges added together along with standby power, LDO and buck regulator losses. The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking. Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when sizing the heatsink. A summary of equations for calculating each loss is shown below in Table 9-1. Table 9-1. Power Losses for MCF8316D Loss type MCF8316D Standby power Pstandby = VM x IVM_TA LDO PLDO = (VM-VAVDD) x IAVDD, if BUCK_PS_DIS = 1b PLDO = (VBK-VAVDD) x IAVDD, if BUCK_PS_DIS = 0b FET conduction PCON = 3 x (IRMS(FOC))2 x Rds,on(TA) FET switching PSW = 3 x IPK(FOC) x VPK(FOC) x trise/fall x fPWM Diode Pdiode = 3 x IPK(FOC) x Vdiode x tdead x fPWM Buck PBK = 0.11 x VBK x IBK (ηBK = 90%) www.ti.com MCF8316D SLLSFX9 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 225 Product Folder Links: MCF8316D

10 Device and Documentation Support

10.1 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.2 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.4 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated device. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. DATE REVISION NOTES December 2024 * Initial Release MCF8316D SLLSFX9 – DECEMBER 2024 www.ti.com

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