MCF51AC256 FREESCALE | Alldatasheet
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Data Sheet: Advance Information Document Number: MCF51AC256 Rev.1 , 06/2008 © Freescale Semiconductor, Inc., 2008. All rights reserved. Preliminary—Subject to Change Without Notice This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MCF51AC256
80 LQFP
14 mm × 14 mm
64 LQFP
10 mm × 10 mm
64 QFP
14 mm × 14 mm The MCF51AC256 is a member of the ColdFire® family of 32-bit variable-length reduced instruction set (RISC) microcontroller. This document provides an overview of the MCF51AC256 series, focusing on its highly integrated and diverse feature set. The MCF51AC256 series is based on the V1 ColdFire core and operates at processor core speeds up to 50.33 MHz. As part of Freescale’s Controller Continuum ®, it is an ideal upgrade for designs based on the MC9S08AC128 series of 8-bit microcontrollers. The MCF51AC256 features the following functional units:
- V1 ColdFire core with background debug module
- Up to 256 KBytes of flash memory
- Up to 32 Kbytes of static RAM (SRAM)
- Up to two analog comparators (ACMP)
- Analog-to-digital converter (ADC) with up to 24 channels
- Controller-area network (CAN)
- Cyclic redundancy check (CRC)
- Inter-integrated circuit (IIC)
- Keyboard interrupt (KBI)
- Multipurpose clock generator (MCG)
- Rapid general-purpose input/output (RGPIO)
- Two serial communica tions interfaces (SCI)
- Up to two serial parallel interfaces (SPI)
- Two flexible timer modules (FTM)
- Timer pulse-width modulator (TPM) MCF51AC256 ColdFire Microcontroller
2.4 Electrostatic Discharge (ESD)
1 MCF51AC256 Family Configurations
1.1 Device Comparison
The MCF51AC256 series is summarized in Table 1. Table 1. MCF51AC256 Series Device Comparison
1.2 Block Diagram
Figure 1 shows the connections between the MCF51AC256 series pins and modules. Figure 1. MCF51AC256 Block Diagram 1 The members of MCF51AC128 with CAN support have 32 K-byte RAM. The other members have 16 K-byte RAM. 2 Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module.
1.3 Features
Table 2 describes the functional units of the MCF51AC256 series. Table 2. MCF51AC256 Series Functional Units
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice MCF51AC256 Family Configurations Freescale Semiconductor6
1.3.1 Feature List
- 32-bit Version 1 ColdFire® central processor unit (CPU) — Up to 50.33 MHz at 2.7 V – 5.5 V — Provide 0.94 Dhrystone 2.1 DMIPS per MHz performan ce when running from internal RAM (0.76 DMIPS per MHz when running from flash) — Implements instruction set revision C (ISA_C)
- On-chip memory — Up to 256 KBytes flash memory read/program/erase over full operating voltage and temperature — Up to 32 KBytes static random access memory (SRAM) — Security circuitry to prev ent unauthorized access to SRAM and flash contents
- Power-Saving Modes — Three low-power stop plus wait modes — Peripheral clock enable register can disable clocks to unu sed modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
- System protection features — Watchdog computer operating properly (COP) reset — Low-voltage detection with reset or interrupt — Illegal opcode and illegal address detection with programmable reset or exception response — Flash block protection
- Debug support — Single-wire background debug interface — Real-time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger — On-chip trace buffer provides progra mmable start/stop recording conditions plus support for continuous or PC-profiling modes — Support for real-time program (and optional pa rtial data) trace using the debug visibility bus
- V1 ColdFire interrupt controller (CF1_INTC) — Support of 40 peripheral I/O interrupt requests plus seven software (one per level) interrupt requests — Fixed association between interrupt request source and leve l plus priority, up to two requests can be remapped to the highest maskable level + priority — Unique vector number fo r each interrupt source — Support for service routine interrupt acknowledge (softw are IACK) read cycles for improved system performance
- Multipurpose clock generator (MCG) — Oscillator (XOSC); loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or
1 MHz to 16 MHz
— FLL/PLL controlled by internal or external reference — Trimmable internal reference allows 0.2% resolution and 2% deviation
- Analog-to-digital converter (ADC) — 24 analog inputs with 12 bits resolution — Output formatted in 12-, 10- or 8-bit right-justified format — Single or continuous conversion (automatic return to idle after single conversion) — Operation in low-power modes for lower noise operation — Asynchronous clock source for lower noise operation — Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value — On-chip temperature sensor
MCF51AC256 Family Configurations MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 7
- Flexible timer/pulse-width modulators (FTM) — 16-bit Free-running counter or a counter with initial and final value. The counting can be up and unsigned, up and signed, or up-down and unsigned — Up to 6 channels, and each channel can be configured for input capture, output compare or edge-aligned PWM mode, all channels can be configured for center-aligned PWM mode – Channels can operate as pairs with equal outputs, pair s with complimentary outputs or independent channels (with independent outputs) – Each pair of channels can be combined to generate a PWM signal (with independent control of both edges of PWM signal) – Deadtime insertion is available for each complementary pair — The load of the FTM registers which have write buffer can be synchronized; write protection for critical registers — Generation of the triggers to ADC (hardware trigger) — A fault input for global fault control — Backwards compatible with TPM
- Timer/pulse width modulator (TPM) — 16-bit free-running or modulo up/down count operation — Two channels, each channel may be input cap ture, output compare, or edge-aligned PWM — One interrupt per channel plus terminal count interrupt
- Cyclic redundancy check (CRC) generator — High speed hardware CRC generator circuit using 16-bit shift register — CRC16-CCITT comp liancy with x16 + x12 + x5 + 1 polynomial — Error detection for all single, double, odd, and most multi-bit errors — Programmable initial seed value
- Analog comparators (ACMP) — Full rail to rail supply operation — Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output — Option to compare to fixed internal bandgap reference voltage — Option to allow comparator output to be visible on a pin, ACMPxO
- Inter-integrated circuit (IIC) — Compatible with IIC bus standard — Multi-master operation — Software programmable for one of 64 different serial clock frequencies — Interrupt driven byte- by-byte data transfer — Arbitration lost interrupt with automatic mode switching from master to slave — Calling address identification interrupt — Bus busy detection — 10-bit address extension
- Controller area network (CAN) — Implementation of the CAN protocol — Version 2.0A/B – Standard and extended data frames – Zero to eight bytes data length – Programmable bit rate up to 1 Mbps – Support for remote frames — Five receive buffers with FIFO storage scheme — Three transmit buffers with internal prio ritization using a “local priority” concept
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice MCF51AC256 Family Configurations Freescale Semiconductor8 — Flexible maskable identifier filter su pports two full-size (32-bit) extended identifier filters, four 16-bit filters, or eight 8-bit filters — Programmable wakeup functionality with integrated low-pass filter — Programmable loopback mode supports self-test operation — Programmable listen-only mode for monitoring of CAN bus — Programmable bus-off recovery functionality — Separate signalling and inte rrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) — Internal timer for time- stamping of received and transmitted messages
- Serial communications interfaces (SCI) — Full-duplex, standard non-return-to-zero (NRZ) format — Double-buffered transmitter and receiver with separate enables — Programmable baud rates (13-bit modulo divider) — Interrupt-driven or polled operation — Hardware parity gene ration and checking — Programmable 8-bit or 9-bit character length — Receiver wakeup by idle-line or address-mark — Optional 13-bit break character genera tion / 11-bit break character detection — Selectable transmitter output polarity
- Serial peripheral interfaces (SPI) — Master or slave mode operation — Full-duplex or single-wire bidirectional option — Programmable transmit bit rate — Double-buffered tr ansmit and receive — Serial clock phase and polarity options — Slave select output — Selectable MSB-first or LSB-first shifting — 16-bit and FIFO operations in SPI2
- Input/Output — 69 GPIOs — 8 keyboard interrupt pins with selectable polarity — Hysteresis and configurable pull-up device on all input pins ; Configurable slew rate and drive strength on all output pins — 16-bits Rapid GPIO pins connected to the processor’s lo cal 32-bit platform bus with set, clear, and faster toggle functionality
1.4 Part Numbers
(V = –40°C to 105°C, C= –40°C to 85°C ) (MCF = Fully Qualified ColdFire) MCF AC 256 XX E Memory size designator V51 (PCF = Product Engineering) X CAN Feature (A: With CAN, B/C: Without CAN)
Table 3. Orderable Part Number Summary
1.5 Pinouts and Packaging
Figure 2 shows the pinout of the 80-pin LQFP. Figure 2. 80-Pin LQFP Figure 3 shows the pinout of the 64-pin LQFP and QFP.
- PTA0 / TxCAN PTD6 / FTM1CLK / AD1P14 PTD5 / AD1P13 PTD4/FTM2CLK/AD1P12 PTG0 / KBI1P0 PTG4 / KBI1P4 / AD1P19 PTG1 / KBI1P1 PTC6 / FTM2FLT PTF7 / RGPIO15 PTE2 / RGPIO2 / FTM1CH0 PTE3 / RGPIO3 / FTM1CH1 PTH0 / FTM2CH2 / AD1P20 PTB1 / TPM3CH1 / AD1P1 PTB0 / TPM3CH0 / AD1P0 PTA7 / AD1P17 PTH4 / SPCK2 PTC1 / SDA1 BKGD / MS VREFL
- PTA1 / RxCAN PTA2 PTA3 / ACMP2O PTA4 / ACMP2– PTA5 / ACMP2+ PTA6 / AD1P16 PTE4 / RGPIO4 / SS1 PTE5 / RGPIO5 / MISO1 VSS VDD PTE6 / RGPIO6 / MOSI1 PTE7 / RGPIO7 / SPSCK1 PTJ4 / DDATA0 PTJ5 / DDATA1 VDD
- TxCAN and RxCAN are not available in the members that do not support CAN
Figure 3. 64-Pin QFP and LQFP Table 4 shows the package pin assignments. Table 4. Pin Availability by Package Pin-Count
22 I R Q T P M C L K 1
- PTA0 / TxCAN
- PTA1 / RxCAN PTA2 PTA3 / ACMP2O PTB5 / AD1P5 PTB4 / AD1P4 PTB3 / AD1P3 PTB2 / AD1P2 PTG6 / EXTAL VSS PTC0 / SCL1 PTC1 / SDA1 PTF1 / RGPIO9 / FTM1CH3 PTE1 / RGPIO1 / RxD1 PTE2 / RGPIO2 / FTM1CH0 PTA4 / ACMP2- PTD2 / KBI1P5 / AD1P10 /ACMP1O PTD3 / KBI1P6 / AD1P1147 PTC3 / TxD263 PTC2 / MCLK PTC4 IRQ / TPMCLK PTE4 / RGPIO4 / SS1 PTE5 / RGPIO5 / MISO1 PTA5 / ACMP2+ PTA6 / AD1P16 PTB0 / TPM3CH0 / AD1P0 PTA7 / AD1P17 PTD4 / FTM2CLK / AD1P12 PTG4 / KBI1P4 / AD1P19 64-Pin QFP 64-Pin LQFP
- TxCAN and RxCAN are not available in the members that do not support CAN
Table 4. Pin Availability by Package Pin-Count (continued)
1 TPMCLK, FTM1CLK, and FTM2CLK options are configured
2 TxCAN is available in the member that supports CAN. 3 RxCAN is available in the member that supports CAN.
2 Preliminary Electrical Characteristics
including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications.
2.1 Parameter Classification
2.2 Absolute Maximum Ratings
conditions, refer to the remaining tables in this section. Table 5. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. sample size across process variations. D Those parameters are derived mainly from simulations.
2.3 Thermal Characteristics
(heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 6. Absolute Maximum Ratings voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating VDD range during instantaneous and
Table 7. Thermal Characteristics
1 Junction temperature is a function of die size, on-chip power dissipation, package thermal
of other components on the board, and board thermal resistance.
2.4 Electrostatic Discharge (E SD) Protection Characteristics
can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. temperature followed by hot temperature, unless specified otherwise in the device specification.
2 Junction to Ambient Natural Convection
Table 8. ESD and Latch-up Test Conditions
2.5 DC Characteristics
Table 9. ESD and Latch-Up Protection Characteristics
1 Human Body Model (HBM) V HBM ±2000 — V
2 Machine Model (MM) V MM ±200 — V
3 Charge Device Model (CDM) V CDM ±500 — V
4 Latch-up Current at T A = 85°CI LAT ±100 — mA
Table 10. DC Characteristics
5 V, ILoad = –4 mA
3 V, ILoad = –2 mA
5 V, ILoad = –2 mA
3 V, ILoad = –1 mA
5 V, I
3 V, ILoad = –8 mA
5 V, ILoad = –8 mA
3 V, ILoad = –4 mA
5 V, ILoad = 4 mA
3 V, ILoad = 2 mA
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
3 V, ILoad = 8 mA
5 V, ILoad = 8 mA
3 V, ILoad = 4 mA
Table 8. ESD and Latch-up Test Conditions (continued)
11 P Internal pullup resistors 3 RPU 20 45 65 k Ω
12 P Internal pulldown resistors 4 RPD 20 45 65 k Ω
13 C Input Capacitance; all non-supply pins C In —— 8 p F
15 D POR rearm time t POR 10 — — μs
Table 10. DC Characteristics (continued)
1 Typical values are based on characterization data at 25°C unless otherwise stated. 2 Measured with VIn = VDD or VSS.
5 Power supply must maintain regulation within operating VDD range during instantaneous and operating
6 All functional non-supply pins are internally clamped to VSS and VDD. 8 The RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD.
2.6 Supply Current Characteristics
Table 11. Supply Current Characteristics 1 Typicals are measured at 25°C. 2 Values given here are preliminary estimates prior to completing characterization. 3 All modules clocks switch on, code run from flash, FEI mode, and does not include any dc loads on port pins.
6 C RTI adder to stop2 or stop3 4, 25°C
7 C LVD adder to stop3 (LVDE = LVDSE = 1) S3I DDLVD
5 Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
2.7 Analog Comparator (ACMP) Electricals
2.8 ADC Characteristics
Table 12. Analog Comparator Electrical Specifications
2 T Supply current (active) I DDAC —2 03 5 μA
4 D Analog input offset voltage V AIO 20 40 mV
Table 13. 5 Volt 12-bit ADC Operating Conditions
Figure 8. ADC Input Impedance Equivalency Diagram reference only and are not tested in production. Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Table 14. 5 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
2.9 External Oscillator (XOSC) Characteristics
only and are not tested in production.
3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes
4 Based on input pad leakage current. Refer to pad electricals. Table 15. Oscillator Electrical Specifications (Temperature Range = –40 to 105°C Ambient) 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. manufacturer’s recommendation.
4 MHz
1 MHz
2.10 MCG Specifications
Table 16. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
4 D Internal reference startup time t irefst — 60 100 μs
1024 X fint_ut
6 D DCO output frequency range - trimmed f dco_t 32 — 40 MHz
11 D FLL acquisition time 2 tfll_acquire —— 1 m s
12 D PLL acquisition time 3 tpll_acquire —— 1 m s
13 D Long term Jitter of DCO output clock
17 D Jitter of PLL output clock measured
2.11 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
20 D Lock time — FLL t fll_lock —— tfll_acquire+
21 D Lock time — PLL t pll_lock —— tpll_acquire+
1 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0). this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. the sample point of a bit using 8 time quanta per bit. is already in lock, then the MCG may stay in lock. 7 Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock. Table 16. MCG Frequency Specifications (continued)(Temperature Range = –40 to 125°C Ambient)
2.11.1 Control Timing
Figure 9. Reset Timing Table 17. Control Timing 1 Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
1 D Bus frequency (t cyc = 1/fBus)f Bus dc — 24 MHz
2 D Internal low-power oscillator period t LPO 800 1500 μs
override reset requests from internal sources.
4 D Reset low drive t rstdrv 66 x tcyc —n s
5 D Active background debug mode latch setup time t MSSU 500 — ns
6 D Active background debug mode latch hold time t MSH 100 — ns
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C.
Figure 10. IRQ/KBIPx Timing
2.11.2 Timer (TPM/FTM) Module Timing
optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Figure 11. Timer External Clock Figure 12. Timer Input Capture Pulse Table 18. TPM/FTM Input Timing
2.11.3 MSCAN
Table 19. MSCAN Wake-up Pulse Characteristics 1 Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
1 D MSCAN Wake-up dominant pulse filtered t WUP 2 μs
2 D MSCAN Wake-up dominant pulse pass t WUP 55 μs
2.12 SPI Characteristics
Table 20 and Figure 13 through Figure 16 describe the timing requirements for the SPI system. Table 20. SPI Electrical Characteristic 1 Refer to Figure 13 through Figure 16. assumes slew rate control disabled and high drive strength enabled for SPI output pins.
9 D Access time, slave
3 Time to data active from high-impedance state.
10 D Disable time, slave 4
4 Hold time to high-impedance state.
Figure 15. SPI Slave Timing (CPHA = 0) Figure 16. SPI Slave Timing (CPHA = 1)
2.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
- Not defined but normally MSB of character just received
- Not defined but normally LSB of character just received
2.14 EMC Performance
2.14.1 Radiated Emissions
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. Table 21. Flash Characteristics 1 Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated. 2 The frequency of this clock is controlled by a software setting. supplied for calculating approximate time to program and erase. Endurance for Nonvolatile Memory.
10 C Data retention 5
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings Freescale Semiconductor36
3 Mechanical Outline Drawings
3.1 80-pin LQFP Package
Mechanical Outline Drawings MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 37
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings Freescale Semiconductor38
Mechanical Outline Drawings MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 39 3.2 64-pin LQFP Package
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings Freescale Semiconductor40
Mechanical Outline Drawings MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 41
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings Freescale Semiconductor42 3.3 64-pin QFP Package
Mechanical Outline Drawings MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 43
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings Freescale Semiconductor44
Revision History
MCF51AC256 ColdFire Microcontroller Data Sheet, Rev.1 Preliminary—Subject to Change Without NoticeFreescale Semiconductor 45
4 Revision History
Table 22. Revision History
1 Initial published
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