MCC14LC5003

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3–3 MC14LC5002 • MC14LC5003 • MC14LC5004 MOTOROLA 72-Segment / 128-Segment LCD Drivers CMOS The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Driv- ers. The MC14LC5002 is the same as MC14LC5003 except for 72 segments. The three devices are functionally the same except for their data input pro- tocols. The MC14LC5002/5003 use a serial interface data input protocol. The devices may be interfaced to the MC68HCXX product families using a minimal amount of software (see example). The MC14LC5004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowl- edge bit back to the transmitter after each eight-bit byte is received. MC14LC5004 also has a “read mode”, whereby data sent to the device may be retrieved via the IIC bus. The MC14LC5002/5003/5004 drive the liquid crystal displays in a multi- plexed-by-four configuration. The devices accept data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. Devices are independently addressable via a two-wire (or three-wire) com- munication link which can be common with other peripheral devices. The MC14LC5003/5004 are low cost version of MC145003 and MC145004 without cascading function. Drives 72 Segments Per MC14LC5002’s Package Drives 128 Segments Per MC14LC5003/5004’s Package May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom Quiescent Supply Current: 30 µ A @ 2.7 V V DD Operating Voltage Range: 2.7 to 5.5 V Operating Temperature Range: -40 to 85 C Separate Access to LCD Drive Section’s Supply Voltage to Allow for Tem- perature Compensation See Application Notes AN1066 and AN442 MC14LC5002 MC14LC5003 MC14LC5004 QFP FU SUFFIX CASE 848B TQFP FB SUFFIX CASE 873A MC14LC5002FB TQFP MC14LC5003FU QFP MC14LC5004FU QFP MCC14LC5003 BARE DIE MCC14LC5004 BARE DIE MCC14LC5003Z AU BUMP DIE MCC14LC5004Z AU BUMP DIE

ORDERING INFORMATION

SEMICONDUCTOR TECHNICAL DATA REV 7

3–4 MC14LC5002 • MC14LC5003 • MC14LC5004 MC14LC5002 BLOCK DIAGRAM 128-BIT LATCH LCD VOLTAGE WAVEFORM AND TIMING GENERATOR FRAME SYNC GENERATOR OSCILLATOR 128-BIT SHIFT REGISTER OSC2 OSC1 POR DRIVERS DRIVERS 128 - 32 MULTIPLEX DATA AND ADDRESS CONTROL AND TIMING A0/A1 ENB DCLK D in V LCD BP1-BP4 FP1-FP4, FP9-FP12, FP17-FP20, FP25-FP28 & FP31-FP32 OSC1 FP32 FP31 FP28 FP27 FP26 FP25 FP20 MC14LC5002 OSC2 V DD BP1 BP2 BP3 BP4 A0/A1 MC14LC5002 PIN ASSIGNMENT FP19 FP18 FP17 V LCD V SS FP12 FP11 FP10 ENB Din DCLK FP1 FP2 FP3 FP4 FP9

3–5 MC14LC5002 • MC14LC5003 • MC14LC5004 MOTOROLA MC14LC5003/MC14LC5004 BLOCK DIAGRAM 128-BIT LATCH LCD VOLTAGE WAVEFORM AND TIMING GENERATOR FRAME SYNC GENERATOR OSCILLATOR 128-BIT SHIFT REGISTER OSC2 OSC1 POR DRIVERS DRIVERS 128 - 32 MULTIPLEX DATA AND ADDRESS CONTROL AND TIMING ENB DCLK D in V LCD BP1-BP4 FP1-FP32 MC14LC5003/MC14LC5004 PIN ASSIGNMENT FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 Din DCLK NC FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 MC14LC5003 OR MC14LC5004 NC FP19 FP18 FP17 FP16 FP15 V LCD VSS FP14 FP13 FP12 FP11 NC NC OSC1 OSC2 V DD BP1 BP2 BP3 BP4 ENB NC NC=NO CONNECTION

3–6 MC14LC5002 • MC14LC5003 • MC14LC5004 ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V SS * Maximum Ratings are those values beyond which damage to the device may occur. Func- tional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to V SS , T A = 25°C) (continued) Symbol Parameter Value Unit V DD DC Supply Voltage - 0.5 to + 6.5 V V in Input Voltage, D in , and Data Clock - 0.5 to + 15 V V in osc Input Voltage, OSC in of Master - 0.5 to V DD + 0.5 V I in DC Input Current, per Pin 10 mA T A Operating Temperature Range - 40 to + 85 C T stg Storage Temperature Range - 65 to + 150 C Characteristic Symbol V DD V V LCD V Min Typical Max Unit Output Drive Current — Frontplanes V O = 0.15 V I FH I FL 2.7 2.7 260 260 m A V O = 2.65 V I FH I FL 2.7 2.7 -240 -240 V O = 1.72 V I FH I FL 2.7 2.7 -40 -1.5 V O = 1.08 V I FH I FL 2.7 2.7 V O = 0.15 V I FH I FL 5.5 5.5 600 600 V O = 5.35 V I FH I FL 5.5 5.5 -520 -520 V O = 3.52 V I FH I FL 5.5 5.5 -35 -1.5 V O = 1.98 V I FH I FL 5.5 5.5 Supply Standby Currents (No Clock) I DD = Standby @ I out = 0 m A I LCD = Standby @ I out = 0 m A I DD = Standby @ I out = 0 m A I LCD = Standby @ I out = 0 m A I DDS I LCDS I DDS I LCDS 2.7 5.5 2.7 5.5 800 1500 m A Supply Currents (f OSC ) = 110 kHz I DD = Quiescent @ I out = 0 m A, no loading I DD = Quiescent @ loading = 270pF I DD = Quiescent @ I out = 0 m A, no loading I DD = Quiescent @ loading = 270pF I LCD = Quiescent @ I out = 0 m A, no loading I LCD = Quiescent @ I out = 0 m A, no loading I DDQ I DDQ I DDQ I DDQ I LCDQ I LCDQ 2.7 2.7 5.5 5.5 2.7 5.5 170 400 m A Input Current I in — — -0.1 — 0.1 m A Input Capacitance C in — — — — 7.5 pF This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precau- tions must be taken to avoid applications of any voltage higher than maximum rated volt- ages to this high-impedance circuit. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal op- eration. This device is not radiation protect- ed.

3–7 MC14LC5002 • MC14LC5003 • MC14LC5004 MOTOROLA (Continued) NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change. Characteristic Symbol V DD V V LCD V Min Typical Max Unit Frequencies OSC2 Frequency @ R1; R1 = 200 k W BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 k W f OSC2 f BP f OSC2 100 100 150 150 kHz Hz kHz Average DC Offset Voltage (BP Relative to FP)V OO 5 2.8 -50 — +50 mV Input Voltage “0” Level V IL V IL 2.8 5.5 0.85 1.65 V “1” Level V IH V IH 2.8 5.5 3.85 Output Drive Current — Backplanes V O = 2.65 V I BH I BL 2.8 2.8 -240 -240 m A V O = 0.15 V I BH I BL 2.8 2.8 260 260 V O = 1.08V I BH I BL 2.8 2.8 V O = 1.72 V I BH I BL 2.8 2.8 -40 V O = 5.35 V I BH I BL 5.5 5.5 -520 -520 V O = 0.15 V I BH I BL 5.5 5.5 600 600 V O = 1.98 V I BH I BL 5.5 5.5 V O = 3.52 V I BH I BL 5.5 5.5 -35 Pulse Width, Data Clock (Figure 1) t w 100 100 ns DCLK Rise/Fall Time (Figure 1) t r , t f 120 120 m s Setup Time, D in to DCLK (Figure 2) t su ns Hold Time, D in to DCLK (Figure 2) t h ns Hold Time for START condition (Figure 2) t start 100 100 ns Hold Time for STOP condition (Figure 2) t stop 100 100 ns DCLK Low to ENB High (Figure 3) t h ns ENB High to DCLK High (Figure 3) t rec ns ENB High Pulse Width (Figure 3) t w 100 100 ns ENB Low to DCLK High (Figure 3) t su ns

Figure 5. Frontplane Combinations

uration A0, A1, A2 = 000 is reserved for Motorola’s use only. will always latch the data after 128 bits have been received. pin must occur while DCLK is high. tocol sections for relevant option. frequency of between 30 Hz and 100 Hz. See Figure 6. Figure 6. Oscillator Frequency vs. Load Resistance

3–12 MC14LC5002 • MC14LC5003 • MC14LC5004 DATA INPUT PROTOCOL Two-wire communication bus DCLK, Din; three-wire com- munication bus DCLK, Din, ENB. MC14LC5002/5003 — SERIAL INTERFACE DEVICE (FIG- URE 7) Before communication with an MC14LC5002/5003 can be- gin, a start condition must be set up on the bus by the trans- mitter. To establish a start condition, the transmitter must pull the data line low for at least one clock-pulse time while the clock line is high. The “idle” state for the clock line and data line is the high state. After the start condition has been established, an eight-bit address (01111110) should be sent by the transmitter. If the address sent corresponds to the address of the MC14LC5002/5003 then on each successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC14LC5002/5003’s internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5002/5003, a stop condition should be set up on the bus (or another start con- dition may be set up if another communication is desired). To establish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC14LC5002/5003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as re- quired). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. MC14LC5004 — IIC DEVICE (FIGURE 8) Before communication with an MC14LC5004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data line low for at least one clock-pulse time while the clock line is high. After the start condition has been established, an eight-bit address (0111111X 0) should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit X 0 is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the controller reads from the LCD driver’s 128-bit shift register on a first-in first-out basis. If the seven most significant address bits sent correspond to the address of the LCD driver then the addressed LCD driver responds by sending an “acknowledge” bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line D in low as an acknowledgment. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC14LC5004’s internal counter latches the data to be dis- played after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5004, a stop condi- tion should be set up on the bus (or another start condition may be set up if another communication is desired). To estab- lish a stop condition, the transmitter must pull the data line high for at least one clock-pulse time while the clock line is high. Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge-related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address.

3–14 MC14LC5002 • MC14LC5003 • MC14LC5004WRITE TO LCD DRIVER READ FROM LCD DRIVER DCLK ENB (IF USED) START 8-BITS ADDRESS 8-BITS DATA LAST DCLK PULSE (DOES NOT SHIFT DATA) ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH. LEFT HIGH LEFT HIGH ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR CONTINUES TO CLOCK DATA AND ACKNOWLEDGE D in (FROM LCD DRIVER) PULLED LOW BY DRIVER PULLED LOW BY DRIVER STOP D in DCLK START 8-BITS ADDRESS 8-BITS DATA LAST DCLK PULSE (DOES NOT SHIFT DATA) (FROM CONTROLLER) ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR CONTINUES TO CLOCK DATA AND ACKNOWLEDGE ADDRESS ACKNOWLEDGED BY DRIVER LEFT HIGH BY DRIVER (FROM LCD DRIVER) STOP (LOW-ORDER BIT=1) Figure 8 . Data Input MC14LC5004 (IIC Device) BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 D IN BP4 BP3 BP2 BP1 (FROM CONTROLLER) BY CONTROLLER BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 (LOW-ORDER BIT =0) BY CONTROLLER FP1 FP2 D in LEFT HIGH BY DRIVER

3–17 MC14LC5002 • MC14LC5003 • MC14LC5004MOTOROLA PACKAGE DIMENSIONS S M S SM S S NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE B B DETAIL A -A,B,D- BASE METAL F D N SECTION B-B J -H-DATUM K U Q R T W X DETAIL C 1 13 V -A- L -D- L B -D- DETAIL A DETAIL CC H E SEATING G M M -H- DATUM 0.10 (0.004) B V A-B0.05 (0.002) 0.20 (0.008) H A-B D 0.05 (0.002) A-B M S S 0.20 (0.008) C A-B DM S S C0.02 (0.008) A-B D SM -C- MILLIMETERS INCHES DIM MIN MAX MIN MX A 9.90 10.10 0.390 0.398 B 9.90 10.10 0.390 0.398 C 2.10 2.45 0.083 0.096 D 0.22 0.38 0.009 0.015 E 2.00 2.10 0.079 0.083 F 0.22 0.33 0.009 0.013 G 0.65 BSC 0.026 BSC H -- 0.25 -- 0.010 J 0.13 0.23 0.005 0.009 K 0.65 0.95 0.026 0.037 L 7.80 REF 0.307 REF M 5˚ 10˚ 5˚ 10˚ N 0.13 0.17 0.005 0.007 Q0 ˚ 7 ˚ 0 ˚ 7 ˚ R 0.13 0.30 0.005 0.012 S 12.95 13.45 0.510 0.530 T 0.13 -- 0.005 -- U0 ˚ - - 0 ˚ - - V 12.95 13.45 0.510 0.530 W 0.35 0.45 0.014 0.018 X 1.6 REF 0.063 REF QFP FU SUFFIX CASE 848B-02

3–18 MC14LC5002 • MC14LC5003 • MC14LC5004 PACKAGE DIMENSIONS TQFP FB SUFFIX CASE 873A-02 NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS -T -, -U- AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8.MINIMUM SOLDER PLATE THICKNESS SHALL 9.EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 7.000 BSC 0.276 BSC AI 3.500 BSC 0.138 BSC B 7.000 BSC 0.276 BSC BI 3.500 BSC 0.138 BSC C 1.400 1.600 0.055 0.063 D 0.300 0.450 0.012 0.018 E 1.350 1.450 0.053 0.057 F 0.300 0.400 0.012 0.016 G 0.800 BASIC 0.031 BASIC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12˚ REF 12˚ REF N 0.090 0.160 0.004 0.006 P 0.400 BASIC 0.016 BASIC Q1 ˚ 5 ˚ 1 ˚ 5 ˚ R 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC SI 4.500 BSC 0.014 BSC V 9.000 BSC 0.354 BSC VI 4.500 BSC 0.014 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF

3–19 MC14LC5002 • MC14LC5003 • MC14LC5004MOTOROLA For MCC14LC5003 / MCC14LC5004 BARE DIE & MCC14LC5003Z / MCC14LC5004Z A U BUMP DIE : DIE SIZE : 1981.2 x 3022.6 µm2 (78 x 119 mil2, 1 mil ~ 25.4µm) AU BUMP SIZE : 70 x 70 µm2 RESERVED AREA : Dimensions in µm Note : 1. Reserved area contains dummy bumps for IC bumping process alignment and IC identifications. 2. No conductive tracks should be laid underneath reserved area to avoid short circuit. 3. Reserved area applies to Au bump die only. It does not apply to bare die. AREA COORDINATES XY A -445 193 -445 45 -300 45 -300 193 B -74 -910 -74 -1100 368 -1100 368 -910 HONG KONG I.C.DESIGN CENTER© +X-X PIN 1 AREA A AREA B Die Pad No. Pin Name Coordinates XY 1 FP32 -736.002 929.199 2 FP31 -736.002 781.999 3 FP30 -736.002 634.799 4 FP29 -736.002 487.599 5 FP28 -736.002 340.399 6 FP27 -736.002 193.199 7 FP26 -736.002 45.999 8 FP25 -736.002 -101.201 9 FP24 -736.002 -248.401 10 FP23 -736.002 -395.601 11 FP22 -736.002 -542.801 12 FP21 -736.002 -690.001 13 FP20 -736.002 -837.201 14 FP19 -736.002 -1205.601 15 FP18 -588.802 -1205.601 16 FP17 -441.602 -1205.601 17 FP16 -294.402 -1205.601 18 FP15 -147.202 -1205.601 19 V LCD 0.000 -1205.600 20 V SS 147.200 -1205.600 21 FP14 294.398 -1205.601 22 FP13 441.598 -1205.601 23 FP12 588.798 -1205.601 24 FP11 735.998 -1205.601 25 FP10 735.998 -837.201 26 FP9 735.998 -690.001 27 FP8 735.998 -542.801 28 FP7 735.998 -395.601 29 FP6 735.998 -248.401 30 FP5 735.998 -101.201 31 FP4 735.998 45.999 32 FP3 735.998 193.199 33 FP2 735.998 340.399 34 FP1 735.998 487.599 35 NC 736.000 634.800 36 DCLK 736.000 782.000 37 D IN 736.000 929.200 38 ENB 736.000 1205.600 39 A2 588.800 1205.600 40 A1 441.600 1205.600 41 A0 294.400 1205.600 42 BP4 147.198 1205.599 43 BP3 -0.002 1205.599 44 BP2 -147.202 1205.599 45 BP1 -294.402 1205.599 46 V DD -441.600 1205.600 47 OSC2 -588.800 1205.600 48 OSC1 -736.000 1205.600 Die Pad No. Pin Name Coordinates XY Die Pad Coordinates Dimensions in µm BOND PAD LAYOUT