MCA3200ETL

MCA750ETL MOTOROLA | Alldatasheet

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MOTOROLA Order this data sheet by ETD TECHNICAL DATA Aavance Information MCA7SOETL MCAS ETL SERIES MACROCELL ARRAYS MCA3200ETL This specification establishes design and performance requirements for the MCA3 ETL Series Macrocell Arrays with mixed ECL, PECL, and TTL compatible interfaces. Motorola’s MOSAIC Ili™ process provides the MCA3 ETL Series with the logic power of 858 to 6915 equivalent 150 ps (typical) gates on one integrated circuit chip. Any signal pin can be programmed for input, output, or bidirectional signals in ECL, TIL, or PECL (pseudo-ECL) logic families. Advanced process technology, combined with TTL~ECL—PECL innovative high-speed logic design, and an extensive macrocell library COMPATIBLE incorporating a versatile 1/O structure give the arrays the performance and MCA3 ETL SERIES flexibility required to meet today’s high-performance system needs. MACROCELL ARRAYS @ Logic Function Fully Specified by User @ Metal Mask Programmable (Three Unique Masks) @ 2.5 GHz Toggle Rate on Selected D Flip-Flop Macros @ Internal ECL Gate Delays — 0.15ns Typical 2 @ Input ECL Cell Delays - 0.15ns Typical Ree @ Output ECL Cell Delays - 0.3ns Typical se Woe @ TTL Input/Translation Cell Delay — 0.55ns Typical OY © TTL Output/Translation Cell Delay — 2.0ns Typical Soh eS @ ECL 100K, 100E, PECL, and TTL Logic Interfaces Te © ECL, TTL, ETL, and PETL System Combinations MICROCOOL GFP . PGA @ Programmable Speed/Power Levels _ @ Three-Level Series Gated Macros TYPICAL ETL SERIES PACKAGES @ MCA2 and MCA3 ECL Series Library Compatibility FIGURE 1 — MCA3 ETL ARRAY BASIC BLOCK DIAGRAM 100K 100K ECL or PECL ECL or PECL Input Logic Buffers Output Logic Buffers Macrocells M-CELLS TTL Input TTL Output Translators Translators TABLE 1 — MCA3 ETL SERIES ARRAY FEATURES ok | ect Minimum | is | | | Array | Equivalent | Addressable. | # Of Universal | Die Sie | packages | Gates | Units(maus) | OCells mils) oS | MCATSOET | 658 | 96 —+| 42 | 139x168] 6a aFe MCA3200ETL 3570 268 x 268 | 169 PGA/160 OFP woaez00erL| 6915 | 900___| 168 | 952% 362 | 224 PGA/A28 TAB “Contact factory for 328 TAB package information and availability. This document contains information on a new product. Specifications and information herein are subject to change without notice. : MOSAIC II, MOSAIC III, and OACS are trademarks of Motorola Inc. —~__ Apollo is a registered trademark of Hewlett-Packard, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corp. FAST is a trademark of National Semiconductor Inc. | @) MOTOROLA m& ‘© MOTOROLA INC., 1991 < Rev 1 (Replaces ADI1745) Z

• ECL or TTL inputs must enter the chip through and TIL Levels where TTL translation to PECL universal (U) cells. These !/O-cells serve as input on-chip levels is performed. PECL and PETL are buffers as well as performing useful logic func- used for high performance interfacing in systems tions such as a Latch or a 2-input OR/NOR TTL with only TTL power supplies available. to ECL translator. Any signal leaving the array must go through a universal (U) cell. Output Three Layer Metal macros are capable of either logic level transla- The MCA3 ETL Series uses three layers of tion to TTL or implementing a variety of logic metal: two layers for internal macro implementa- functions such as: Latches, MUxXes, and tion and inter-macro routing, and a third layer for EXOR/EXNORs. Bidirectional macros are placed power and ground bussing. Macro interconnec- in one U-cell. Both ECL and TTL Bidirectional tion, power, and ground distribution routing are macros are available. invisible to the user. Vertical (metal-1) channels The chip uses ECL circuitry for the internal are located between the columns of cell sites. array and ECL/TTL for the I/O. Figure 3 shows Horizontal (metal-2) channels may be routed over the four possible implementations for an ETL the macrocell locations. _ The placement of a array. The !/O system allows the array to be macro, therefore, never obstructs metal-2 routing. utilized in full ECL, full TTL, PECL/TTL and All metal layers are separated by a layer of dielec- ECL/TTL (ETL) systems. In ECL environments, tric isolation and are connected using "VIA'‘s”. either 100K @ -5.2V + 5%, or 100K @ -4.5V + Macros such as adders, multiplexers, decod- 0.3V, may be selected. Outputs are capable of ers, latches, flip-flops, XORs, AND-ORs, etc. are driving 60 ohm, 50 ohm, and 25 ohm loads. built using first layer metal within a cell. (Hori- Differential 1/O are available at a cost of two I/O zontal metal-2 routing channels are not required.) cells. TTL push pull and tristate outputs are This eliminates the majority of interconnects that supported, 12mA and 24mA output current sinks normally have to be made in the channels of a can be chosen. gate array and significantly reduces routing chan- PECL is Pseudo-ECL or positive referenced nel requirements. MCA3 ETL arrays contain a ECL. This interface operates between 0 and +5.0V number of free routing channels which is gener- rather than the -5.2V or -4.5V for normal ECL. ally sufficient to provide for auto-routability even Macro performance is identical to operation at in an 100% utilized array. normal ECL levels. PETL stands for Pseudo-ECL FIGURE 3 — MCA3 ETL ARRAY SIGNAL INTERFACES a)ECL b)TTL c)PECL/TTL d)ECL/TTL VCCE (Ground) VCCT. VCE (+5.0V) 9° () | nn: ia | | eEepinenie sheneeseeeenennenn | ECL i TTL i Inputs | ECL M-CELLS ECL Inputs /TTL-PECL M-CELLS PECL-TTL Input Output Logie Ect togic Teg. Translator PECL Translator [T5," pd Outputs Tepe Outputs ° 6 VEEE (~§.2V or ~4.5V) VEET, VEEE (Ground) a) b) VCCT, VOCE (+5.0V) VCCT (+5.0V) 9 9 TL rs cn | TTL poerrnnnnerrnneionererern Translator | Translator TT Translator ba Transiator TTL aaa f opt} Outputs L_promereeprseerenprennnnsocccct | Outputs PECL 1 iar H ECL —| fi Inputs [PECL ] {ly} wecetts PECL Inputs ECL ib weceis Hi ECL Input Output Input i | Output TL T i { Pec H i i T— Outputs ee Outputs a i Sc {e} fe) VEET, VEEE (Ground) VEEE (-8.2V or ~4.5V) ) a MCA3 ETL SERIES - MOTOROLA

The MCAS Series of arrays is implemented using ducing the series base resistance and the process called MOSAIC Ili which achieves collector—base capacitance. An "edge-defined” high performance requirements through delivering technique is used to achieve submicron emitter internal gate delays of 0.15ns (typical) at 0.53mA widths without the use of submicron lithography. switch current. This third-generation process is MOSAIC III allows for polysilicon resistors in or- oxide-isolated in the same manner as was its der to reduce node capacitance. A Schottky mod- predecessor, MOSAIC II. ule is incorporated into the standard MOSAIC III The key improvement over MOSAIC II is the process for fabrication of guarded and use of the poly-electrode-transistor (PET) struc- non-guarded Schottky devices. Figure 4 contains ture which utilizes p+ polysilicon for extrinsic a cross section diagram of a Schottky transistor. base doping and the base electrode and n+ With the Schottky module, high performance TTL polysilicon for the emitter. The polysilicon base inputs and outputs are possible. electrode greatly enhances switching speed by re- FIGURE 4 — CROSS SECTION OF MOSAIC III SCHOTTKY TRANSISTOR Emitter Schottky 1 N+ doped Diode ride Sign, B98 [_poiysiicon Collector py dope [ie paiyelcon MMM EEG CAM aise 8 A th ail i DESIGN FEATURES FIGURE 5 — TTL OUTPUT STAGE Universal I/O Structure The placement of I/O macros within U-cells VOGT (45.0) around the periphery of the array’s internal logic permits the chip’s interface pins to be pro- "4 grammed as inputs, outputs, or bidirectional 1/0. The U-cells also provide the function of ECL, Lk PECL, or TTL logic level translation. Each array Translated L. | TTL Output contains one U-cell for each available I/O signal ECL Input 7 o pad. The number of I/O signal pads for each Signal a array is listed in the table of Array Features on Cx x page 1. U-cells contain a number of devices z including Schottky transistors and diodes; all TTL f 3 | 3 output macros are compatible with FAST™ cir- cuitry. The ECL to TTL output translator gate VEET (Ground) portion of a typical U-cell TTL output macro is schematically represented in Figure 5. The ECL portion of the TTL output macro (not shown) may TABLE 3 — ARRAY OPERATING FREQUENCIES be a tri-stated, 2-Input OR or NOR gate which is driven from the internal portion of the array. wee May ee Operating Frequencies | Sional Type (50% Duty Cycle) | (60% Duty Cycte) The input and output frequencies of the array Se s will depend on the I/O macro selected, the pack- ie a age type, and package pin used. Each package [roureot Pree | | — contains several pins with minimum distance to [Output] —s600,——i«dT=CstCCDS the die which allow for maximum frequency opera- TTL [input | 250 tion. In a design, these pins may be selected for [Output | 100 (@ 15pF) critical signals requiring optimum performance. Notes: The L/H 7xx Series macros in conjunction with 1. Input Frequencies up to 2.6 GHz can be obtained with a differential input and output macros (C70 and sinusoidal AC coupled single-ended input. E70) were specifically designed for high frequency 2. Refer to the MCA3 ETL Design Manual for maximum frequency applications. Maximum operating frequencies for requirements and limitations. the MCAS ETL arrays are shown in Table 3. MOTOROLA . MCA3 ETL SERIES

Primary features of the two Quad Flat Pack black anodized aluminum. For the 224 and 169 (QFP) and two Pin Grid Array (PGA) packages are PGA packages the heat sink is of the pin-fin type summarized below. Both the 64 and 160 QFP (see Figure 14) and for the 64 and 160 QFP packages have been designed for optimum high packages is of the circular fin type with a square frequency operation by incorporating a strip line base (see Figure 15). Figure 11 shows how the characteristic impedance of 50 ohms for the I/O heat sink is mounted directly to the heat slug on interface. Consult the factory for information the package. The chip is also attached directly to concerning the 328 TAB (Tape Automated Bond) the heat slug using a silver filled epoxy com- version for the MCA6200ETL array. Drawings for pound in order to provide a low thermal resis- each package described below are shown in Fig- tance. A ‘thermal compound’ is used between the ures 18 thru 21. heat slug and the heat sink to provide good thermal contact. The aluminum heat sinks were

64 Pin QFP (MCA750ETL): chosen because of their overall thermal perform-

© 42/0 ance, low cost, and lower weight as compared to © 22 power/ground copper versions. « Plastic (non—hermetic) * Cu die attach heat slug FIGURE 11 — Heat Sink Mounted on the Optional heat sink 224/169 PGA Packages e JEDEC registration M0094

160 Pin QFP (MCA3200ETL): Heat Sink

• 120 1/0 Heat | * 40 power/ground Slug © Plastic (non—hermetic) . iy die attach heat slug \\ © Optional heat sink a e JEDEC registration M0108 Sak oe LE

169 Pin Grid Array (MCA3200ETL): | | | | Trcaszoosa0 ETL Die /\\ | | | |

© 0.100" pin spacing © 120 1/0 224/169 PGA Packages © 49 power/ground © Multi-layer ceramic (hermetic) Thermal Test Diode © CuW die attach heat slug An option is available on CAD for placing a Wire-bond interconnect thermal test diode on an ETL array. When using © Ag filled epoxy die attach a test diode, junction temperature and thermal * Optional heat sink characteristics of the package can be measured by the designer.

224 Pin Grid Array (MCAG6200ETL):

• 0.100" pin spacing Forced Convection Impingement * 168 1/0 Forced convection impingement involves forc- © 56 power/ground ing ambient air through an opening directly down © Multi-layer ceramic (hermetic) on the heat sink (see Figure 12). The air flow ¢ CuW die attach heat slug through the pin fins is generally non-laminar. * Wire-Bond Interconnect The thermal resistance from the device to the * Ag filled epoxy die attach ambient air (@ja) depends heavily on the flow rate ¢ Optional heat sink of the impinged air. Thermal Characteristics Using Heat Sinks FIGURE 12 — Forced Convection Impingement jc, junction to case thermal coefficient, is typically between 1.8 to 2.2°C/W for the 224 and ~. rot 4 169 PGA package. Almost all the heat generated a \\ H {} | / en by the device is removed via the CuW heat slug “ee ONE E Ze to which the die is attached. Therefore, a heat ae Ait Flow Velocity, Va NOTE: Opening is sink or cold plate should be attached directly to Tae \\ at Tempe Pyyt fee is 1.85",Sq. ) the CuW heat slug in order to effectively remove Mae if | Ns ed heat from the package and die. ly i} PW 0.28" Given that Qj, = @jo + Oca, the array must “Cant nnn nin nin +; ean i operate in a thermal environment such that @ca 7 ul HUE i (the thermal resistance between the package case en and ambient air) and T, (the ambient temperature) Gpepererep neem eoerepererep are controlled in order to meet the Ty specification ef a st for AC performance of 115°C. The heat sinks currently being offered by Motorola for all ETL packages are composed of EE MOTOROLA MCA3 ETL SERIES 3 -

Thermal Resistance . The total thermal resistance of the packaging Assumptions: configuration depends on many variables includ- 224 PGA with heat sink ing parallel heat flow paths other than from the Ta = 50°C (ambient) die to the heat sink (e.g. heat may flow from the Pp = 11 Watts (die power) board itself to the heat sink.) The thermal resis- air flow = 500 Ifpm tance from the die to the heat sink is composed of thermal resistances for the silicon, epoxy die at- From Figure 16, @JA = 3.1°C/W tach, and the heat sink. The junction temperature of the device is given Thermal Calculations by: The modest power requirements for the ETL arrays combined with good package thermal char- Ty = Ta + Poa = acteristics should minimize any thermal problems. 50 + (11)(3.1) = 84.1°C Junction temperature can be calculated with the This number is well below the 115°C specified equation: maximum junction temperature for the array. Ty = Ta + Po@ya 64 QFP Thermal Considerations Based on similar calculations as for the 224 where PGA, a 64 QFP dissipating 1.5 watts with no heat . sink can be used in ambient temperatures up to T= Junction temperature | 68.5°C before reaching the maximum junction Qya = Thermal coefficient (from Figure 16) temperature of 115°C. While still dissipating 1.5 Pp = Array power dissipation watts but with a heat sink and 200 Ifpm of air Ta = Ambient temperature flow, the 64 QFP can be used in ambient tempera- : : tures up to 91°C. Dissipating 2.0 watts with a For example, prsection ne following list of as: heat sink and 500 Ifpm of air flow, the 64 QFP sumptions, the junction temperature can be calcu- , ° lated as follows: can be used in ambient temperatures up to 94°C. FIGURE 16 — Thermal Resistance 169 and 224 FIGURE 17 — Thermal Resistance 64 and 160 PGAs (Typical) QFPs (Typical) . 30.0} 5 5 PRELIMINARY DATA oa 13.0) o 26.0 —— — Without Heat Sink 2E, Zk \\ — = Z12.0h \\ <E 24.0 With Heat Sink Attached es 25 ool Pat.o|\\ \\ Pe 22.0 NX & & Sa100 Sa ool \\\\ ~ 5u Sw ~ 64.aFP 5 54 N ~ iL 56 80 \\ 5G 16.0 N > w 7.0 169 PGA With Optional w 2 14.0] ~ __ 160 aFP 28 60 \\ Al Pin-Fin Heat Sink 28 y0) 7~ft LL <0 (Thermalloy #23298) Za 77 BW 5.0 » L BY 10.9] 64 QFP 2S 40 ~~ 2S so cw ~ co 2230 — 2 60 160 QFP = = oo 224 PGA With Optional == 40 c ‘Al Pin-Fin Heat Sink & =z 10 (Thermalloy #2329B) z= 20) ° 200 400 600 800 ° 200 400 600 800 HORIZONTAL AIR FLOW~LINEAR FEET/MINUTE HORIZONTAL AIR FLOW-LINEAR FEET/MINUTE MOTOROLA . MCA3 ETL SERIES

APPLICATION DESIGN DEVELOPMENT the customer receives fully tested prototype one first step towards successful design on an devices. MCA3 ETL array is to contact the local Motorola sales office. The sales engineer will describe the WORKSTATION/MAINFRAME INTERFACE array pricing structure and place the customer in Motorola’s Open Architecture CAD System contact with a bipolar product marketing special- (OACS™) supports front end design along with ist. The application is reviewed to assure per- pre- and post-layout timing simulation on Men- formance objectives can be met. Design flow tor Graphics engineering workstations. Physical variables and program schedules will be layout (place and route) and timing analysis de- explained. sign tools are supported on Motorola's mainframe A variety of working relationships can be es- CAD system (WACC). | tablished between the customer and Motorola. In a typical design flow using the MCA3 OACS These arrangements may range from a complete tool set (see Figure 22), the customer executes the Motorola turn-key design effort to the customer first design phase by developing the schematic doing the schematic, along with pre- and post- (using NetEd™) and performing functional and layout timing simulation. Customers can perform Pre-layout simulations (using QuickSim™) on the their own schematic capture and simulation using workstation. Pre-layout simulations use worst- a Mentor Graphics (HP Apollo) engineering work- case macro propagation delays with typical metal station, Motorola provides a workstation based lengths per fanout and include worst-case net design system for pre- and post-layout simula- delays. Motorola then uses the resulting design tion to verify design implementation before releas- files to perform physical layout of the circuit on ing options to manufacturing. WACC. The post-layout timing files, based on Once the optimum design flow has been de- actual wire routing lengths, that originated on termined, a Semicustom Purchase Agreement WACC are back-annotated to the customer to (SPA) between the customer and Motorola can be support QuickSim for final system timing simula- prepared. A SPA specifies the cost to the cus- tions. Design and/or layout iterations are made if tomer for services in design development and necessary. Following a successful post-layout manufacture of prototype devices. The completion design verification and sign off by the customer, of this agreement is normally accomplished when Motorola implements manufacturing the cus- tomer’s specific ASIC design. FIGURE 22 — TYPICAL MCA3 ETL OACS SYSTEM DESIGN FLOW AND TECHNOLOGY FILES! DESIGN ERC UNIT DELAY PRE-LAYOUT PRE-LAYOUT ( CAPTURE L> VERIFICATION >| SIMULATION veay cate / {DELAY siM (NetEd) (OACS) (QuickSim) (OECAL) (QuickSim) — — — -— Supported Mentor Graphics’ Tools TRANSFER ----s TO WACC POST-LAYOUT rt Smotation, | (QuickSim) | LAYOUT DELAY CALC SIMULATION GENERATION Fabrication (wacc} MCA3 OACS 2.0 System Features @ Installation and Verification Utilities @ Produces EDIF 2.0.0 Netlist @ Electrical Rules Checking @ Unit Delay (Functional) Simulation @ Pre- and Post-Layout Simulation NedEd and QuickSim are Trademarks of Mentor Graphics Corp MCA3 ETL SERIES . MOTOROLA

The highest possible level of quality in con- array. An activation energy of 0.70 EV was used crete, measurable terms is Motorola’s goal for its to calculate acceleration factors for other tempera- products and services. Each process and product tures. is extensively characterized and qualified. Relia- bility assurance engineers work closely with 4 FIT = One device failure per 109 device hours macrocell array designers and computer aided de- or sign software engineers to identify and eliminate One part per million failure rate per 103 hours problem causes. Statistical process control tech- niques are used in each step of manufacturing to The reliability estimate is based on modeling of assure first pass design success for all customers. various failure mechanisms where the MCA3 ETL In addition to initial qualification the Reliability arrays features have been compared to other Engineering Department performs ongoing relia- MCA3 arrays as well as previous generation ar- bility testing to maintain a high level of confi- rays. Comparison of actual reliability data to dence in fabrication and assembly operations. previous estimates derived in an identical manner Failure rates as a function of junction temperature have closely predicted actual results. are plotted for the MCA3 ETL arrays in Figure 23. As a result of exceedingly high quality and At a junction temperature of 115°C the failure rate reliability standards, Motorola has achieved one is estimated to be: 250 FIT for the 6200ETL; 145 of the lowest part reject records in the industry. FIT for the 3200ETL; and 50 FIT for the 750ETL FIGURE 23 — FAILURE RATE vs RECIPROCAL TEMPERATURE FOR MCA3 ETL ARRAYS N : 1 \\ 10K FIT SIN ——— 6200ETL —— 3200ETL \\ — — 750ETL O41 q \\ 1000 FIT 0.0145 \\\\ 0.01 \\ 100 FIT 0.005 l

0.001 IN \\ 10 FIT

(%FAIL) 1000 HR . 0.0001 1 FIT 450 350 250 150-118 65 50 25 500 400 300 200 100 Temperature °C (Tu) Estimated static operation average failure-rate as a function of junction temperature (Slope of line based on Arrhenius equation with 0.70 EV activation energy) MOTOROLA . MCA3 ETL SERIES

Each macrocell array M and U Cell location An asterisk (*) indicates an input into the 2nd contains a number of conventional transistors and level of a series—gated tree. A pound sign (#) resistors that can be interconnected with CAD indicates an input into the 3rd level of a series selected metal patterns to form logic functions. gate structure. Internal input followers are used The macrocell library contains pre-defined metal to translate to the proper levels. Numbers in patterns for more than 180 different logic func- parentheses in front of inputs indicate DC loading tions. Designers may select any of the macrocell factors for low and high power macros. functions for any M or U Cell site location. Each macrocell, however, may only be placed in the VO and Translation (U) Cells appropriate cell location type. Internal logic func- Universal cells capable of input, output, and tions are placed in M cell locations. Input, out- translation are placed around the periphery of the put, and translation logic functions for signals chip. All inputs coming onto the chip must be going on and off the chip are performed in U cell connected to an input macro. Even when logic locations. A listing of all MCA3 ETL macros level translation is not required, U-cells are nec- begins on page 19. Selected examples of I/O and essary to ensure full compatibility and adequate internal macros from the macrocell library are noise margins when interfacing with the various illustrated on pages 15 thru 19. ECL logic families. Interface cells can perform Worst-case propagation delay is specified for TTL to ECL/PECL translation combined with sev- a maximum junction temperature of Ty max = eral logic functions. ECL/PECL output macros 2% 7 i are used primarily to provide an output interface can result’ in faster propagation delays. logic outside the package by supplying 25 ohm, ECL/PECL macrocell power dissipation is speci- 50 ohm, and 60 ohm drive capability. Output fied at Vege = —5.2 V. and bidirectional macros also provide the logic The worst-case setup times and minimum Benes ebic lover aniston and latches in ad- pulse widths are specified for all flip-flops and . latches. Hold times are zero unless otherwise specified. SELECTED MACROCELL EXAMPLES ECL/PECL INPUT MACROS - MACRO: C50 INPUT LATCH with ENABLE LOW 0 w) J UCELL POWER: (m\\ MACRO DELAYS (ps) _|L MACRO] H MACRO LM 8.6 ereves Sepues cane fiMacro_ 9.9 [ow Tour eto fate | TRUTH TABLE jel [AYE [400] 400 | 260 | 250 | ei —pata [8 | _vavs To Ye Poet ental | 2 YA | = [28] = [75 | "8 o—4 For [°° a [ve [ses] — [375] — | RST Pax ety | | (2) D Puy x | HW [| SET UP [600 | 450 | ee ee Min CLOCK PULSE WIDTH| 1000 Wore ts crance [Min RESET PULSE WIDTH MACRO: C70 _ DIFFERENTIAL INPUT BUFFER WITH OFF CHIP TERMINATION INPUTS HI DRIVE MACRO

2 U-CELLS

1 LEVEL SERIES GATING POWER: (mW)

LMacro 7.8 JA YA el MACRO DELAYS (ps) | L MACRO [H MACRO ve Cw or tmTol@le | Fl Yc TELFI [YAYB.YC,YD| 75 [100]; _ YD TRUTH TABLE JB NOTES: Pty ty No TNO”) Outputs JA and JB can be used as ee off-chip input termination ports when con- a nected via Macro E75. If outputs JA and DL _ JB are left open, Macro C70 may be used NOTE: ND = NOT DEI as a standard differential input buffer. MCA3 ETL SERIES . MOTOROLA

SELECTED MACROCELL EXAMPLES TTL TO ECL INPUT TRANSLATOR MACRO MACRO: TOO TRANSLATOR with True and Complement [Power (mW) _[L MACRO] H MACRO 1 LEVEL SERIES GATING VCCT (input High) [2.6 | 2.6 | voor (inputtow [1.8 [18] vA WEEE [aa 87] Ye [NT our JHTOT HT © | YaY8 [625] 850] $75 | 700 | Yo Yo.vO | 750] 700600 | 650 Tl=YA=YB= YC-YD ECL/PECL OUTPUT MACROS NOTE: DC loading is shown in parentheses ( ). For example, if (8,12) is shown, that input represents a DC load of 8 for a low power macro and 12 for a high power macro. The number of AC loads is shown in a separate table if it is other than one. Output macro specifications include metal routing, die pad, and package capacitive loading effects. MACRO: E70 DIFFERENTIAL OUTPUT BUFFER

2 U-CELLS POWER: (mW)

1 LEVEL SERIES GATING H Macro 57.2 MACRO DELAYS (ps)| L MACRO | H MACRO, 6A co PIN Tour [MTom] o) bo [ae [ coo P80 225)

6 TRUTH TABLE

— = [aA [ 6B | bdo J co | CO- PO-A-B a NOTES: Inputs A and B should be treated as upper PH itp ti fh level inputs for AC and DC fan-in considerations [HTH [ND [ ND} only. These inputs follow the I/O connection NOTE: ND = NOT DEFINED rules for second level inputs. [AB TT 2 yt ECL TO TTL OUTPUT TRANSLATOR MACROS MACRO: T30 NOR TRANSLATOR

1 UCELL

1 LEVEL SERIES GATING VOCT (Output Lowy] 14.8 | 27.0 | VOCT Output High | 5.8 [8.9 | (2.4) VEEE ) Yo—D>Wa (2,4)B MACRO DELAYS |) wacro [## macro | (ps) [NT our Jmol {To 2875 2275 Load Factor (ps/pF)| 35 [ 44 | 19 [ 39 | WA- Use Load Factor to determine the delay for WA-A+B external loading. a MOTOROLA . MCA3 ETL SERIES

SELECTED MACROCELL EXAMPLES BIDIRECTIONAL 1/0 MACROS MACRO: B26 2-2 OR/AND With Input Buffer (50 ohm output)

1 U-CELL

2 LEVEL SERIES GATING POWER: (mW)

H Macro 20.6 (6)A ee MAGRO OFLAYS | L MACRO | H MACRO *D Pw] oor Tm ToyayTo) vA [ae | ca] | [37s] 300] Mi CO A,B YC,YD 425 | 550 yo cl [AB [ yoo | [ [4251 s50 | Yo peo | ca {| [4s5[ 350] SIMULATION MODEL [co | vave [| [600] 50] yoyo | | [475 [600 | A yaya [| [175 | 200 |

2 ID ; vexo [| | 75}

*D =_ > YA CB = YA= YB = YC = YD = (A+B) » (C+D) YB ye YD — MACRO: T64 ECL 2—INPUT NOR TRANSLATOR and TTL to ECL INPUT BUFFER With ECL Tri-State Enable 1U-CELL

1 LEVEL SERIES GATING TOTAL (WB Low)

TOTAL (WB High) (2,4) TOTAL (WB ZH) [49.6 [70.2 | (2,4) B TOTAL (WB ZL) [46.8 [69.4 | c MAGRO DELAYS (ps) H MACRO vA LW] or | w | aj 0 | a ye WA LAB | we | 2050 [seas | 2575 | 2400 | ye tI 3575 | 4475 [AB | vo | 4375 [| 3650 | 3000 | 3250 Toad Factor pare] #9 | 35 | 99 | 19 _] SIMULATION MODEL [aa are pz eae PY 2650 [4500/3400 [2375 | 2550 | 2900 [2825 | 2300 A Load Factor (ps/pF) | 46 | 66 | 59 | 26 | 43 | 30 | 65 | 30 | B ° c [we [ve {750 [700 [soo [67s | YA Macro delays are for 15pF. Use Load Factor to determine the delay for other loads. YB ve TRUTH TABLE [x |x THT? x yx a a LH Tx yepepe ta Px Ta Toupeyo ya — {xX [x PHP opty MCA3 ETL SERIES MOTOROLA ~ 7

SELECTED MACROCELL EXAMPLES INTERNAL MACROS The M Cells in the array comprise the internal location. Each macro specifies how much of the area on the chip and are used for the majority of cell is needed to implement that particular logic capability. The macros in the Internal function. M-Cell library use 1/4, 1/2, 3/4 or 1 entire cell MACRO: 202 2-Input OR/NOR 1/4 CELL POWER: (mW) 1 LEVEL SERIES GATING L Macro 1.4 H Macro 2.8 YA MACRO DELAYS (ps) |_L MACRO. [i | our |) TOT m1 oO | A YB B yo Ye.yo | 250 | 300 | 200 | 225 | YD YA=YB-YC-YD-A+B MACRO: 403 8-INPUT OR/NOR 1/4 CELL POWER: (mW) 1 LEVEL SERIES GATING L Macro 1.4 H Macro 2.8 MACRO DELAYS (ps)_| L MACRO | H MACRO A [Nour JH POTmMTO) D YB YA=YB=YC-YD=A+B+C+D+E+F+G+H E Yc F YD G H MACRO: 893 3xD LATCH WITH COMMON CLOCK 1/2 CELL L Macro 12.8 A DATA MACRO DELAYS (ps) MACRO var vA Low | oor [wm olelo . EN [Kec | vavevo [eso] 400[ | oe q [0 | vave.vo_[475 [ss [| SETUP TIME [600 [| MIN ENABLE PULSE WIDTH 7000 °° PATA Q i TRUTH TABLE LAT ye px [ow T= | ce DATA ene) ye CEN NOTE: -- = NO CHANGE NOTE: Latches are enabled when input D is low. MOTOROLA MCA3 ETL SERIES 18 -

SELECTED MACROCELL EXAMPLES DIFFERENTIAL INTERNAL (M) CELLS MACRO: 700 __ DIFFERENTIAL LINE RECEIVER HI DRIVE MACRO 1/2 CELL POWER: (mW) 1 LEVEL SERIES GATING L Macro 10.6 MACRO DELAYS (ps) | L MACRO] H MACRO | YA { oN fT our fT mToTe{o} era v8 YAYS[vas[2s| |_| 2B Yo Yoyo [roof so] [| Yo Notes: 1. The default output follower current for each output is 0.96 ma. If the outputs are twinned, the user can select 1.92 ma. 2. The user should note that different Rey, d K val ly f a NUMBER OF AG LOADS 2._ The user shou e ferent Rey, Ref and K values apply for Actual . INPUT | 1st LEVEL |2nd LEVEL TRUTH TABLE [es [1 | | 0.09 pF [A 7-8] YAY8 | YC.vD | ptyTH Tt tH | a [HT WH] ND [ND | NOTE: ND = NOT DEFINED MACRO: 711 FLIP-FLOP WITH GATED DATA INPUT AND DIFFERENTIAL CLOCK 1/2 CELL H Macro 16.0 Ae ° ©YA MACRO DELAYS (ps) H MACRO ; 30 a ee ow our Tm om [oo] eT po [eo | ve.vo |__| 300 [225 | nn a a [vara [T= srs [Te vexo ar | RST MIN CLOCK PULSE WIDTH| _+| 300 _| Ee MIN RESET PULSE WIDTH| | 550 paTaseTUR |_| 200‘ | vatanoto [i100 — NUMBER OF AC LOADS MIN RESET HOLD || 100] INPUT | 1st LEVEL |2nd LEVEL| ,., Actual Capacitance MIN RESET RECOVERY —___|__ 200 [aA_pt|__0.09 pF Notes: a [ B [i [| 0.09 pe 1. The default output follower current for each output is 0.48 ma. If [oc [tt 0.07 pF] the outputs are twinned, the user can select 0.96 ma. [ot 0.07 pF 2. Minimum reset hold time is the minimum amount of time that RESET Ce | 1 | | 0.09 pF must be be held ‘high’ after the CLOCK switches from a ‘low’ to a ‘high’ in order for the flip-flop to remain in the reset state. TRUTH TABLE 3. It should be noted that the Master portion of the flip-flop is asynchronously reset when the RESET line is ‘high’. This reset scheme [pata] ctock | eliminates the possibility of an output glitch for the condition: freser[oatal crock | o_| RESET ='H’, DATA =H’, and the CLOCK transitions from ‘L’—»'H’. pt x ya t= a a j tT A [ton teat A | pH OT x ap tp | [ HO x yt TAT =| LA TW [isk Thott th NOTE: _-- = NO CHANGE MCA3 ETL SERIES . MOTOROLA

MCA3 ETL MACRO LIBRARY LISTING SIZE indicates the macrocell size in universal (U) cells for 1/O macros and in quarter cells for the internal major (M) macrocelis, SG indicates the levels of series gating used in the macrocell function. Note that a ‘3’ in this column denotes a macro which uses three-level series gating and thus cannot be used with a supply voltage of -4.5 Vdc. All three-level series gated functions are indicated by shading. TABLE 6 — ECL/PECL I/O MACROS Macro Function Size SG INPUT INTERFACE (C) MACROS L/HCO1 INPUT BUFFER (Non-inverting) Quad Buffer 1-U CELL 1 L/HC02 INPUT BUFFER (Inverting) Quad Buffer 1-U CELL 1 L/HCO3 INPUT BUFFER (inverting, Non-Inverting) 1-U CELL 1 L/HCOS DUAL DIFFERENTIAL INPUT BUFFER 2-U CELLS 1 L/HC13 DIFFERENTIAL INPUT BUFFER 2-U CELLS 1 LC15 DIFFERENTIAL BYPASS 2-U CELLS 1 L/HC50 INPUT LATCH with ENABLE LOW 1-U CELL 1 LC70 DIFFERENTIAL INPUT BUFFER WITH OFF CHIP TERMINATION 2-U CELLS 1 INPUTS (High Drive) OUTPUT DRIVERS (E) MACROS, 60 & 50 ohm L/HEO1 2-INPUT OR 1-U CELL 1 L/HEO2 2-INPUT NOR 1-U CELL 1 L/HEO3 4-INPUT OR 1-U CELL 1 L/HEO4 4-INPUT NOR 1-U CELL 1 L/HEOS 2 to 1 MUX 4-U_ CELL 2 L/HEO6 2-2 OR/AND 1-U CELL 2 L/HEO7 2-2 OR/EXOR 1-U CELL 2 HEO8 2 to 1 MUX with ENABE LOW (inverting)) 1-U CELL 2 HEOS 2 to 1 MUX with ENABLE LOW (Non-Inverting) 1-U CELL 2 L/HE10 2-2 OR/NAND 1-U_ CELL 2 L/HEN1 2 to 1 MUX with ENABLE LOW 1-U CELL 2 L/HE12 DIFFERENTIAL OUTPUT BUFFER 2-U CELL 1 L/HESO D LATCH with CLOCK ENABLE LOW 41-U CELL 2 HE70 DIFFERENTIAL OUTPUT BUFFER 2-U CELLS 1 HE71 OPEN COLLECTOR DIFFERENTIAL OUTPUT BUFFER 2-U CELLS 1 LE75 OFF-CHIP TERMINATION PAD 1-U CELL 1 CUTOFF OUTPUT (ZE) MACROS, 50 & 25 ohm ZE00 4-INPUT OR (50 ohm) 1-U CELL 1 STECL 1/0 (S) MACROS LSoO 2-INPUT OR 1-U CELL 1 BIDIRECTIONAL 1/0 (B) MACROS, 50 & 25 ohm HB26 2-2 OR/AND with INPUT BUFFER (50 ohm output) 1-U CELL 2 HB27 2-2 OR/NAND with INPUT BUFFER (50 ohm output) 1-U CELL 2 HB28 2 to 1 MUX LOW ENABLE with INPUT BUFFER (50 ohm output) 1-U CELL 2 HB29 4-INPUT OR with INPUT BUFFER (50 ohm output) 1-U CELL 1 HB30 4-INPUT NOR with INPUT BUFFER (50 ohm output) 1-U CELL 1 HBSO 4-INPUT OR with INPUT BUFFER (25 ohm cutoff output) 1-U CELL 2 HBS1 4-INPUT NOR with INPUT BUFFER (25 ohm cutoff output) 1-U CELL 2 HB76 4-INPUT OR with INPUT BUFFER (50 ohm cutoff output) 1-U_ CELL 1 a MOTOROLA . MCA3 ETL SERIES.

• TABLE 7 — TTL & PECL I/O MACROS Macro Function Size SG INPUT TTL TO ECL _(T: 00-29) MACROS L/HTOO TRANSLATOR with True and Complement 1-U CELL 1 OUTPUT ECL TO TTL (T: 30-59) MACROS L/HT30 NOR TRANSLATOR 1-U CELL 1 L/HT31 NOR TRANSLATOR with TTL Tri-State Enable 1-U CELL 1 L/HT33 OR TRANSLATOR 1-U CELL 1 L/HT36 OR TRANSLATOR with ECL Tri-State Enable 1-U CELL 2 L/HT37 NOR TRANSLATOR with ECL Tri-State Enable 41-U_CELL 2 BIDIRECTIONAL I/O (T: 60-89) MACROS L/HT60 ECL 2-INPUT NOR TRANSLATOR and TTL to ECL INPUT BUFFER 1-U CELL 1 with TTL Tri-State Enable L/HT63 ECL 2-INPUT OR TRANSLATOR and TTL to ECL INPUT BUFFER 1-U CELL 1 with ECL Tri-State Enable L/HT64 ECL 2-INPUT NOR TRANSLATOR and TTL to ECL INPUT BUFFER 1-U CELL 1 with ECL Tri-State Enable ECL TO TRI-STATE CONTROL (T: 90) MACRO L/HT90 ECL to Tri-State Control NOR TRANSLATOR 1-U_CELL 1 INPUT TTL TO PECL (P: 00-29) MACROS L/HPO0 TRANSLATOR with True and Complement 1-U_CELL 1 OUTPUT PECL TO TTL (P: 30-59) MACROS L/HP30 NOR TRANSLATOR 1-U CELL 1 L/HP33 OR TRANSLATOR 1-U CELL 1 L/HP36 OR TRANSLATOR with PECL Tri-State Enable 1-U CELL 1 L/HP37 NOR TRANSLATOR with PECL Tri-State Enable 1-U CELL 1 ~ BIDIRECTIONAL 1/0 (P: 60-89) MACROS L/HP63 PECL 2-INPUT OR TRANSLATOR and TTL to PECL INPUT 1-U CELL T BUFFER with PECL Tri-State Enable L/HP64 PECL 2-INPUT NOR TRANSLATOR and TTL to PECL INPUT 1-U CELL 1 BUFFER with PECL Tri-State Enable TABLE 8 — INTERNAL MACROS INTERNAL MACROS (M-Cells) Macro Function Size SG 17H200 “INPUT OR/NOR 74 CELL T L/H201 4-INPUT OR/NOR 1/4 CELL 1 L/H202 2-INPUT OR/NOR 1/4 CELL 1 L/H203 8-INPUT OR/NOR 1/2 CELL 2 L204 12-INPUT OR/NOR 1/2 CELL 1 20 6-INPUT OR/NOR 174 CELL L/H211 2-2 OR/AND 1/4 CELL 2 L/H212 3-2-2-2 OR/AND 1/2 CELL 2 L213 4-3-3-3 OR/AND 1/2 CELL 1 L/H214 2-2-2-2-1-1-1-1 OR/AND FULL CELL 2 A 2-2-3-3-3 OR/AND ULE 2 L/H216 4-2-3-2-3 OR/AND FULL CELL 2 L217 5-4~3-2 OR/AND 1/2 CELL 1 L/H218 5-4-3-2-1 OR/AND FULL CELL 2 L/H219 3-3 OR/AND 1/4 CELL 2 T7227 -2 ORTEXOR 174 CELL 2 : L/H222 DUAL 2-2 OR/AND/EXNOR FULL CELL 2 _ L/H223 4-INPUT EXNOR 1/2 CELL 2 L/H224 4-INPUT EXOR 1/2 CELL 2 L/H225 2-1-1-2 OR/AND/EXOR 1/2 CELL 2 MCA3 ETL SERIES MOTOROLA - 21

TABLE 8 — INTERNAL MACROS [continued] INTERNAL MACROS (M—Cells) Macro Function Size SG H226 2-1-1-2 OR/AND OR L/H227 2-1 EXOR/AND/NAND 1/2 CELL 2 L/H228 2-1 AND/EXOR 1/4 CELL 2 L251 4-TO-1 MUX W/ENABLE (LOW) 1/2 CELL 2 L/H252 QUAD 2-TO-1 MUX FULL CELL 2 T7H25: =TO=1 MUX W/ENAB OW) 4 L/H254 2-TO-1 MUX W/GATED INPUTS 1/4 CELL 2 L/H255 DUAL 2-TO-1 MUX W/COM, SELECT 1/2 CELL 2 L/H256 2-TO-1 MUX 1/4 CELL 2 L258 4-TO-1 MUX W/ENABLE (HIGH) 1/2 CELL 2 L7H259 4=TO-1 MUX 2 L/H261 1-OF-4 DECODER W/ENABLE (LOW) 4/2 CELL 2 L/H262 1-OF-4 DECODER W/ENABLE (HIGH) 1/2 CELL 2 L/H263 1-OF-4 DECODER (HIGH) FULL CELL 2 L/H277 4-2-4-2-4-2 OR/AND 3/4 CELL 2 H276 DATA INPUT DATA LATCH 4 2 L/H279 4-2-4-2-4-2-4-2 OR/AND FULL CELL 2 L/H280 4-2-4-2 OR/AND 172 CELL 2 L/H281 FULL ADDER FULL CELL 2 L/H282 FULL ADDER W/GATED INPUTS 1/2 CELL 2 H28 2-BIT LOOK-AHEAD CARRY U To L/H284 HALF ADDER W/GATED INPUTS 1/4 CELL 2 L/H285 3-BIT ADDER (SUM) 1/2 CELL 2 L/H286 3-BIT ADDER (CARRY) 1/2 CELL 2 L/H290 OD FLIP-FLOP WITH SET AND RESET 41/2 CELL 2 T7H297 D FLIP-FLOP WITH A 172 L/H292 D FLIP-FLOP WITH MUX 3/4 CELL 2 L/H293 D LATCH WITH RESET 1/4 CELL 2 L/H294 D LATCH WITH MUX 1/2 CELL 2 L/H295 GATED 2-WAY D LATCH 1/2 CELL 2 T/H296 XNOR D LATCH 72 CELL L/H297 GATED 4-WAY D LATCH 3/4 CELL 2 L/H298 DUAL D LATCH W/RESET 1/2 CELL 2 L302 INPUT OR/NOR (High Drive) 1/2 CELL 1 /H310 4-4-4-4 OR/AND FULL CELL 1 T/H3tt 3-3-3 AND/OR UI L/H312 3-3-3 AND/OR 1/2 CELL 2 L/H313 2-2 OR/AND 1/4 CELL 2 L/H315 2-2-1-1 OR/AND 1/2 CELL 2 L/H318 3-3 AND/OR 1/2 CELL 1 1379 =3-2-1 AND/OR i L/H320 2-3-4-4 AND/OR W/ENABLE (HIGH) FULL CELL 2 U/H321 6-6-4-4-2-2 OR/AND FULL CELL 2 L322 3-3-3 AND/OR 1/2 CELL 1 L/H323 3-2-2-2-2-3 AND/OR FULL CELL 2 7H324 5-5-5 AND/OR U T 7 L328 2-1 AND/EXOR (High Drive) 1/2 CELL 2 L/H331 3-2-2 AND/OR 1/2 CELL 2 L/H332 GATED OR 1/2 CELL 2 1/H333 GATED OR 1/2 CELL 2 7H370 DIFFERENTIAL LINE RECEIVER 74 CELL U/H371 2-1 MUX WITH DIFFERENTIAL INPUTS 1/4 CELL 2 L/H372 D FLIP-FLOP W/DIFFERENTIAL CLOCK AND DATA 1/2 CELL 2 L/H373 2-1 MUX W/DIFF INPUTS AND DIFF MUX CTL 1/4 CELL 2 L/H374 DIFFERENTIAL LINE RECEIVER 1/4 CELL 1 U/H375 D FLIP-FLOP WITH DIFFERENTIAL CLOCK 172 CELL 2 L/H376 D FLIP-FLOP WITH DIFFERENTIAL CLOCK 1/2 CELL 2 L380 NOR LATCH 1/4 CELL 1 L/H381 D FLIP-FLOP WITH SET 1/2 CELL 2 L/H391 D FLIP-FLOP, NEGATIVE EDGE TRIGGERED 1/2 CELL 2 eee MOTOROLA MCA3 ETL SERIES 22 -

TABLE 8 — INTERNAL MACROS [continued] INTERNAL MACROS (M-—Cells) Macro Function Size SG $3 D FLIP=FLOP WITH MUX, NEGATIVE EDGE TRIGGERED a L/H393, D LATCH WITH CLOCK ENABLE (HIGH) 1/4 CELL 2 L/H394 D FLIP-FLOP WITH MUX, NEGATIVE EDGE TRIGGERED FULL CELL 2 L/H395 D FLIP-FLOP WITH ASYN SET AND DATA ENABLE FULL CELL 2 L/H396 SCAN D FLIP FLOP FULL CELL 2 L/H398 SCAN D LATCH W/ASYN SET 1/2 CELL 2 L/H400 12-INPUT OR 1/4 CELL 2 L/H401 12-INPUT NOR 1/4 CELL 2 L402 2-INPUT OR/NOR, 3-INPUT OR/NOR 1/4 CELL 1 a0 S-INPUT-ORJNOA 7 7 Hae IZeINROT NOR cre L/H413 4-3-3-3 OR/AND 1/2 CELL 2 L414 3-3-3-3 OR/AND 1/2 CELL 2 L/H417 5-4-3-2 OR/AND 1/2 CELL 2 L/H418 5-4-3-2-1 OR/AND 3/4 CELL 2 L/H419 4-4 OR/AND 1/4 CELL 2

421 DUAL EXOR 1/4 CELL 2

tiHagg Oe ...]—=—©—©—6heeFCOtO eee —~r—~—“iaOrsOriarsNrsCa CC SSN r—“iCiOrisOrOisOrsCO*sCSsi réliC RS CiéC Hae GS See OR/AND treet Ease QUAD teem " ane er 7 Ee Kooy Eto MUR W/ENABCESIC ie: L/H455 DUAL 2-10-14 MUX W/ENABLE (HIGH) re eR : _ 456 TRIP -TO-1 MUX(COMMON creases TRIPLE a poumate 1/2 CELL 2 resem MUX W/ENABLE HIGH) Somme mma CELL : t/HaG1 _J-OF-4 DECODER WITH ENABLECOW) te CELL 3 jided _ bsencopee i CC 1/H466. = J-OF 4 DECODER WITH ENABLEHIGH) = CE L470 DUAL 2-TO-1 MUX(COMMON SELECT) 1/4 CELL 2 L474 D RENTIAL LINE R VER (High Drive} 1 2 L482 TRIPLE FULL ADDER . FULL CELL 2 SUHaES EIT ADDER Ss ee EE 3 L/H501 2-INPUT OR (Quad Buffer) 1/4 CELL 1 L/HS502 2-INPUT NOR (Quad Buffer) 1/4 CELL 1 (S03 x2 INPUT OR 1 1 L/H510 4-4-4-4 OR/AND. 1/2 CELL 2 Re Fe 3 UH5I2 SS-SANDIOR Sirs a 3 L/H513 3-1-1-1 OR/AND 1/4 CELL 2 H518 3-3 AND/OR 4CeELt L/H519 3-3-2-1 AND/OR 1/2 CELL 2 PLFHS2O oo 2382424 AND/OR W/ENABLE(HIGH) Cy 3 LisH503 S42-2-2-2-S AND/OR FULLCEtL 8 H553 2-TO-1 MUX W/ENABLE LOW, 1/4 CELL 2 Wott SsOUIPUT SUFFER W/DIFF INPUT & ENABLE (auad Bulle) TF a L585 D FLIP-FLOP W/2to 1 MUX DATA INPUT 1/2 CELL 2 L593 W BUFFER 1/4 CELL 1 PAG te BES BO RPAND Ce ee cs “474 CELL 3 1/HOI6 | 4-2-3-3-2 OR/AND oe V2 CELL 3 a MCA3 ETL SERIES MOTOROLA - 23

TABLE 8 — INTERNAL MAGROS [continued] INTERNAL MACROS (M-Cells) Macro Function Size SG an ie ee ees Mx s—<=RSsisisrsi‘(COsOOCitsCsCSsS=< §§ER ee ll > oe ee ee ORS oe JUL ADDER WIGATEO INPUTS, oe eR en L/H692 D FLIP-FLOP WITH MUX 3/4 CELL 2 604 6 P-FLOP W/RES N ATIVI OLD Mi L700 DIFFERENTIAL LINE RECEIVER (High Drive) 1/2 CELL 2 L701 2-TO-1 MUX W/DIFF INPUTS AND MUX CONTROL (High Drive) 1/2 CELL 2 H710 D FLIP-FLOP WITH DIFFERENTIAL CLOCK AND DATA 1/2 CELL 2 H711 O FLIP-FLOP W/GATED DATA INPUT AND DIFF CLOCK 4/2 CELL 2 PREIR coe D BEIRSEEOR WEXNOR GATED DATA INPUT & DIFF CLOCK FUL CER ae

713 D FLIP-FLOP W/DIFF CLOCK AND DATA (High Drive) SF OLL CELL

L714 — D FLIP-FLOP W/ eareD DATA & DIFF CLK (High Drive) FULL CELL 2 oe eee L804 BUA INPUT AND 4 L805 DUAL 2-INPUT NAND 1/4 CELL 2 L806 DUAL 2-INPUT AND/NAND 1/4 CELL 2 L807 DUAL 2-INPUT AND/NAND 1/4 CELL 2 RHO. Set MUX WITH ENABLE (HIGH) oe BOE CER ee L611 DUAL 4-INPUT OR 1/4 CELL 1 i812 DUAL 4-INPUT OR/NOR 1/4 CELL 1 L813 DUAL 4-INPUT OR/NOR 1/4 CELL 1 L814 DUAL 4-INPUT NOR 1/4 CELL 1

81 DUAL 2-INPUT OR 1/4 LL 1

L816 DUAL 2-INPUT OR/NOR 1/4 CELL 1

817 DUAL 2-INPUT OR/NOR 1/4 CELL 1

Ls18 ___ DUAL 2-INPUT NOR 1/4 CELL 1

820 INPUT OR, 2-INPUT AND 4

L850 EXPANDABLE 2-1 MUX(CODER) AND 2x2-1 MUX 1/2 CELL 2 L854 EXPANDABLE 2-1 MUX 1/2 CELL 2 L852 EXPANDABLE 2-1 MUX 1/2 CELL 2 L853 EXPANDABLE 2-1 MUX 1/2 CELL 2 ee ee ee ECC CL St iyo XPaNDABLESyMuNCoDED = ee F ie oe ANE a ane — r———O—C—CR re EC L881 DUAL D (INVERTING) FLIP-FLOP: 1/2 CELL 2 Lea2 DUAL D FLIP-FLOP 1/2 CELL 2 89 xD LA wr OMMON CLO TT CO 2 L895 D FLIP-FLOP 1/4 CELL 2 L896 ___3xD LATCH WITH COMMON CLOCK AND RESET 4/2 CELL 2 a MOTOROLA MCA3 ETL SERIES 24 ~

TABLE — 9 DC ELECTRICAL CHARACTERISTICS . MCA ETL arrays are available in the following options: 100K, 100E operating at -4.5 Vdc (ECL) with 5.0 Vdc (TTL) 100K, 100E operating at -5.2 Vdc (ECL) with 5.0 Vdc (TTL) PETL Operating at +5.0 Vdc (PECL and TTL) The power supply voltage limits for the following tables are: VCC = VCCO = 0 volts VCCT = 4.75 to 5.25 volts VEEE = -4.2 to -4.8 volts or VEET = 0 volts VEEE = -4.784 to -5.616 volts ECL CHARACTERISTICS 400K COMPATIBLE OPTIONS — ECL OUTPUTS Specification Limits Ty = 25 to 115 °C Characteristic [ “wine | ax Output HIGH Voltage =t025[-955_ | -880_ | mv | Output HIGH Voltage (low power) [=1045 | -975_ | -880 | _mv | Output HIGH Voltage (cutoff | =1050 | 910 =735_ | mv | Output LOW Voltage | =1810_ | -1705 =1620 L Vou? | output Low Voltage (cutoff) =2020 Input HIGH Voltage =1165 [| 850 mv _| Input LOW Voltage =2020 [1475 | mv | 1. Standard (HE and HB macro) 60 ohm outputs terminated with a 50 ohm resistor to -2.0 volts or low power (LE macro) outputs terminated with a 68 ohm resistor to -2.0 volts. ~ 2. Low power outputs with a 60 ohm external load to -2.0 volts. 3. Cutoff outputs are not compensated for temperature. 100K COMPATIBLE OPTIONS — STECL OUTPUTS (6mA AND 10mA CURRENT SOURCE) Specification Limits Ty = 25 to 115 °C Characteristic [Min [typ Max Output HIGH Voltage =1025 Output LOW Voltage | =1e00 [1785 [1620 | mv | Input HIGH Vottage 16s] | 880 | mv Input LOW Voltage [=2020 [= t475_ | mv | 1, STEOL output levels are specified with no external load. 2. This table specifies levels for all STECL outputs. DC CURRENT LIMITS — 100K COMPATIBLE OPTIONS Specification Limits Input Forcing Voltages Ty = 25 to 115 °C TINH Max ViH_ Max Iputidown + (NUlinput) [_ma_| | lpulidown | 0.067 for standard input (75K pulldown) | _'putidown _| where: 12.5 for 10 mA current source input | Ipuidown _| 7.5 for 6 MA current source input Number of DC unit loads connected to input | input [00s ma A MCA3 ETL SERIES . MOTOROLA

TABLE — 9 DC ELECTRICAL CHARACTERISTICS [continued] DC CURRENT AND RESISTOR LIMITS — STECL OUTPUTS AND INPUT CS Characteristic }oMIN | tye max [lout10 CC STECL and inputcs TO oT 25 ma Hout 6 STECL and input os as sma] [Rout 27 STECL Series Resistor | 20 T2742 ohms | [Rout 40 STECL Series Resistor | 30 Tao sos J 4. lout 10 and lout 6 refer to a 10 mA or 6 mA, respectively, internal current source for a STECL output or an input current source 2. Rout 27 and Rout 40 refer to a 27 ohm or 40 ohm, respectively, internal series resistor at the output of a STECL driver. TTL AND PECL CHARACTERISTICS DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE — TTL Symbol [Min | _Typ _| Max | Test Conditions [Von [Output HIGH voltage [27 | 34 | | v | Ton=-3.0mA | Voor=Min | [Wor [output Low vortege | —— | 0.38 | oso[ v | to.-ta/eama | Voor=min | [Vin [Input HIGH Vortage | 20 | -- | -- | v | ireshois over Voor and temp. range | [vit [input Low Vottage | -- | == | 6.80.| v_| tireshold over Vocr and temp. rane [Vix [input Clamp Diode Varage| | [-12[ v | Vecr-Min, N= -18ma_—_| [wt [input HIGH Curent [| = | =| 20 [wa | Veor=Max. Vine2.7V | [int [inp Low Curent | —— [== | ~400[ wa | VoorMax. Vines V | [fozri_| Ouput OM Curent HGH | —- [| —= | 50 [wa] Veor=Max, Vise? V | Tiozt [output OF Current Low [== | == | -80.[ wa | Voor Max. Vine. | [ox [ase [ie | Fle won FE 1. Current per input. 2, Output should not be shorted for more than one second and no more than one output should be shorted at a time. The power supply voltage limits for the following tables are: Veee = O volts Voce = Veco = 4.75 to 5.25 volts Vocr = 4.75 to 5.25 volts Veet = 0 volts PECL OUTPUTS Characteristic [Min typ Max | Vin [input HIGH Voltage Voce - 1165[ [Voce = 850] mv | L_ Vit input Low voitage Voce = 2020) Voce = 1475) mv_| 1. Standard (HE and HB macro) §0 ohm outputs terminated with a 50 ohm resistor to [Voce ~2.0] volts, or low power (LE macro) outputs terminated with a 68 ohm resistor to [Voce -2.0] volts. 2. Low power outputs with a 60 ohm external load to [Voce -2.0] volts. 3. Cutoff outputs are not compensated for temperature. ee MOTOROLA . MCAS ETL SERIES

TABLE 9 — DC ELECTRICAL CHARACTERISTICS [continued] ~ RECOMMENDED OPERATING CONDITIONS [wt Max Glock input Rise/Fall Times (20 10 80%) EGL_| 5 | »s | [rt [ax Clock Input Rise/Fall Times (10 to. 90%) TL | 151 ns _| LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED [Symbot | ____ Characteristic | vawe | Unit] [Tout | ECL/PECL Output Source Current Continuous (25 onmj | 60 (| ma [Tout ECL/PECL Output Source Current Surge (25 onm® | ___ 200 +| ma [Tout | ECL/PECL Output Source Current Continuous (STECL, T0mA~)| 5 | ma _| [Tout EOL/PECL Output Source Curent Surge (STECL, 10ma) | 40+ mA —* [Tout | ECL/PECL Output Souree Current Continuous STECL, 6 ma) | @ | ma ‘| [Tout ECL/PECL Output Source Current Surge (STECL, 6ma) | 44 ma _| [| TTL input Curent Cito S| mA CS 1. If a cutoff output is in the low (disabled) state and is being forced by an external driver, the forcing voltage must fall between Voce and -2.0 volts for ECL and Voce and +3.0V for PECL operation. 2. Surge current is defined as an output current between 30 mA and 100 mA for a 50/60 ohm output, 60 mA and 200 mA for a 25 ohm output, 5mA and 40 mA for a STECL (10mA), and 9 mA and 44 mA for a STECL (6mA). The surge current must last for less than 10s and must have a duty cycle equal to or less than 1%. a MCA3 ETL SERIES . MOTOROLA