MCA10000ECL

MCA10000ECL MOTOROLA | Alldatasheet

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Order this data sheet by MCA10000ECL/D MOTOROLA = SEMICONDUCTOR SEE MCA10000ECL TECHNICAL DATA MCA10000ECL MACROCELL ARRAY The MCA10000ECL Array is a member of Motorola's “Third- MCAS ECL SERIES Generation” MCA3 ECL series. Motorola's MOSAIC III process MACROCELL ARRAY provides the MCA10000ECL with the logic power of over 10,000 equivalent 120 picosecond (typical) gates on one integrated circuit chip. This advanced process technology, combined with inno- vative gate array design, gives the array the performance and flexibility to meet today’s high-performance system needs. LPS © Logic Function Fully Specified by User Z Metal Mask Programmable (Three Unique Masks) ws a © Over 10000 Equivalent Logic Gates mel ° © Internal Gate Delays — 120 ps Typical © Input Cell Delays — 120 ps Typical © Output Cell Delays — 300 ps Typical 360 Lead TAB © Flexible /O Structure with up to 256 Signal Lines © Supported By Complete CAD Development System © Interfaces with MECL 10KH or ECL 100K Logic Families Siete. @ Programmable Speed/Power Levels sas <3 SSa. © Series-Terminated ECL Outputs for Multichip Applications SF Ss © Three-Level Series Gated Macros = Re asters tt @ MCA2 and MCA3 ECL Series Library Compatibility Serenade © High Performance Packages including 289 TAB PGA with > Optional Pin-Fin Heatsink, 235 PGA and 360 Lead TAB Tape

235 PGA (Pin Grid Array) Package

FIGURE 1 — MACROCELL ARRAY LAYOUT TAS i mn a M — Major (Internal) Cells E fitintn Hnotioie & Siciood sited 414 Total Ef , nooq0one_ a = Divisible into 1656 Quarter Cells Ee aM CONHnnoMe EB Hs | — Input Interface Cells BE HHHAAWHE ees 224 Total =n QOOMnneen Ee Ss & & OOHncccne s Ee i [UOUORNOONe & Ee i H HUHAHHHHH ths O — Output Celis (shaded boxes) = & OeGdognnoo a S Ei OOOGOOnO0 ge 200 Total Ee IOOOAORO a os wl NOOR 0Re ey = Dl HOGUOROOe & a } QOONRoo0 ae C — Clock Generators B i OOOO o0 on 2 Total = t HOARD oS = A COMBACGo ee B= WACOM oS . Re AC COOONM t S—— 360 Bonding Pads (TAB Version) BE ronmmn poonema py opopo of Be Minin Boost ff milton ceiceld = Over 1400 Routing Channels FF = uated fata datattatefoetatoatatetatstetat atolls taiat ist atte MECL 10K, MECL 10KH, MOSAIC 1, MOSAIC Ill and OACS are trademarks of Motorola Inc. NetEd and QuickSim are trademarks of Mentor Graphics Corp. | & MOTOROLA HH Rev. 2 MOTOROLA INC. 1991 (Replaces ADI1390R1)

TABLE 1 — BASIC MCA10000ECL ARRAY FEATURES 1. Array contains 1656 internal quarter cells, 200 output driver (O) cells, 224 input interface (I) cells, 256 VO ports. 2. Compatible with MECL 10KH and ECL 100K input/output logic levels. 3. Up to 12,402 equivalent gates if full adders, output latches, and input OR’s are used. 4, Up to 11,160 equivalent gates if D flip-flops, output latches, and input OR’s are used. 5. Die size: 385 x 385 mils. 6. Speed/power programmable from 8-15 Watts Low Power Array (LPA) and 12-30 Watts High Power Array (HPA). 8. Current source pulldowns on internal macrocell outputs to VeE2 (—3.4 Vde nominal) 9. Input cell delays: 150 ps (HPA), 300 ps (LPA) worst case. 10. Internal cell delays: 175 ps (HPA), 300 ps (LPA) worst case (2-input OR, FO = 1, metal = 0). 11, Output cell delays: approx. 600 ps worst case (includes 250 ps package pin delay). 12, Standard 50 and 25 ohm ECL output drivers. Optional low-power 68 chm drivers. 13. Series-terminated (STECL) outputs with on-chip series resistors and programmable current sinks. 14, Expandable MUX/DECODE macro functions. 15. High-performance 289 PGA package with controlled impedance. 16. Two on-chip clock pulse generators/buffers. 17. Three-level series gated macros available for increased functional density and performance. PRODUCT DESCRIPTION binational logic to all forms of latches and flip-flops. An Motorola’s “Third Generation” — MCA3 ECL series internal quarter cell can contain functions as large as a is a two part family which includes the MCA10000ECL D flip-flop (the L892 is a dual D flip-flop in a half cell). and the MCA2200ECL. This data sheet features the Logic may also be implemented in the input and output MCA10000ECL array. The MCA10000ECL Macrocell cells. (See Figure 3.) Array contains the equivalent of over 10000 gates, each The output cells contain functions such as a 4-input with a typical delay of 120 ps with one load and no OR/NOR (LX02) or a D latch (LX92). The array supports metal. The array is fabricated using Motorola’s MOSAIC standard ECL 50 and 68 ohm outputs, 25 ohm cutoff Ill process which features poly-electrode-transistors drivers, and 50 ohm cutoff drivers. The designer, how- (see Figure 2). ever, may use an external load of 60 ohms with a slight The array is fully compatible with the two prevailing loss in VoH noise margin. In addition, the designer may industry ECL standards: MECL 10KH and ECL 100K. The select series-terminated (STECL) outputs or inputs with ECL 100K compatible version features temperature current-source pulldowns for multichip applications. compensation over a junction temperature range of 25 Input (I) macrocells are used for interfacing with exter- to 115 degrees Centigrade. Both 10KH and 100K ver- nal ECL 100K levels (optional for 10KH) or for buffering sions of the MCA10000ECL are specified for use with a signals driving lower-level inputs on the array. Veet of either — 4.5 Vdc or —5.2 Vde (nominal). The MCA10000ECL array uses three layers of metal The array contains four types of cells in which macro- for routing: two layers for internal macro implemen- cell functions can be placed: internal (M) cells, input (I) tation and inter-macro routing, and a third layer for cells, output (O) cells, and clock (C) cells. The MCA3 ECL power and ground bussing. Both macro interconnection Series Design Manual includes an extensive, common routing and power and ground distribution are invisible Macrocell Library for the MCA10000ECL and to the user. Vertical (metal-1) channels are located MCA2200ECL arrays. The Macrocell Library listing illus- between the columns of cell sites. Horizontal (metal-2) trates all the logic functions (macros) which can be channels may be routed over the macrocell locations. implemented in these cells and provides critical design The placement of a macro will not obstruct metal-2 rout- information such as propagation delays and power ing. The three metal layers are separated by a layer of requirements for each macro. The MCA3 library sup- dielectric isolation and are connected using “VIA's.” ports all of the macro functions from Motorola’s Macros such as adders, multiplexers, decoders, MCA2500ECL library as well as numerous additional latches, flip-flops, XORs, AND-ORs, etc. are built using functions optimized around the MCA3 cell architecture. first layer metal within a cell. (Horizontal metal-2 routing With few exceptions, all marcos in the MCA3 library can channels are not required.) This eliminates the majority be implemented in either the MCA10000ECL or of interconnects that normally have to be made in the MCA2200ECL array configuration. However, the channels of a gate array and significantly reduces rout- MCA2200ECL array is offered only in the high power ing channel requirements. The MCA10000ECL contains version. a number of free routing channels which is generally The MCA10000ECL contains 414 M-cells, 224 |-cells, sufficient to provide for auto-routability even in a fully 200 O-cells, and 2 C-cells as shown in Figure 1. The utilized array. MCA10000ECL is available in either a high or low power The chip uses ECL circuitry for the internal array and version and macrocells on both versions are speed/ for the I/O. Single-level, two-level, and three-level power programmable. series-gated ECL structures are used to implement logic The majority of the designer's circuit is implemented functions. Series-gating allows complex macro func- using the internal (M) cells. The internal cells contain a tions to be implemented with fewer transistors while wide variety of SSI/MSI functions ranging from com- maintaining maximum performance. a MOTOROLA MCA10000ECL

FIGURE 2 — CROSS SECTION OF MOSAIC Ill PROCESS. Emitter Base i Collector » Nitride Si, Ny P+ doped N+ doped doped oN | Ps doped, [wie Ns doped ; SEVERE Nitise Sig Ny 6 5 aA SS

9 Vere TM Ns]

MOSAIC III (Motorola Oxide-isolated Self Aligned Implanted Circuit) — Patents Pending FIGURE 3 — INTERNAL CELL ARCHITECTURE (1/4 MAJOR (M) CELL) TWO 2nd-LEVEL INPUT Yee Vee Yee Wann Veer KKK KK][ ee eae is hy $ “ww Yee! { ; i 4 x x vounourrure Two swiTen ONE sraever 1] NOTES UR OUTPUT CURRENT- 1. QUARTER CELL IS THE 2, ALTHOUGH A 14 CELL ONLY HAS TWO SWITCH CURRENT t 4 rPreye 3 : SOURCE RESISTORS. A 12 Kt CELL HAS FIVE BECAUSE OF BO Ty 3 RESISTOR PLACEMENT. Veer PROCESS DESCRIPTION MCA3 ECL Series Performance The MCA10000ECL is implemented using a new pro- The MCA10000ECL array is the result of a successful cess called MOSAIC Ill which achieves the high perfor- match between state-of-the-art bipolar processing mance requirements of 0.12 ns (typical) for internal gate technology (MOSAIC III) and innovative circuit design delays. This third-generation process is oxide-isolated techniques. Several key features of Motorola’s MCA2 in the same manner as was its predecessor, MOSAIC il. macrocell arrays as well as many new features The key improvement over MOSAIC II is the use of designed to take advantage of the MOSAIC III process the poly electrode transistor (PET) structure which uti- are implemented on the array. Speed/power pro- lizes p+ polysilicon for extrinsic base doping and the grammability allows the designer to choose the exact base electrode and n+ polysilicon for the emitter. The performance level to fit his or her design needs. In the polysilicon base electrode greatly enhances switching low speed/power version, the MCA10000ECL displays speed by reducing the series base resistance and improved delay performance to that of the Motorola collector-base capacitance. An “edge-defined” tech- MCAZ2500ECL, but with four times the gate count and nique is used to achieve submicron emitter widths with- only slightly more power dissipation. The high-power out the use of submicron lithography. MOSAIC III allows version of the array yields performance levels which for polysilicon resistors in order to reduce node capac- are over twice those of the MCA2500ECL. itance. The process also provides for the deposition of The MCA10000ECL uses input (1) cells as input signal gold bumps as an interface for tape-automated bonding buffers to insure adequate voltage levels and noise mar- (TAB). Three levels of metallization are used, two for gins for interfacing with external ECL 100K logic levels. interconnection wiring and the third for power bus \\-cells are also used to buffer external signals which distribution, drive lower level macrocell inputs. |-cells are optional for 10KH interface and 100K differential inputs. MCA10000ECL MOTOROLA

289 Pin Grid Array heat slug and the heat sink to provide good thermal

@ 0.100" pin spacing contact. The aluminum pin-fin heat sink was chosen @ 256 1/0 because of its overall thermal performance, low cost, © 32 power/ground (1 loc. pin) and lower weight compared to a copper version. © multi-layer epoxy-bonded fiberglass (non-hermetic} @ CuW die attach heat slug © TAB bond interconnect FIGURE 7 — HEAT SINK MOUNTED ON THE 289 PGA © .008” outer lead bond pitch Heat Sink © ,004” pad pitch © Ag filled epoxy die attach Heat | © optional Motorola pin-fin heat sink Slug

235 Pin Grid Array \\ tee a |

0.100" pin spacing ene) eee 2c NU na © 55 power/ground MCA10000ECL Die / @ multi-layer ceramic (hermetic) 289 PGA Package @ CuW die attach heat slug ® wire-bond interconnect © Agffilled epoxy die attach Forced Convection Impingement © optional Thermalloy pin-fin heat sink (Part No. Forced convection impingement involves forcing 23298) ambient air through an opening directly down on the heat sink (see Figure 8). The air flow through the pin TAB (Tape Automated Bond) Tape fins is generally non-laminar. The thermal resistance @ Tape is in S35mm format from the device to the ambient air (6a) depends heavily @ Die on tape is supplied in a carrier on the fiow rate of the impinged air. @ Tape has two metal layers (signal layer and ground plane) © 360 leads, .004” inner lead bond pitch, .008" outer FIGURE 8 — FORCED CONVECTION IMPINGEMENT lead bond pitch © Tape metallurgy: Sn over .001” Cu conductor on ra i | o ue The tape-automated bonding (TAB) process used in Stee, NALEEB EF Me the 289-pin grid array package involves the use of spe- ss... 7s Air Flow Velocity, VA “NOTE: Opening is cial solder bumps on the die which are mass-bonded Soe a Tenens: TA 1.85” Sa. to a flexible tape consisting of thin copper leads ZZELEZLEZZZZZ 33 1" } if EA AC ececcezccncs attached to a polyimide dielectric substrate. Customers OEE BEATA oS 0:25" who opt to do their own packaging may choose to wee HN ai receive the MCA10000ECL bonded to the TAB tape. “r - Parts in tape are supplied in a specially designed carrier. Heat Sinks and Cooling Considerations The thermal requirements for an MCA3 design will vary according to array size, choice of power version, percent utilization of the array, desired reliability levels, and the mixture of high and low power macrocells FIGURE 9 — FORCED CONVECTION HORIZONTAL within the array. In the low-power version of the array Air Flow Velocity, V (8-15 Watts typical dissipation for a fully utilized array), wn Temperature TA = TA a heat sink and air flow will be required to meet the nenennnneeeeecenenecnneeeeeee maximum junction temperature limit of 115°C for ac = Saga et arene a specifications. The highest performance version (12-30 poem H Sipe eanenneee Watts typical dissipation for a fully utilized array) may = E BERS require techniques such as impinged air with a heat sink ee or the use of liquid cooling in order to meet the maxi- A mum junetion temperature limit. Th Using the Heat Sink With the 289 PGA The heat sink currently being offered by Motorola for the 289 PGA is a black anodized 6061 aluminum pin-fin Thermal Resistance heat sink containing 4 screw holes for direct mounting The total thermal resistance of the package/heat sink to the heat slug on the package. The chip is attached configuration depends on many variables including par- directly to the heat slug using a silver filled epoxy com- allel heat flow paths other than from the die to the heat pound in order to provide a low thermal resistance (see sink (e.g. heat may flow from the board itself to the heat Figure 7). A ‘thermal compound’ is used between the sink). The thermal resistance from the die to the heat a : MOTOROLA MCA10000ECL

FIGURE 10 — THERMAL RESISTANCE (TYP) JUNCTION-TO-AMBIENT PGA PACKAGE WITH HEAT SINK 5.0 10 | AT Tessie AT TPT Py TT eI AEE 53 . 70 A eo LIN TT PETE) JAP TT TT TTT PLL IAL TE EE TT ee AN TT = [I Ls 25 < 5.0 iS POOP RSET BICN Northen 20 — 40 Ws with Thermalioy Heat Sink IN eti titi itt) oft MAA TTT 0 1.0 20 3.0 40 50 ° ~ LT (CUBIC FEET PER MINUTE) 2.9L. 289 PGA with Motorola Fin-Fin ++ Heat Sink FIGURE 10a — IMPINGED AIR FLOW (289 PGA) 10 I | tp 0 200 400 600 800 1000 sink is composed of thermal resistances for the silicon, (LINEAR FEET PER MINUTE) epoxy die attach to the heat slug, and the heat sink to ambient air. FIGURE 10b — HORIZONTAL AIR FLOW (235 & 289 PGA) JA = OCA + OC Example Calculation of Junction Temperature: Assumptions: DESIGN DEVELOPMENT INTERFACE SYSTEM

289 PGA with heat sink The first step towards successful design on an MCA3

Horizontal air flow ECL Array is to contact the local Motorola sales office. Ta = 25°C (ambient) The sales engineer will describe the array pricing struc- Pp = 25 Watts (die power) ture and place the customer in contact with one of air flow = 600 Ifpm Motorola’s Design Centers (see location listings on page , _ 26). The application is reviewed to assure performance From Figure 10b @yaq = 2.2 objectives and program schedules can be met. Design ; . jan ie ah flow variables will be explained. The junction temperature of the device is given by Once the optimum design flow has been determined, Ty = Ta + Pp Ja = 25 + (25)(2.2) = 80°C a Semicustom Purchase Agreement (SPA) between the customer and Motorola can be prepared. A SPA spec- ifies the cost to the customer for services in design Forced Convection Horizontal (“Conventional Flow”) development and manufacture of prototype devices. Horizontal air flow, or forced convection horizontal is The completion of this agreement is normally accom- a conventional air flow configuration used in many TTL plished when the customer receives ten prototype and lower power ECL environments (see Figure 9). devices. Ambient air is blown horizontally (parallel to the plane of the package) over the package and heat sink. Workstation Interface Motorola's Open Architecture CAD System (OACS™) Thermal Characteristics supports front end design on Apollo/Mentor engineer- 6J¢ is typically 0.6 to 0.8°C/W for the 289 PGA package ing workstations. Timing and layout design tools are and 0.8 to 1.1°C/W for the 235 PGA package. Almost all supported on Motorola's mainframe CAD system the heat generated by the device is removed via the (WACC). CuW heat slug to which the die is attached. Therefore, In a typical design flow using the MCA3 OACS tool a heat sink or cold plate should be attached directly to set (see Figure 11), the customer executes the first the CuW heat slug in order to effectively remove heat design phase by developing the schematic and per- from the package and die. Given that 0ja = @Jc + OCA, forming functional simulations on the workstation. the array must operate in a thermal environment such Motorola then uses the resulting design files to layout that 8c, (the thermal resistance between the package the circuit and complete the design. Post layout simu- case and ambient air) and T, (the ambient temperature) lations are performed and evaluated to design require- are controlled in order to meet the Ty specification for ments. Design and/or layout iterations are made if AC performance of 115°C. necessary. MCA10000ECL MOTOROLA

FIGURE 11 — TYPICAL MCA3ECL OACS SYSTEM DESIGN FLOW TECHNOLOGY FILES DESIGN. ~ ERC UNIT DELAY ~ Thank DELAY EST'D DELAY ( carruRe J->{ verieication J siMuLATION J TO WACC CALCULATION SIMULATION ANALYSIS: LAYOUT CALCULATION SIMULATION GENERATION RELEASE — — — Supported Mentor Graphics’ Tools (NetEd™ and Quicksim™) MCA3 OACS System Features: © Installation and Verification Utilities @ Produces Standard EDIF 2.0.0 Netlist © Electrical Rules Checking @ Functional Simulation © Netlist Translation to WACC PRODUCT RELIABILITY FIGURE 12 — FAILURE RATE versus JUNCTION TEMPERATURE The highest possible level of quality in concrete, measurable terms is Motorola’s goal for its products ‘000° and services. Each process and product is extensively 12 14 -16 18 20 22 24 26 28 30 32 34 36 characterized and qualified. Reliability assurance engi- 10 neers work closely with macrocell array designers and computer aided design software engineers to identify and eliminate problem causes. Statistical process con- 1 soceir trol techniques are used in each step of manufacturing to assure first pass design success for all customers. \\ In addition to initial qualification the Reliability Engi- neering Department performs ongoing reliability test- o. \\ 4000 FIT ing to maintain a high level of confidence in fabrication and assembly operations. Failure rate as a function of \\| junction temperature is plotted for the MCA10000ECL array in Figure 12. At a junction temperature of 115°C 001 \\ 0.0098 100 FIT the failure rate is calculated to be 98 FIT (0.0297%/1000 (% FAIL) Q isc hrs.) with a 90% confidence level. An activation energy 7000 HR of 0.70 EV was used to calculate acceleration factors for ! other temperatures. noo | 27 CONFIDENCE torr

1 FIT = One device failure per 109 device hours A TTLELEN TA

One part per million failure rate per 103 hours «00! AT This data has been derived from over 1,157,000 device 450 350 250 150 65 50 6 0 hours without a single failure. 500 400 300 200 100 As a result of exceedingly high quality and reliability TEMPERATURE °C (TJ) standards, Motorola has achieved one of the lowest part reject records in the industry. MCA10000ECL MOSAIC Ili MACROCELL ARRAY Static operation failure-rate as a function of junction temperature (Slope of line based on Arrhenius equation with 0.70 EV activation energy) a MOTOROLA MCA10000ECL

Each macrocell M, O, and | Cell location contains a Worst-case propagation delay is specified for VeE1 number of conventional transistors and resistors that = -45V + 0.3 Vor VEE, = —5.2V + 8%, VEE? = can be interconnected with CAD selected metal patterns —3.4V + 8%, and a maximum junction temperature of to form logic functions. The macrocell library contains Ty max = 115°C. in general, a lower junction temper- pre-defined meta! patterns for more than 180 different ature can result in faster propagation delays. Macrocell logic functions. Designers may select any of the macro- power dissipation is specified at Veg, = —5.2 V. For cell functions for any M, O, and | Cell location. Each VeE1 = —4.5V, the typical power is calculated by mul- macrocell, however, may only be placed.in the appro- tiplying Pp by the factor 0.87. The specified power dis- priate cell location type. An M-cell, may only be placed sipation values do not include the output emitter fol- in an M cell location, an X-cell may only be placed in lower power which is 2.72 mW/output in the high-power an O cell location, and a I-cell may only be placed in a array or 1.63 mW/output in the low-power array (VEE? |-cell location. = -3.4V). A list of macrocells is shown in Table 2. The worst-case setup times are also listed for all flip- flops and latches. Hold times are zero unless otherwise Internal (M) Cells specified. The M Cells in the array comprise the internal area The worst-case minimum pulse width is specified for on the chip and are used for the majority of logic capa- the clock inputs of flip-flops and latches to insure proper bility. Each M Cell contains 76 resistors and 76 transis- operation. tors. The macros in the M-Cell library can use 1/4, 1/2, An asterisk (*) indicates an input into the 2nd level of 3/4 or 1 entire Internai cell location. Each macro specifies @ series-gated tree. A pound sign (#) indicates an input how much of the cell is needed to implement that par- into the 3rd level of a series gate structure. Internal input ticular function. followers are used to translate to the proper levels. MACRO: 201 — 4-Input OR/NOR 1/4 Cell

1 Level Series Gating POWER: (mW)

Low Power Array | High Power Array | B YB YA=YB=YC=YD=A+B+C+D Cc yc D YD vacno oeLA pn Wah Power roy PO [imecro TH macro [i Macro | H Macro | Loom [out Jin fin fin Tf fio [| |__aecio | vaya | 280 | 278 | 200 | 200 | 200 | 200 | 175 | 175 | asco | veo | 400 | 400 | 300 | 300 | 300 | 300 | 250 | 250 | MACRO: 403 — 8-Input OR/NOR 1/4 Cell : Low Power Array | High Power Array A L Macro 14 24 B c YA YA=YB=YC=YD=A+B+C+D+E+F+G+H D YB MACRO DELAYS (ps) F Yo Pe [taco TH Macre | Macro | HMacro_| 6 jw [out [iw fia fie Tot Poa H AB.CD.EFGH | YAYB | 225 | 260 | 175 | 200 | 175 | 175 | 150 | 150 | AB.CD.EFGH | vc¥D | 800 | 725 | 475 | oo | 475 | 400 | 300 MCA10000ECL MOTOROLA

MACRO: 376 — D Flip-Flop with Differential Clock 1/2 Cell

2 Level Series Gating POWER: (mW)

*c YE +p Dye sal, air ower fis Pete fete fee [xe va a0 [900 20 | 280 200" | 200 15 | 200 | rua TaBLe [cae | v0 20 | ae0 [175 | a00 | 150 | 75 | 160 18 [Pep vo | 276 [ao | 250 | 00 | 250 | 276 | 20 | 280 De |r [aelc [ow] ve|| co | ve | 50 | soo 25 | ars | aso | a5 | 25 | 20 | ee pe Dee Pf — | eos [oo | 250 | 00-| 250 | 276 | 200 [250 | ce a er eee ee a eee etc peta pe pe fe [oe foo | — [oo] — [ooo] — [eco] — | Dee pepo fe pe oo] — ooo] — Pare | — Paee | Doce fore ep ow foe] [ eo — eo] — Pe [ — [wo — | hepa texte) } 1-4 ab oats] [nc] [mn cxoce emo | aso] wo] ao) ooo | [Tin cux ese wor | ers | aso | aso | 300 [aoe Tew fne] | ac] [nest ese wiot [ors [wo | wo | om] Pcp pa fiona] a] | camnnesr recay tie | ers | aso | aso [200 NOTE: — = NO CHANGE MACRO: 893 — 3xD Latch with Common Clock 1/2 Cell [tow Power Aray_| High Power Avay | A oa Qa YA [EMeere | Mme | EMeero | Hace | ee Case | vavave [sso [ao] | [aol] |_| [> | vavere [ws [sos | tars fare} | | | fe [han ewaous ese wor] —seoo [| 70 [J GFN ‘TRUTH TABLE [om [ex [a _] Tae | _|varvene| JOTE: QUEN [we [el # | hunches are enabled when input D is low. NOTE: — = NO CHANGE a MOTOROLA MCA10000ECL

The input interface cells are interspersed among the are necessary to insure full compatibility and adequate Output cells around the periphery of the chip. All 100K noise margins when interfacing with the various ECL inputs coming onto the chip must be connected to an logic families. Interface Cells can perform simple logic Interface Cell. 10KH inputs may go directly to the upper functions such as a 2-input NOR or a differential buffer. level of an M-cell. The output of | cells is then routed to the internal portion of the macrocell array. These cells NOTE: Power values listed are for Veg? = —3.4 Vdc. MACRO: 100 — 2 Input OR/NOR 11-Cell ve [waco s8 + A YB B yc YD ps Ya=YB=YC-YD-A+8 |_tMecro | HMacro | LMacro | HMacro_| pow four fi fi fw Tir fe [i oT | vaye | 226 | 260 | 175 | 200 | 175 | 175 | 150 | 150 | Las | yevo [22s | 275 | 15 | 200 | 178 | 200 | 180 | 175 | MACRO: 103 — Differential Buffer 11-Cell Low Power Array | High Power Array tmaco | og | ts vA [HMacro[ 18 | ne A YB B Yc YD Pe [tmecro [Macro [Macro | HMacre | YA=YB=YC=YD-A-B pow | our fem fo fin io fia fe Las [vaya | 195 | 225 | 175 | 200 | 160 | 150 | 150 | 150 | TRUTH TABLE [a | 8 | YAyB| Yc.vD jee | no | no | [utet a fe | NOTE: ND = NOT DEFINED MCA10000ECL MOTOROLA

Output Driver (X) Macrocells The Output Cells are located around the periphery of The Output cell provides macros with a similar logic the array. Macrocells implemented using O-Cells have capability to 1/4 of a Major Cell. either an ‘HX,’ ‘LX,’ or ‘2X’ (cutoff driver) prefix followed by the macro number (e.g. HX71). X macrocells can use NOTE: DC loading is shown in parentheses (). For exam- 1 or 2 of these Output Cells as indicated in the library. ple, if (8,12/4,6) is shown, that input represents a DC The X Cells are used primarily to provide an output load of 8 for a low power macro in the low power array, interface between the internal logic in the array and the 12 for a high power macro in the low power array, 4 for logic outside the package by supplying 25 ohm, 50 ohm, a low power macro in the high power array, and 6 for and 68 ohm drive capability. These macros also provide a high power macro in the high power array. The num- extra logic capability with logic functions such as OR- ber of AC loads is shown in a separate table if it is other AND, Exclusive OR with enable, flip-flops and latches. than one. MACRO: X01 — 2 Input OR/NOR

1 O-Cell

| Low Power Array | High Power Array LMacro | za | aaa (8,12/4,6) A ZA XA=2A=XB=ZB=A+B (8,12/4,6) B xB Pe rr High Power Array

28 MACRO DELAYS (ps) 1

PH [tMecro TH Macro | tMacro | H Macro | Pow our fo Pro fe Fo fm a [ro [a] | as [xa | 00 | 300 | 360 | 275 | 47 | 300 | 360 | 200 | | as | xe _| 52s | 360 | 375 | 275 | 500 | 300 | 360 | 250 | [aa | za_| 2s | 42s | 308 | 360 | 400 | 400 | 328 | 325 | [as [28 | 42s | 480 | 360 | 360 | 400 | 42s | 325 | 360 | MACRO: X53 — 2-to-1 MUX with Enable (Low) 10-Cell

2 Level Series Gating POWER: (mW) TRUTH TABLE

High Power Array |_| | |xazal MUX [Meco [ 194 [mo] [ee a (8,12/4,6) B qi XA [ela] es | fe q ZA (12148) A Set EN MACRO DELAYS (ps) Low Power Array High Power Array y |_Lacro | HMacro | LMacro | H Macro | ° Pw | our fiw Ti fon Trot fe [i [| (9.1857)" D |__as | xa | 60 | 400 | 400 | 300 | 560 | 375 | 400 | 300 | [| __ Number of a Loads a [input | tst Level | and evel ['ardtevet | [> | xa _| 675 | 475 | 600 | 375 | 680 | 475 | 475 | 375 | Po} + for LT F600 [600 [ars | a0 | 525 | 600 | 460 | 40 | MACRO: ZX05 — 5 Input OR (50 Ohm Cutoff Driver) 10-Cell POWER: (mW)

1 Level Series Gating Low Power Array | High Power Array

(126) A tmecro [9 | tat (12/6) B MACRO DELAYS (ps) 28) 0 =) [mero | WMacr | UMacro | Haro | (1216) a a ese es XA=A+B+C4D+E agcoe | xa | ss0[ sso] | [sso|ssol [| MOTOROLA MCA10000ECL

MACRO: 2X85 — 8-Input OR GATE (25 Ohm Cutoff Driver)* 2 0-Cell *D MACRO DELAYS (ps) Low Power Array High Power Array “F Pow | our [en Pro fee Tro fe Tra [i [| “H enn | xa | el asf [Tf TT | XA=A+B+C+D+E+F+G+H NOTE: * Indicates macro is available on MCA10000ECL Low Power Array only. TABLE 2 — MACRO LISTING SIZE indicates the macrocell size in quarter cells for the Internal (M) macrocells and in full | or O cells for the Input Interface or Output macrocells, respectively. SG indicates the levels of series gating used in the macrocell function. Note that a ‘3’ in this column denotes a macro which uses three-level series gating and thus cannot be used with a supply voltage of — 4.5 Vdc. All three-level series gated functions are indicated by shading. INTERNAL (M) MACROCELLS U/H200 5-INPUT OR/NOR 1/4 CELL 1 WH201 4-INPUT OR/NOR 1/4 CELL 1 UH202 2-INPUT OR/NOR 1/4 CELL 1 ~ U/H203 8-INPUT OR/NOR 1/2 CELL 2 L204 12-INPUT OR/NOR 1/2 CELL 1 UH207 6-INPUT OR/NOR - 4 CELL 2 UH211 2-2 OR/AND V4 CELL 2 UH212 3-2-2-2 OR/AND | 1/2 CELL 2 L213 4-3-3-3 OR/AND 1/2 CELL 1 UH214 2-2-2-2-1-1-1-1 OR/AND FULL CELL 2 UH215. 2-2-3-3-3 OR/AND. FULL CELL 2 VH216 4-2-3-2-3 OR/AND FULL CELL | 2 L217 5-4-3-2 OR/AND 2 CELL 1 UH218 5-4-3-2-1 OR/AND FULL CELL 2 UH219 3-3 OR/AND 1/4 CELL 2 UH221 2-2 OR/EXOR 1/4 CELL 2 UH222 DUAL 2-2 OR/AND/EXNOR FULL CELL 2 WH223 4NPUT EXNOR 1/2 CELL 2 UH224 41NPUT EXOR 1/2 CELL 2 UH225 2-1-1-2 OR/AND/EXOR 1/2 CELL 2 UH226 2-1-1-2 OR/AND/EXNOR 2 CELL 2 UH227 2-1 EXOR/AND/NAND V2 CELL 2 UH228 2-1 AND/EXOR 1/4 CELL 2 L251 4-TO-1 MUX W/ENABLE (LOW) 1/2 CELL 2 UH252 QUAD 2-TO-1 MUX |FULL CELL 2 UH253 2-TO-1 MUX W/ENABLE (LOW) 1/4 CELL 2 W/H254 2-TO-1 MUX W/GATED INPUTS 14 CELL 2 | UH255, DUAL 2-TO-1 MUX W/COM. SELECT 1/2 CELL 2 WH256 2-TO-1 MUX 1/4 CELL 2 L258 4-TO-1 MUX W/ENABLE (HIGH) 1/2 CELL 2 UH259 4-T0-1 MUX 1/2 CELL ~ UH261 1-OF-4 DECODER W/ENABLE (LOW) 1/2 CELL WH262 1-OF-4 DECODER W/ENABLE (HIGH) 1/2 CELL UH263 1-OF-4 DECODER (HIGH) FULL CELL U/H277 4-2-4-2-4-2 OR/AND 3/4 CELL MCA10000ECL MOTOROLA

TABLE 2 — MACRO LISTING (continued) INTERNAL (M) MACROCELLS UH278 3 DATA INPUT DATA LATCH 1/4 CELL 2 UH279 4-2-4-2-4-2-4-2 OR/AND FULL CELL 2 UH280 4-2-4-2 OR/AND 1/2 CELL 2 UH281 FULL ADDER FULL CELL 2 UH282 FULL ADDER W/GATED INPUTS 4/2 CELL 2 UH283 2-BIT LOOK-AHEAD CARRY FULL CELL 2 UH284 HALF ADDER WIGATED INPUTS 1 CELL 2 UH285 3-BIT ADDER (SUM) 1/2 CELL 2 UH286 3-BIT ADDER (CARRY) 12 CELL 2 UH290 D FLIP-FLOP WITH SET AND RESET 12 CELL 2 UH291 D FLIP-FLOP WITH RESET V2 CELL 2 UH292 D FLIP-FLOP WITH MUX 3/4 CELL 2 UH293 D LATCH WITH RESET 14 CELL 2 UH294 D LATCH WITH MUX 2 CELL 2 UH295 GATED 2-WAY D LATCH 12 CELL 2 UH296 EXNOR D LATCH 12 CELL 2 UH297 GATED 4-WAY D LATCH 3/4 CELL 2 UH298 DUAL D LATCH W/RESET 1/2 CELL 2 L302 INPUT OR/NOR 1/2 CELL 1 UH310 4-4-4-4 OR/AND FULL CELL 1 UH311 3-3-3-3 AND/OR FULL CELL 2 UH312 3-3-3 AND/OR 4/2 CELL 2 UH313 2-2 OR/AND 14 CELL 2 UH315, 2-2-1-1 OR/AND 1/2 CELL 2 UH318 3-3 AND/OR 1/2 CELL 1 1319 3-3-2-1 AND/OR 1/2 CELL UH320 2-3-4-4 AND/OR W/ENABLE (HIGH) FULL CELL UH321 6-6-4-4-2-2 OR/AND FULL CELL 1322 3-3-3 AND/OR (LPA ONLY) 12 CELL UH323 3-2-2-2-2-3 AND/OR FULL CELL UH324 5-5-5-5 AND/OR FULL CELL 1 . L328 2-1 AND/EXOR (LPA ONLY) . 1/2 CELL 2 UH331 3-2-2 AND/OR 1/2 CELL 2 UH332 GATED OR 1/2 CELL 2 UH333 GATED OR 1/2 CELL 2 UH370 DIFFERENTIAL LINE RECEIVER 1/4 CELL 2 UH371 2-1 MUX WITH DIFFERENTIAL INPUTS 1/4 CELL 2 UH372 D FLIP-FLOP W/DIFFERENTIAL CLOCK AND DATA 12 CELL 2 UH373 2-1 MUX WIDIFF INPUTS AND DIFF MUX CTL 1 CELL 1 UH374 DIFFERENTIAL LINE RECEIVER 174 CELL 1 UH375 D FLIP-FLOP WITH DIFFERENTIAL CLOCK V2 CELL 2 UH376 D FLIP-FLOP WITH DIFFERENTIAL CLOCK 12 CELL 2 L380 NOR LATCH 1a CELL 1 UH381 O FLIP-FLOP WITH SET 1/2 CELL 2 UH391 D FLIP-FLOP, NEGATIVE EDGE TRIGGERED v2 CELL 2 UH392 D FLIP-FLOP WITH MUX, NEGATIVE EDGE TRIGGERED 3/4 CELL 2 L/H393 D LATCH WITH CLOCK ENABLE (HIGH) 1/4 CELL 2 UH394 L394 D FLIP-FLOP WITH MUX, NEGATIVE EDGE TRIGGERED FULL CELL 2 UH395 D FLIP-FLOP WITH ASYN SET AND DATA ENABLE FULL CELL 2 UH396 SCAN D FLIP-FLOP FULL CELL 2 /H397 D LATCH WITH ASYN SET 14 CELL 2 | UH398 SCAN D LATCH W/ASYN SET 1/2 CELL 2 UHa00 12-INPUT OR 14 CELL 2 UHa01 12:INPUT NOR 14 CELL 2 Lao2z 2-INPUT OR/NOR, 3-INPUT OR/NOR 14 CELL 1 UHa03 8-INPUT OR/NOR 14 CELL 1 UHa04 12INPUT NOR 1/2 CELL 3 UHa11 2-2-2 OR/AND 1/4 CELL 3 UHa13 4-3-3-3 OR/AND 12 CELL 2 L414 3-3-3-3 OR/AND V2 CELL 2 ee MOTOROLA MCA10000ECL

TABLE 2 — MACRO LISTING (continued) INTERNAL (M) MACROCELLS UH416 4-2-3-2.3 OR/AND FULL CELL 3 UH417 5-4-3-2 OR/AND V2 CELL 2 UH418 5-4-3-2-1 OR/AND 3/4 CELL 2 UHa19 4-4 OR/AND 14 CELL 2 La21 DUAL EXOR V4 CELL 2 UH422 DUAL 2-2 OR/AND/EXOR V2 CELL UH424 6-INPUT EXNOR v2 CELL UH425 6-INPUT EXOR V2 CELL UH427 2-1 EXOR/AND/NAND 14 CELL Una38 6-5-4-3-2-1 OR/AND v2 CELL UH451 4-1 MUX W/ENABLE (LOW) V2 CELL L452 QUAD 2-TO-1 MUX V2 CELL UH453 2-TO-1 MUX W/ENABLE (LOW) V4 CELL UH454 2-TO-1 MUX W/ENABLE (HIGH) 1/4 CELL UH455 DUAL 2-TO-1 MUX W/ENABLE (HIGH) v2 CELL L456 TRIPLE 2-TO-1 MUX (COMMON SELECT) v2 CELL 2 L457 TRIPLE 2-TO-1 MUX V2 CELL 2 UH4s8 4-1 MUX W/ENABLE (HIGH) V2 CELL 3 UHa59 DUAL 4-1 MUX v2 CELL 3 unae1 1-OF-4 DECODER WITH ENABLE (LOW) 2 CELL 3 UH462 1-OF-4 DECODER WITH ENABLE (HIGH) v2. CELL L464 8-3 ENCODER FULL CELL LH465 1-OF-4 DECODER WITH ENABLE (LOW) v2 CELL UH466 1-OF-4 DECODER WITH ENABLE (HIGH) 172 CELL L470 DUAL 2-TO-1 MUX (COMMON SELECT) V4 CELL L474 DIFFERENTIAL LINE RECEIVER (LPA ONLY) v2 CELL 2 Las2 TRIPLE FULL ADDER FULL CELL 2 UH485 3-BIT ADDER 2 CELL 3 ~ UH501 2 INPUT OR (L MACRO, LPA ONLY) V4 CELL 1 UH502 2 INPUT NOR (L MACRO, LPA ONLY) 1/4 CELL 1 L503 5x2 INPUT OR : V2 CELL 1 U/H510 4-4-4-4 OR/AND V2 CELL 2 UH511 3-3.3-3 AND/OR V2 CELL 3 UH512 3-3-3 AND/OR v2. CELL 3 UHS513 3-1-1-1 OR/AND 4 CELL 2 UH518 3-3 AND/OR 14 CELL 2 UH519 3-3-.2-1 AND/OR v2 CELL 2 H520 2-3-4-4 AND/OR WIENABLE (HIGH) v2 CELL 3 UH523 3-2-2-2-2-3 AND/OR FULL CELL 3 H553 2-TO-1 MUX WIENABLE (LOW) V4 CELL 2 UHS71 8 OUTPUT BUFFER WIDIF INPUT AND ENABLE (L MACRO, LPA ONLY) V2 CELL 3 L585 SCAN D FLIP-FLOP Wi2-TO-1 MUX DATA INPUT 12 CELL 2 L593 W BUFFER 1/4 CELL 1 ) UH611 3-3-3 OR/AND 1/4 CELL 3 | UH616 4-2-3.3-2 OR/AND v2 CELL 3 | UH618 5-4-3-2-1 OR/AND V2 CELL ) UHes8 4-1 MUX v2 CELL : UH685 FULL ADDER W/GATED INPUTS V2 CELL | UHe31 D FLIP-FLOP W/RESET 1/2 CELL | UH692 D FLIP-FLOP WITH MUX 3/4 CELL . UH694 D FLIP-FLOP W/RESET (NEGATIVE HOLD TIME) V2 CELL 2 | UH802 3INPUT EXOR/EXNOR 14 CELL 3 : Lvig03 3INPUT EXOR/EXNOR V4 CELL 3 L804 DUAL 2 INPUT AND 1/4 CELL 2 L805 DUAL 2 INPUT NAND va CELL 2 L806 DUAL 2 INPUT AND/NAND 1/4 CELL 2 L807 DUAL 2 INPUT AND/NAND Va CELL 2 UH809 8-1 MUX WITH ENABLE (HIGH) FULL CELL 3 UH810 8-1 MUX WITH ENABLE (HIGH) FULL CELL 3 Ls11 DUAL 4 INPUT OR 1a CELL 1 MCA10000ECL MOTOROLA

TABLE 2 — MACRO LISTING (continued) INTERNAL (M) MACROCELLS L812 DUAL 4 INPUT OR/NOR V4 CELL 1 L813 DUAL 4 INPUT OR/NOR 4 CELL 1 Lg14 DUAL 4 INPUT NOR 14 CELL 1 L815 DUAL 2 INPUT OR VV CELL 1 isi6 DUAL 2 INPUT OR/NOR 1/4 CELL 1 L817 DUAL 2 INPUT OR/NOR va CELL 1 L818 DUAL 2 INPUT NOR 1/4 CELL 1 UH819 3-2-1 OR/AND 1/4 CELL 3 L820 2INPUT OR, 2-INPUT AND 1/4 CELL 2 L850 EXPANDABLE 2-1 MUX (CODER) AND 2x2-1 MUX 12 CELL 2

1851 EXPANDABLE 2-1 MUX W/2 CELL 2

L852 EXPANDABLE 2-1 MUX V2 CELL 2 (853 EXPANDABLE 2-1 MUX 2 CELL 2 L860 EXPANDABLE 4-1 MUX (CODER) WITH ENABLE 12 CELL 3 UHe61 EXPANDABLE 4-1 MUX V2 CELL 3 uHe62 EXPANDABLE 4-1 MUX v2 CELL UHe63 EXPANDABLE 4-1 MUX 2 CELL L870 EXPANDABLE 8-1 MUX (CODER) 72 CELL UH871 EXPANDABLE 8-1 MUX 1/2 CELL UH872 EXPANDABLE 8-1 MUX v2 CELL UH873 EXPANDABLE 8-1 MUX 1/2 CELL 3 Lg91 D FLIP-FLOP 1/2 CELL 2 L892 D FLIP-FLOP v2 CELL 2 L893 3xD LATCH WITH COMMON CLOCK V2 CELL 2 L/H894 D LATCH WITH MUX 1/4 CELL 3 L895 D FLIP-FLOP. 1a CELL 2 L896 3xD LATCH WITH COMMON CLOCK AND RESET v2 CELL 2 L897 DUAL LATCH WITH COMMON ENABLE (LPA ONLY) V4 CELL 2 INPUT INTERFACE (l) MACROCELLS UHIOO 2 INPUT OR/NOR 1 FCELL 1 UHIO1 2 INPUT OR (H MACRO, HPA ONLY) . 7 ECELL 1 UHI02 2 INPUT NOR (H MACRO, HPA ONLY) 1 ECELL 1 UHt03 DIFFERENTIAL BUFFER 7 CELL 1 UHIO4 DIFFERENTIAL BUFFER (H MACRO, HPA ONLY) TECELL 2 UHI05 DIFFERENTIAL BUFFER (H MACRO, HPA ONLY) 7 CELL 1 UHI06 INPUT BUFFER 1 ECELL 1 UHI07 INPUT BUFFER (H MACRO, HPA ONLY) 1 ECELL 1 UHIo8 INPUT BUFFER (H MACRO, HPA ONLY) TECELL 1 X MACROCELLS (50 AND 68 OHM OUTPUT DRIVERS) UHX01 2 INPUT OR/NOR 1 O-CELL 1 UHXo2 4 INPUT OR/NOR 1 O-CELL 1 UHX03 2-2 OR GATES 1 O-CELL 2 UHXo4 2-2 OR GATES 1 O-CELL 2 UHX05 5 INPUT OR/NOR 1.0-CELL 1 UHX06 8 INPUT OR/NOR 2 O-CELLS 2 UHX0? DUAL AND/OR 2 O-CELLS 2 UHX08 DUAL AND/OR 2 O-CELLS 2 UHX11 2-2 OR/AND 1 O-CELL 2 UHX21 2.2 OR/EXOR 1.O-CELL 2 UHX51 2-T0-1 MUX 1 O-CELL 2 UHX52 DUAL 2-TO-1 MUX 2 O-CELLS 2 UHXs3 2-TO-1 MUX WITH ENABLE (LOW) 1 O-CELL 2 UHX58 4-T0-1 MUX 2 O-CELLS 3 Lea 4-TO-1 MUX (Y OUTPUTS) 2 O-CELLS 3 UHX71 DIFFERENTIAL BUFFER 1 O-CELL 2 UHX91 D FLIP-FLOP W/RESET 2 O-CELLS 2 UHX92 D LATCH WITH RESET 1 O-CELL 2 UHX93 DUAL D LATCH WITH RESET 2 O-CELLS 2 UHX94 D FLIP-FLOP W/RESET 2. O-CELLS 2 | MOTOROLA MCA10000ECL : 16

TABLE 2 — MACRO LISTING (continued) ZX MACROCELLS (25 AND 50 OHM CUTOFF DRIVERS) 2x01 2 INPUT OR (50 OHM CUTOFF DRIVER} 1 O-CELL 1 2x02 4 INPUT OR (50 OHM CUTOFF DRIVER) 1 0-CELL 1 2X03 2-2 OR (50 OHM CUTOFF DRIVER) 1 O-CELL 2 2X04 2-2 OR (50 OHM CUTOFF DRIVER) 1 O-CELL 2 2X05 5-INPUT OR (50 OHM CUTOFF DRIVER) 10-CELL 1 2X06 8-INPUT OR (50 OHM CUTOFF DRIVER) 2 O-CELLS 2 2X07 DUAL AND/OR (50 OHM CUTOFF DRIVER) 2 0-CELLS 2 2x11 2-2 OR/AND (50 {2 CUTOFF) 1 O-CELL 2 2x51 2-TO-1 MUX (50 © CUTOFF) 1 0-CELL 2 2X52 DUAL 2-TO-1 MUX (50 2 CUTOFF) 2 O-CELLS 2 2x58 4-TO-1 MUX (60 © CUTOFF) 2 O-CELLS 2x1 DIFFERENTIAL BUFFER (50 OHM CUTOFF DRIVER) 1 O-CELL 2x81 25 OHM OR/NOR DRIVER (CUTOFF)* 1 O-CELL 2x82 4 INPUT OR GATE (25 OHM CUTOFF DRIVER)* 1 O-CELL 2x83 2-2 OR GATES (25 OHM CUTOFF DRIVER)* 2 0-CELLS 2x84 2-2 OR GATES (25 OHM CUTOFF DRIVER)* 2 O-CELLS 2X85 8 INPUT OR GATE (25 OHM CUTOFF DRIVER)* 2 0-CELLS 2X86 2-2 OR/AND (25 OHM CUTOFF DRIVER)* 1 O-CELL 2x87 2-TO-1 MUX (25 OHM CUTOFF DRIVER)* 2 O-CELLS CLOCK BUFFER MACROCELLS CLKS DIFFERENTIAL CLOCK GENERATOR (5 GATES) CLK CELL 2 CLKE DIFFERENTIAL CLOCK GENERATOR (6 GATES) CLK CELL 2 CLK7 DIFFERENTIAL CLOCK GENERATOR (6 GATES + EXT. GATES) CLK CELL 2 STANDARD ECL OUTPUTS vo2s 25 OHM PAD CELL PAD CELL O50 50/68 OHM PAD CELL PAD CELL . BIDIRECTIONAL W/O CELLS B25 25 OHM BIDIRECTIONAL PAD CELL PAD CELL vB50 50 OHM BIDIRECTIONAL PAD CELL PAD CELL vaso BIDIRECTIONAL STECL BUFFER . PAD CELL SERIES-TERMINATED (STECL) OUTPUTS vsoo STECL PAD CELL — 0 OHMS SERIES PAD CELL | VS27 STECL PAD CELL — 27 OHMS SERIES PAD CELL vs40 STECL PAD CELL — 40 OHMS SERIES PAD CELL MCA10000ECL MOTOROLA

TABLE 3 — DC ELECTRICAL CHARACTERISTICS MCA3 arrays are available in the following four compatibility options: 10KH operating at — 4.5 Vdc 10KH operating at — 5.2 Vde 100K operating at —4.5 Vdc 100K operating at —5.2 Vde The power supply voltage limits for the following tables are: Vee1 = —4.2 to —4.8 volts or Vcc = Vcco = 0 volts VEE1 = —4.784 to —5.616 volts VEE2 = —3.128 to —3.672 volts 10KH COMPATIBLE OPTIONS — ECL OUTPUTS/INPUTS Output HIGH Voltage | =1020 | -eao | -980 | -s10 | -s20 | -735 | mv_| Vor? | Output HIGH Voltage (low power) | = 104s | 240 | -1000 | -sto | -sa0 | -735 | mv _| Vou? _| Output HIGH Voltage (cutoff | -1080 | -e40 | -1010 | sto | 950 | -735 | mv _| Output LOW Voltage | -1950 | - 1630 | - 1950 | ~1630 | - 1960 | -1600 | mv_| Output LOW Voltage (cutoff) 2020 | ~ 1960 | —20z0 | ~1960 | 2020 | -1950 | mv _| Input HIGH Voltage | =1170 | ~s10 | -1130 | -780 | -1070 | -700 | mv_| Input LOW Voltage | =2020 | - 1480 | 2020 | -1480 | - 2020 | -1450 | mv_| 1, Standard (HX macro) 50 ohm outputs terminated with a 50 ohm resistor to ~ 2.0 volts or low power (LX macro) outputs terminated with a 68 ohm resistor to - 2.0 volts. 2. Low power outputs are VO50 or VB50 outputs which are driven by an LX macrocell. This spec shows levels for low power outputs with a 60 ohm external load to ~2.0 volts. 3. Cutoff outputs include both 50 ohm and 25 ohm cutoff outputs. 100K COMPATIBLE OPTIONS — ECL OUTPUTS/INPUTS 7 Specification Limits Ty = 25°C to 115°C | min [tye | Mex | Output HIGH Voltage [| =1028 | -955 | -e80 | mv_| Output HIGH Voltage (low power) | =104 | -s75 | -e80 | mv _| Vor? | Output HIGH Voltage (cutoff) | =1050 | -s10 | -735 | mv_| Output LOW Voltage | -1s10 | -1705 | -1620 | mv _| Voi _| Output LOW Voltage (cutoff) | -2020 | -1985 | -1950 | mv | Input HIGH Voltage [-=165 [| -a50 | mv | Input LOW Voltage | -2020 | | = 1475 | mv | 1. Standard (HX macro) 50 ohm outputs terminated with a 50 ohm resistor to ~ 2.0 volts or low power (LX macro) outputs terminated with a 68 ohm resistor to — 2.0 volts. 2. Low power outputs are VO5O or VBS50 outputs which are driven by an LX macrocell. This spec shows levels for low power outputs with a 60 ohm external load to — 2.0 volts. 3. Cutoff outputs include 50 and 25 ohm cutoff outputs. Cutoff outputs are terminated with 25/50 ohm resistors to ~ 2.0 volts. Cutoff outputs are not compensated for temperature and, therefore exhibit the same temperature tracking as the 10KH specification above. MOTOROLA MCA10000ECL

TABLE 3 — DC ELECTRICAL CHARACTERISTICS (continued) 10KH COMPATIBLE OPTIONS — STECL OUTPUTS/INPUTS (6.0 mA and 10 mA Current Source) Me oe Symbol | Min [Max | min | Max | Min | Max | | You | Oupurnichvotage | = 1020 | ~a10 | 90 | ~700 | -s20 | =700 | mv _| | Vor [Oupurtowvorage | — 1880 | ~ 160 | ~ 1960 | — v6a0 | ~1980 | - 1600 | mv _| [vin [input HGH Vorage | =e | era | -r1e0 | -200 [=1070 [ -700 [mv _| [vu [input tow votge | 2020 | ~ sa | ~2020 | ~r480 | -2020 | 450 [mv _| 1. STECL output levels are specified with no external load. 2. This table specifies levels for all STECL outputs driven by HX or LX output macrocells. 100K COMPATIBLE OPTIONS — STECL OUTPUTS/INPUTS (6.0 mA and 10 mA Current Source) [min | tye [Mex | | Von | OupurHicHVotage 1028 | 28s | a80 | mv | [Vor [ouwpurtowvorage = 1800 | t705 | 1620 | mv | | Vix | imputHiGHVorege | tes P50 | [vu | impurtowvortage Taco | ta | mv | 1. STECL output levels are specified with no external load. 2. This table secifies levels for all STECL outputs driven by HX or LX output macrocelis. DC CURRENT LIMITS — 10KH AND 100K COMPATIBLE OPTIONS [eats | attain vongee | 8 See © ey Ma PVM utidown + (NuMingr) ma | tputidown _| | 0.067 for standard input (75K pulldown) | ma _| | Iputtdown —_| where: | tputidown | | tinput__| [input | [a ne high power aay ma a [Teen gs [a DC CURRENT AND RESISTOR LIMITS — STECL OUTPUTS AND INPUT CS | min [tye | Max _| [Mowto [steciandimnues | 8 tas | m [tour60 | StecLandinpxcs Ts | go] ma | [Rour27 | STECL Series Resistor | aaa ones | [Rour40 | stect series Restor || hems | 1. fout 10 and loyt 6.0 refer to a 10 mA or 6.0 mA, respectively, internal current source for a STECL output or an input current source. 2. Rout 27 and Rout 40 refer to a 27 ohm or 40 ohm, respectively, internal series resistor at the output of a STECL driver. a MCA10000ECL MOTOROLA

TABLE 3 — DC ELECTRICAL CHARACTERISTICS (continued) RECOMMENDED OPERATING CONDITIONS [sympot [ hanced Vas Ei leeremmveearee vee pee | “11 [auneton Temperture AC and OC Spea) atts [Tutt [ Max Cock input ise Ties 2010808) SS 8a LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED [smoot [Chasen date 0 [Tur | Out Sour Curent Coninuous 6088 ohm) 0m [tout | output Source Curent Suge (5068 ohm 100m | [eur Output Soure Curent Cominuous 25 ohm) ma [tour _| Output Sour Curent Coninvous STEGL Wma) Sma | [tout | Output Sour Curent Suge STECL10ma)— wom [ou | Ouput Sours Curent Coninvous STECL 6OmA) 8m [our | Output Souree Curent Suge STECL,60ma) dam [1 | unaton Tenperture notinelinid tse 1. If a cutoff output is in the low (disabled) state and is being forced by an external driver, the forcing voltage must fall between Vcc and — 2.0 volts. 2. Surge current is defined as an output current between 30 mA and 100 mA for a 50/68 ohm output, 60 mA and 200 mA for a 25 ohm output, 5.0 mA and 40 mA for a STECL (10 mA), and 9.0 mA and 44 mA for a STECL (6.0 mA). The ‘surge current must last for less than 10 us and must have a duty cycle equal to or less than 1%. ee MOTOROLA MCA10000ECL

FIGURE 13 — 235 PIN GRID ARRAY PACKAGE WITH OPTIONAL HEAT SINK L ° ae WQOGQOQOOQOOQOQOQOQOHHOHOOO) v T WOOQODHOOQOQOOGQOOQOOQOOOO|T 4 WDOOOODOQOOOQOODODOOOO| S$ ny Q9OOGQOOQHOOOOOOOOSS|R f- i ©QQOO® OOOCOOO!P po fofoyotoro} @OOQOO|N s LOFT) ©QOQOO|M LOLOTOTO} @OOO}L C000 @OOO| K ©2000 @@OO} J ©000 LOLOLOYO} ey R ®OOOO @OOOO| F 8 @OQQOOO @OOOOOO|E OQOQDOOOQOOQOQOQOOQOOSOOO| 0 1 ®QMQOQOOQOQGQOOOHQHQOGOOOOO|C PLOWOOGQOOQOQOOOHOOOO| 8 DOODOQOOQDQOOOODODOOOGO) A FT 1234567 8 9101112131415161718 c—| W: Rev. 2.2 12/19/89 E A [ef ors or booaooood fF [eo | .074 | 0.09 poooooong [bo | 0.015 [0.078 | pogcoooodg co a Po oooebed [6 |= 0.7007. = poooouoo dem ae pegooogo gras poooaoaooand [Mw _| 0.85 sq [0.91 Sa 0 [ps] 0.1208. = AREIN INCHES [wo 075078 Thermalloy Heat Sink #2329B for 235 PGA MCA10000ECL MOTOROLA

FIGURE 14 — 289 PIN GRID ARRAY PACKAGE WITH NO HEAT SINK - K ewveran tycpose Ath ° stand in d= bo © ©60 ©0000 08 © w = O©F00OOOHHHHHOHOOOOHOO |v == ©900000000000000000 fu -— ©00000000000000000000|T —> CRO RCHCROROMOMORORCRORORORCRCRCRORORCMIN IES — ©0000 COROROMOMOM ME t— ©0000 [ ®2O0O00|N — ©0000 ®0000]H — ©0000 ©0000/F — ®@LOOTHSOOOOOSFOOOOO® |e -—= 01 2000000000000 00000000|0 > 200KOCHOHHHHOOHOOHHOHOGH Jc = — [ooo oO MOR OM OOM OMOMOMOMOMOMOMOMONO} B 4 mn a 12°34 5 6 7 B 9 10111213 44 15 16 17 18 19 20 21 me © GID CID © > © GT a DIMENSIONS (inches) OL FVHHHHHHOHHHHHHOHOH ee ©9000 00HOHOHHHHOKOO ©9O29OHKHOHHHHHHOHOHHOO [ a | 2088q_| 2.108q focccccccsbessce_cc el = 0.066 Ref.- ©0200 @000 ®0000 202000 | or | = 0.05 Typ.— ©0000 20000 0.059 90000 00000 SOOSS TOSes = 0.100 Typ. = ©CO00Q | i | (OOM OMOMC) 0.142 ©0000 ©0000 [st ©0000 J ©0000 a = 0.325 Typ. = 00900) $|eseee 0.242 ©8200 195 dia. ©0000 0.079 ecccscvcefoccocccs od [o | — 0.080 Typ. PODVDODOHODOOHOHHOHOODOOSD - S OROMOROMOMCMOMOMOM MONON OR OR OM OMOMOM) [P| =~ 0.040 Typ. OLCLCHOHHHHHHHHOHHHHOOH ay ai® © eaT® oD P PWR/GND by-pass. ° Capacitors (12X) 6 decoupling VEE/GND 6 decoupling VEE2/GND ae MOTOROLA MCA10000ECL

FIGURE 15 — 289 PIN GRID ARRAY PACKAGE WITH OPTIONAL HEAT SINK - E = tik CGN. by pase G Stand-off Pin (4X) wt = O0FOHHHHHHHLHHHHOOO v a POOH HHHOHHHHODHHOHHGOO Uu -— POOCHHLHHHHOHHOHHOOOOOHD|T pa: GOOG GOOOOHOOHOOOOO®O s — ©0000) ®O9OO0/R ;-— ©2000 ®S2GeeC0/ a — ©2000 ®O2SCOO| P ae = al |ooooo jooeeo|m v2 —— ©2000 O@CCSlL -— ©0000 POCOO! J —) ©2800 JSOOCOSO!|H ——) ©0000 SOGGC0/G —) GOGHHOHHHHHHHHHHHHOO E — o1 SPOOKHSHHHHHHSHHGHOOHOOB!/D $s —— Lf OQOGHSHOHHHOHHHSOHGOOHHOD Cc =) O0FFGO0O0FHHHOHHGHHHHOO B ne Fc 1234567 8 9101112131415161718192021 DIMENSIONS {inches) © GID GI © 0 0 a GID oT] ooh] 4 g4 ET a a Le [oo [ons “Toe | jap eoooogaoccms Lo “Stas | [fp Oooo ooooooR [Pe [one | oes | op COBO OOO ROO. [co _|— oot | (oP OOBOOOOMAOOCpe eMOOOO0OO000 00 Te Emre (poooococoaasl, en oogeoocngotbe seocecoggo ootge ee oogoooomoog: [ox [= 100m | Jae OOMOOOOMTUT, [9 [= o020 Tye, = gp oooocooocock Ee re ee od ee ee kp EID 0 0 0 CD EID e PWR/GND by-pass Capacitors (124) 6 decoupling VEE/GND- 6 decoupling VEE2/GND MCA10000ECL MOTOROLA

ASIC Regional Design Centers U.S.A International Motorola reserves the right to make changes without further notice to any products herein to improve reliability. function or design. Motoroladoesnotassume | any liability arising aut of the application or use of any product or circuit described herein; neither does it convey any license under its patentrightsnorthe rights. | of others, Motorola products are not designed. intended. or authorized for use as components in systems intended for surgical implant into the body. or other | ‘applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnity and | hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims. costs. damages, and expenses, andreasonable | attorney fees arising out of. directly or indirectly. any claim of personal injury or death associated with such unintended or unauthorized use. evenifsuchciaim | alleges that Motorola was negligent regarding the design or manutacture of the part. Motorola and ‘Mare registered trademarks of Motorola. Inc. Motorola. | Inc. is an Equal Opportunity/Atirmative Action Employer. | Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 7 (@) MOTORS, A. ee