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MC9S08AC128MLKE

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MC9S08AC128 8-Bit Microcontroller Data Sheet

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Data Sheet: Technical Data Document Number: MC9S08AC128 Rev. 2, 6/2009 © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. MC9S08AC128 8-Bit Microcontroller Data Sheet 8-Bit HCS08 Central Processor Unit (CPU)

40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND, CALL and RTC instructions Memory Management Unit to support paged memory. Linear Address Pointer to allow direct page data accesses of the entire memory map Development Support Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip in-circuit emulator (ICE) Debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints. Memory Options Up to 128K FLASH — read/program/erase over full operating voltage and temperature Up to 8K Random-access memory (RAM) Security circuitry to prevent unauthorized access to RAM and FLASH contents Clock Source Options Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module System Protection Optional computer operating properly (COP) reset with option to run from independent internal clock source or bus clock CRC module to support fast cyclic redundancy checks on system memory Low-voltage detection with reset or interrupt Illegal opcode detection with reset Master reset pin and power-on reset (POR) Power-Saving Modes Wait plus two stops Peripherals ADC — 16-channel, 10-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel SCIx — Two serial communications interface modules supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge SPIx — One full and one master-only serial peripheral interface modules; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting IIC — Inter-integrated circuit bus module; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing TPMx — One 2-channel and two 6-channel 16-bit timer/pulse-width modulator (TPM) modules: Selectable input capture, output compare, and edge-aligned PWM capability on each channel. Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — 8-pin keyboard interrupt module Input/Output Up to 70 general-purpose input/output pins Software selectable pullups on input port pins Software selectable drive strength and slew rate control on ports when used as outputs Package Options 80-pin low-profile quad flat package (LQFP) 64-pin quad flat package (QFP) 44-pin low-profile quad flat package (LQFP)

MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor2 Table of Contents Related Documentation MC9S08AC128 Series Reference Manual (MC9S08AC128RM) contains extensive product information including modes of operartion, memory, resets and interrupts, reg- ister definitions, port pins, CPU, and all peripheral module information. For the latest version of the documentation, check our website at: http://www.freescale.com Chapter 1 Chapter 2 Chapter 3 3.9 Internal Clock Generation Module Characteristics . . . 24 Chapter 4 Chapter 5

MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 3 Chapter 1 Device Overview The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core.

1.1 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU.

MC9S08AC128 MCU Series Data Sheet, Rev. 2

4 Freescale Semiconductor

Figure 1-1. MC9S08AC128 Series Block Diagram KBI1P7–KBI1P0 PTD3/KBI1P6/AD1P11 PTD4/TPM2CLK/AD1P12 PTD5/AD1P13 PTD6/TPM1CLK/AD1P14 PTC1/SDA1 PTC0/SCL1 VSS VDD PTE3/TPM1CH1 PTE2/TPM1CH0 PTE0/TxD1 PTE1/RxD1 PTD2/KBI1P5/AD1P10 PTD1/AD1P9 PTD0/AD1P8 PTC6 PTC5/RxD2 PTC4 PTC3/TxD2 PTC2/MCLK PORT CPORT DPORT E 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) IIC MODULE (IIC1) SERIAL PERIPHERAL INTERFACE MODULE (SPI1) USERMEMORY DEBUG MODULE (DBG) (AW128 = 128K, 8K) HCS08 CORE CPUBDC PTE5/MISO1 PTE4/SS1 PTE6/MOSI1 PTE7/SPSCK1 HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD LOW-POWER OSC INTERNAL CLOCK GENERATOR (ICG) RESET VSSAD VDDAD VREFH ANALOG-TO-DIGITAL CONVERTER (ADC) 6-CHANNEL TIMER/PWM MODULE (TPM1) PTD7/KBI1P7/AD1P15 10-BIT BKGD/MS PTF3/TPM1CH5 PTF2/TPM1CH4 PTF0/TPM1CH2 PTF1/TPM1CH3 PORT F PTF5/TPM2CH1 PTF4/TPM2CH0 PTF6 PTF7 INTERFACE MODULE (SCI2) SERIAL COMMUNICATIONS (AW96 = 96K, 6K) VREFL RQ/TPMCLK AD1P15–AD1P0 SPSCK1 SS1 MISO1 MOSI1 TPM1CLK or TPMCLK TPM1CH0–TPM1CH5 SCL SDA RXD2 TXD2 INTERFACE MODULE (SCI1) SERIAL COMMUNICATIONS RXD1 TXD1 SERIAL PERIPHERAL INTERFACE MODULE (SPI2) SPSCK2 MISO2 MOSI2 6-CHANNEL TIMER/PWM MODULE (TPM2) TPM2CLK or TPMCLK TPM3CH1 TPM3CH0 2-CHANNEL TIMER/PWM MODULE (TPM3) TPMCLK TPM2CH0–TPM2CH5 FLASH, RAM (BYTES) VOLTAGE REGULATOR EXTAL XTAL PTH3/TPM2CH5 PTH2/TPM2CH4 PTH0/TPM2CH2 PTH1/TPM2CH3 PORT H PTH5/MOSI2 PTH4/SPSCK2 PTH6/MISO2 - Pin not connected in 64-pin and 48-pin packages - Pin not connected in 48-pin package PTB3/AD1P3 PTB2/AD1P2 PTB0/TPM3CH0/AD1P0 PTB1/TPM3CH1/AD1P1 PORT B PTB5/AD1P5 PTB4/AD1P4 PTB6/AD1P6 PTB7/AD1P7 PTJ3 PTJ2 PTJ0 PTJ1 PORT J PTJ5 PTJ4 PTJ6 PTJ7 PTG3/KBI1P3 PTG2/KBI1P2 PTG0/KBIP0 PTG1/KBI1P1 PORT G PTG5/XTAL PTG4/KBI1P4 PTG6/EXTAL PTA3 PTA2 PTA0 PTA1 PORT A PTA5 PTA4 PTA6 PTA7 CYCLIC REDUNDANCY CHECK MODULE (CRC)

MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 5 Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals.

2.1 Device Pin Assignment

Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device. Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package 80-Pin LQFP PTG3/KBI1P3PTC4 PTC5/RxD2 PTD3/KBI1P6/AD1P11IRQ/TPMCLK PTD2/KBI1P5/AD1P10RESET VSSADPTF0/TPM1CH2 VDDADPTF1/TPM1CH3 PTD1/AD1P9PTF2/TPM1CH4 PTD0/AD1P8 PTF5/TPM2CH1 PTB7/AD1P7 PTF6 PTB6/AD1P6 PTJ0 PTB5/AD1P5 PTJ1 PTB4/AD1P4 PTJ2 PTB3/AD1P3 PTJ3 PTB2/AD1P2 PTE0/TxD1 PTB1/TPM3CH1/AD1P1 PTE1/RxD1 PTB0/TPM3CH0/AD1P0 PTF3/TPM1CH5 PTH3/TPM2CH5 PTF4/TPM2CH0 PTC3/TxD2 PTC2/MCLK PTH6/MISO2 PTH5/MIOSI2 PTH4/SPCK2 VDD (NC) VSS PTG6/EXTAL PTJ6 PTG5/XTAL PTJ7 VREFH PTG2/KBI1P2 PTD7/KBI1P7/AD1P15 PTA0 PTD6/TPM1CLK/AD1P14 PTD5/AD1P13 PTD4/TPM2CLK/AD1P12 PTG0/KBI1P0 PTG4/KBI1P4 PTG1/KBI1P1 PTC6 PTF7 PTE2/TPM1CH0 PTE3/TPM1CH1 PTH2/TPM2CH4 PTH1/TPM2CH3 PTH0/TPM2CH2 PTA7 PTC1/SDA1 PTC0/SCL1 BKGD/MS VREFLPTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTE4/SS1 PTE5/MISO1 VSS VDD PTE6/MOSI1 PTE7/SPSCK1 PTJ4 PTJ5 Note: Pin names in bold are lost in lower pin count packages.

Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2

6 Freescale Semiconductor

Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices. Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package PTF2/TPM1CH4 RESET PTF0/TPM1CH2 PTF3/TPM1CH5 PTF4/TPM2CH0 PTC6 PTF7 PTG2/KBI1P2 PTG1/KBI1P1 PTG0/KBI1P0 VDD VSS PTE7/SPSCK1 PTE6/MOSI1 PTB7/AD1P7 PTD0/AD1P8 PTD1/AD1P9 VDDAD VSSAD PTB1/TPM3CH1/AD1P1 PTB6/AD1P6 PTD5/AD1P13 VREFH PTC5/RxD2 PTG5/XTAL BKGD/MS VREFL PTG3/KBI1P3 PTD6//TPM1CLK PTD7/AD1P15/KBI1P7 18 19 20 21 22 23 50 51 5253 54 55 17 32 PTF5/TPM2CH1 PTF6 PTE0/TxD1 16PTE3/TPM1CH1 PTA0 PTA1 PTA2 PTA3 PTB5/AD1P5 PTB4/AD1P4 PTB3/AD1P3 PTB2/AD1P2 PTG6/EXTAL VSS PTC0/SCL1 PTC1/SDA1 PTF1/TPM1CH3 PTE1/RxD1 15PTE2/TPM1CH0 PTA4 28 29 30 31 PTD2KBI1P5/AD1P10 PTD3/KBI1P6/AD1P1147 PTC3/TxD2 63 62 61 PTC2/MCLK 60PTC4 IRQ/TPMCLK PTE4/SS1 PTE5/MISO1 PTA5 PTA6 PTB0/TPM3CH0/AD1P0 PTA7 PTD4/AD1P12/TPM2CLK PTG4/KBI1P4 64-Pin QFP Note: Pin names in bold are lost in lower pin count packages.

Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 7 Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device. Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package Table 2-4. Pin Availability by Package Pin-Count Pin Number Lowest < -- Priority --> Highest 80 64 44 Port Pin Alt 1 Alt 2

111 P T C 4

222 I R Q T P M C L K 1

333 R E S E T

444 P T F 0 T P M 1 C H 2

555 P T F 1 T P M 1 C H 3

6 6 — PTF2 TPM1CH4 7 7 — PTF3 TPM1CH5

886 P T F 4 T P M 2 C H 0

32 PTD3/KBI1P6/AD1P11

Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2

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99 — P T C 6 10 10 — PTF7 11 11 7 PTF5 TPM2CH1 12 12 — PTF6 13 — — PTJ0 14 — — PTJ1 15 — — PTJ2 16 — — PTJ3 17 13 8 PTE0 TxD1 18 14 9 PTE1 RxD1 19 15 10 PTE2 TPM1CH0 20 16 11 PTE3 TPM1CH1 21 17 12 PTE4 SS1 22 18 13 PTE5 MISO1 23 19 14 PTE6 MOSI1 24 20 15 PTE7 SPSCK1 25 21 16 V SS 26 22 17 V DD 27 — — PTJ4 28 — — PTJ5 29 — — PTJ6 30 — — PTJ7 31 23 18 PTG0 KBI1P0 32 24 19 PTG1 KBI1P1 33 25 20 PTG2 KBI1P2 34 26 21 PTA0 35 27 22 PTA1 36 28 — PTA2 37 29 — PTA3 38 30 — PTA4 39 31 — PTA5 40 32 — PTA6 41 33 — PTA7 42 — — PTH0 TPM2CH2 43 — — PTH1 TPM2CH3 44 — — PTH2 TPM2CH4 45 — — PTH3 TPM2CH5 46 34 23 PTB0 TPM3CH0 AD1P0 47 35 24 PTB1 TPM3CH1 AD1P1 48 36 25 PTB2 AD1P2 49 37 26 PTB3 AD1P3 Table 2-4. Pin Availability by Package Pin-Count (continued) Pin Number Lowest < -- Priority --> Highest 80 64 44 Port Pin Alt 1 Alt 2

Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 9 50 38 — PTB4 AD1P4 51 39 — PTB5 AD1P5 52 40 — PTB6 AD1P6 53 41 — PTB7 AD1P7 54 42 27 PTD0 AD1P8 55 43 28 PTD1 AD1P9 56 44 29 V DDAD 57 45 30 V SSAD 58 46 31 PTD2 KBI1P5 AD1P10 59 47 32 PTD3 KBI1P6 AD1P11 60 48 33 PTG3 KBI1P3 61 49 — PTG4 KBI1P4 62 50 — PTD4 TPM2CLK AD1P12 63 51 — PTD5 AD1P13 64 52 — PTD6 TPM1CLK AD1P14 65 53 — PTD7 KBI1P7 AD1P15 66 54 34 V REFH 67 55 35 V REFL 68 56 36 BKGD MS 69 57 37 PTG5 XTAL 70 58 38 PTG6 EXTAL 71 59 39 V SS 72 — — V DD(NC) 73 60 40 PTC0 SCL1 74 61 41 PTC1 SDA1 75 — — PTH4 SPSCK2 76 — — PTH5 MOSI2 77 — — PTH6 MISO2 78 62 42 PTC2 MCLK 79 63 43 PTC3 TxD2 80 64 44 PTC5 RxD2

1 TPMCLK, TPM1CLK, and TPM2CLK options are

configured via software; out of reset, TPM1CLK, TPM2CLK, and TPMCLK are available to TPM1, TPM2, and TPM3 respectively. Table 2-4. Pin Availability by Package Pin-Count (continued) Pin Number Lowest < -- Priority --> Highest 80 64 44 Port Pin Alt 1 Alt 2

Chapter 2 Pins and Connections MC9S08AC128 MCU Series Data Sheet, Rev. 2

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MC9S08AC128 Series Data Sheet, Rev. 2 Freescale Semiconductor 11 Chapter 3 Electrical Characteristics and Timing Specifications

3.1 Introduction

This section contains electrical and timing specifications.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). Table 3-1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations.

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 Series Data Sheet, Rev. 2

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Table 3-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to + 5.8 V Input voltage VIn – 0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD.

3 Power supply must maintain regulation within operating VDD range during instantaneous and

operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. ID ± 25 mA Maximum current into VDD IDD 120 mA Storage temperature Tstg –55 to +150 °C

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 13

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 3-1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) Eqn. 3-2 Solving equations 1 and 2 for K gives: Table 3-3. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH –40 to 125 °C Maximum junction temperature TJ 150 °C Thermal resistance 1,2,3,4 80-pin LQFP 2s2p 64-pin QFP 2s2p 44-pin LQFP 2s2p

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal

resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2 Junction to Ambient Natural Convection

3 1s - Single Layer Board, one signal layer 4 2s2p - Four Layer Board, 2 signal and 2 power layers θJA °C/W

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 Series Data Sheet, Rev. 2

14 Freescale Semiconductor

K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3-3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

3.6 DC Characteristics

This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table 3-4. ESD and Latch-up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ω Storage Capacitance C 100 pF Number of Pulse per pin – 3 Machine Series Resistance R1 0 Ω Storage Capacitance C 200 pF Number of Pulse per pin – 3 Latch-up Minimum input voltage limit – 2.5 V Maximum input voltage limit 7.5 V Table 3-5. ESD and Latch-Up Protection Characteristics Num C Rating Symbol Min Max Unit

1 C Human Body Model (HBM) VHBM ± 2000 – V

2 C Machine Model (MM) VMM ± 200 – V

3 C Charge Device Model (CDM) VCDM ± 500 – V

4C Latch-up Current at TA = 125°CI LAT ± 100 – mA

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 15 Table 3-6. DC Characteristics Num C Parameter Symbol Min Typ 1 Max Unit 1 — Operating Voltage V DD 2.7 — 5.5 V

2 P Output high voltage — Low Drive (PTxDSn = 0)

5 V, ILoad = –2 mA

3 V, ILoad = –0.6 mA 5 V, ILoad = –0.4 mA 3 V, ILoad = –0.24 mA VOH VDD – 1.5 VDD – 1.5 VDD – 0.8 VDD – 0.8 VP Output high voltage — High Drive (PTxDSn = 1)

5 V, I

Load = –10 mA

3 V, ILoad = –3 mA

3 V, ILoad = –0.4 mA VDD – 1.5 VDD – 1.5 VDD – 0.8 VDD – 0.8

3 P Output low voltage — Low Drive (PTxDSn = 0)

Load = 2 mA 3 V, ILoad = 0.6 mA 5 V, ILoad = 0.4 mA 3 V, ILoad = 0.24 mA VOL 1.5 1.5 0.8 0.8 VP Output low voltage — High Drive (PTxDSn = 1) Load = 10 mA

3 V, ILoad = 3 mA

5 V, ILoad = 2 mA

3 V, ILoad = 0.4 mA 1.5 1.5 0.8 0.8

4 P Output high current — Max total I

IOHT — 100 mA P Output low current — Max total I OL for all ports IOLT — 100 mA 6 P Input high 2.7v ≤ V DD 4.5v V IH 0.70xVDD —— voltage; all digital inputs 4.5v ≤ VDD ≤ 5.5v VIH 0.65xVDD ——V 7 P Input low voltage; all digital inputs V IL — — 0.35 x V DD 8 P Input hysteresis; all digital inputs Vhys 0.06 x VDD mV 9 P Input leakage current; input only pins 2 |IIn|— 0 . 1 1 μA 10 P High Impedance (off-state) leakage current 2 |IOZ|— 0 . 11 μA

11 P Internal pullup resistors 3 RPU 20 45 65 k Ω

12 P Internal pulldown resistors 4 RPD 20 45 65 k Ω

13 C Input Capacitance; all non-supply pins CIn —— 8p F

14 D RAM retention voltage VRAM —0 . 6 1 . 0V 15 P POR rearm voltage VPOR 0.9 1.4 2.0 V

16 D POR rearm time t POR 10 — — μs

17 P Low-voltage detection threshold — high range

VLVDH 4.2 4.3 4.3 4.4 4.4 4.5 V 18 P Low-voltage detection threshold — low range V DD falling VDD rising VLVDL 2.48 2.54 2.56 2.62 2.64 2.7 V

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 Series Data Sheet, Rev. 2

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Figure 3-1. Typical IOH (Low Drive) vs VDD–VOH at VDD = 3 V 19 P Low-voltage warning threshold — high range VDD falling VDD rising VLVWH 4.2 4.3 4.3 4.4 4.4 4.5 V

20 P Low-voltage warning threshold — low range

V DD falling VDD rising VLVWL 2.48 2.54 2.56 2.62 2.64 2.7 V P Low-voltage inhibit reset/recover hysteresis V hys — 100 mV

22 P Bandgap Voltage Reference

5 VBG 1.170 1.200 1.230 V 1 Typical values are based on characterization data at 25°C unless otherwise stated. 2 Measured with VIn = VDD or VSS. 3 Measured with VIn = VSS. 4 Measured with VIn = VDD. 5 Factory trimmed at VDD = 3.0 V, Temperature = 25°C. Table 3-6. DC Characteristics (continued) Num C Parameter Symbol Min Typ 1 Max Unit –5.0E-3 –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 VDD–VOH (V) VSupply–VOH Average of IOH IOH (A) –40°C 25°C 125°C –6.0E-3

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 Series Data Sheet, Rev. 2

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3.7 Supply Current Characteristics

Table 3-7. Supply Current Characteristics Num C Parameter Symbol VDD (V) Typ1 1 Typical values are based on characterization data at 25°C unless otherwise stated. See Figure 3-5 through Figure 3-7 for typical curves across voltage/temperature. Max Unit Temp (°C) 1C Run supply current measured at (CPU clock = 2 MHz, fBus = 1 MHz)

2 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins

5 0.750 0.950 3 3 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. mA –40 to 125 °C3 0.570 0.770 2C Run supply current measured at (CPU clock = 16 MHz, fBus = 8 MHz)

4 All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins

5 4.9 5.10 5 5 Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization. mA –40 to 125 °C3 3.5 3.70 Stop2 mode supply current S2IDD 5 1.0 160 μA –40 to 85°C –40 to 125°C 3 0.8 150 μA –40 to 85°C –40 to 125°C 4C Stop3 mode supply current S3IDD 5 1.2 1803 μA –40 to 85°C –40 to 125°C 3 1.0 170 μA –40 to 85°C –40 to 125°C 5C RTI adder to stop2 or stop36 6 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Wait mode typical is 560 μA at 3 V with fBus = 1 MHz. S23IDDRTI 53 0 0 500 500 nA –40 to 85°C –40 to 125°C 33 0 0 500 500 nA –40 to 85°C –40 to 125°C

6 C LVD adder to stop3 (LVDE = LVDSE = 1) S3I

180 μA –40 to 85°C –40 to 125°C 39 0 160 160 μA –40 to 85°C –40 to 125°C 7C Adder to stop3 for oscillator enabled (OSCSTEN =1) 7 Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode (HGO = 0), clock monitor disabled (LOCD = 1). S3IDDOSC 5,3 5 8 μA μA –40 to 85°C –40 to 125°C

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 19 Figure 3-5. Typical Run IDD for FBE and FEE Modes, IDD vs. VDD IDD VDD

20 MHz, ADC off, FEE, 25°C

20 MHz, ADC off, FBE, 25°C

8 MHz, ADC off, FEE, 25°C

8 MHz, ADC off, FBE, 25°C

1 MHz, ADC off, FEE, 25°C

1 MHz, ADC off, FBE, 25°C

Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 Series Data Sheet, Rev. 2

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Figure 3-6. Typical Stop 2 IDD Figure 3-7. Typical Stop3 IDD –5.0E-3 –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 –6.0E-3 –7.0E-3 –8.0E-3 1.8 2 2.5 3 3.5 4 4.5 5 Stop2 IDD (A) Average of Measurement IDD IDD (A) VDD (V) –40°C 25°C 55°C 85°C –5.0E-3 –4.0E-3 –3.0E-3 –2.0E-3 –1.0E-3 000E+0 –6.0E-3 –7.0E-3 –8.0E-3 1.8 2 2.5 3 3.5 4 4.5 5 Stop3 IDD (A) Average of Measurement IDD IDD (A) VDD (V) 25°C 55°C 85°C –40°C

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 21

3.8 ADC Characteristics

Table 3-8. 5 Volt 10-bit ADC Operating Conditions Characteristic Conditions Symb Min Typ 1 1 Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. Max Unit Supply voltage Absolute VDDAD 2.7 — 5.5 V Delta to VDD (VDD–VDDAD)2 2 dc potential difference. ΔVDDAD –100 0 +100 mV Ground voltage Delta to V SS (VSS–VSSAD)2 ΔVSSAD –100 0 +100 mV Ref voltage high VREFH 2.7 VDDAD VDDAD V Ref voltage low VREFL VSSAD VSSAD VSSAD V Supply current Stop, reset, module off I DDAD — 0.011 1 μA Input voltage V ADIN VREFL —V REFH V Input capacitance C ADIN —4 . 5 5 . 5 p F Input resistance RADIN —3 5 k Ω Analog source resistance External to MCU 10-bit mode fADCK > 4MHz fADCK < 4MHz RAS 10 kΩ 8-bit mode (all valid f ADCK)— — 10 ADC conversion clock frequency High speed (ADLPC = 0) fADCK 0.4 — 8.0 MHz Low power (ADLPC = 1) 0.4 — 4.0 Temp Sensor Slope –40°C to 25°C m — 3.266 — mV/° C25°C to 125°C 3.638 — Temp Sensor Voltage 25°CV TEMP25 — 1.396 — V

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Figure 3-8. ADC Input Impedance Equivalency Diagram VAS RAS CAS VADIN ZAS Pad leakage due to input protection ZADIN SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT RADIN ADC SAR ENGINE SIMPLIFIED CHANNEL SELECT CIRCUIT INPUT PIN RADIN CADIN INPUT PIN RADIN INPUT PIN RADIN

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 23 Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Conditions C Symb Min Typ 1 Max Unit Supply current ADLPC = 1 ADLSMP = 1 ADCO = 1 TI DDAD — 133 — μA Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 TI DDAD — 218 — μA Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 TI DDAD — 327 — μA Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 TI DDAD — 582 — μA VDDAD < 5.5 V P— — 1 m A ADC asynchronous clock source tADACK = 1/fADACK High speed (ADLPC = 0) P fADACK 23 . 35 M H z Low power (ADLPC = 1) 1.25 2 3.3 Conversion time (Including sample time) Short sample (ADLSMP = 0) P t ADC —2 0— A D C K cycles Long sample (ADLSMP = 1) —4 0— Sample time Short sample (ADLSMP = 0) P t ADS —3 . 5— A D C K cycles Long sample (ADLSMP = 1) — 23.5 — Total unadjusted error Includes quantization 10-bit mode P E TUE — ±1 ±2.5 LSB 2 8-bit mode — ±0.5 ±1.0 Differential non-linearity 10-bit mode P DNL — ±0.5 ±1.0 LSB 2 8-bit mode — ±0.3 ±0.5 Monotonicity and no-missing-codes guaranteed Integral non-linearity 10-bit mode C INL — ±0.5 ±1.0 LSB 2 8-bit mode — ±0.3 ±0.5 Zero-scale error VADIN = VSSA 10-bit mode P EZS — ±0.5 ±1.5 LSB 2 8-bit mode — ±0.5 ±0.5 Full-scale error VADIN = VDDA 10-bit mode P EFS — ±0.5 ±1.5 LSB 2 8-bit mode — ±0.5 ±0.5 Quantization error 10-bit mode D E Q —— ±0.5 LSB 2 8-bit mode — — ±0.5

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3.9 Internal Clock Generation Module Characteristics

Pad leakage3 * RAS 10-bit mode D E IL — ±0.2 ±2.5 LSB 2 8-bit mode — ±0.1 ±1 1 Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Based on input pad leakage current. Refer to pad electricals. Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Symbol Min Typ 1 1 Typical values are based on characterization data at VDD = 5.0V, 25°C or is typical recommended value. Max Unit Load capacitors C1 See Note 2 2 See crystal or resonator manufacturer’s recommendation. Feedback resistor Low range (32k to 100 kHz) High range (1M – 16 MHz) R F 10 MΩ MΩ Series resistor Low range Low Gain (HGO = 0) High Gain (HGO = 1) High range Low Gain (HGO = 0) High Gain (HGO = 1) ≥ 8 MHz

4 MHz

1 MHz

R S 100 kΩ Table 3-9. 5 Volt 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Characteristic Conditions C Symb Min Typ 1 Max Unit ICG EXTAL XTAL Crystal or Resonator RS RF

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 25

3.9.1 ICG Frequency Specifications

Table 3-11. ICG Frequency Specifications (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient) Num C Characteristic Symbol Min Typ 1 1 Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. Max Unit Oscillator crystal or resonator (REFS = 1) (Fundamental mode crystal or ceramic resonator) Low range High range High Gain, FBE (HGO = 1,CLKS = 10) High Gain, FEE (HGO = 1,CLKS = 11) Low Power, FBE (HGO = 0, CLKS = 10) Low Power, FEE (HGO = 0, CLKS = 11) flo fhi_byp fhi_eng flp_byp flp_eng 100 kHz MHz MHz MHz MHz Input clock frequency (CLKS = 11, REFS = 0) Low range High range f lo fhi_eng 100 kHz MHz

3 Input clock frequency (CLKS = 10, REFS = 0) fExtal 0— 4 0 M H z

4 Internal reference frequency (untrimmed) fICGIRCLK 182.25 243 303.75 kHz

5 Duty cycle of input clock (REFS = 0) tdc 40 — 60 %

Output clock ICGOUT frequency CLKS = 10, REFS = 0 All other cases fICGOUT fExtal (min) flo (min) f Extal (max) fICGDCLKmax( max) MHz

7 Minimum DCO clock (ICGDCLK) frequency fICGDCLKmin 3— M H z

8 Maximum DCO clock (ICGDCLK) frequency fICGDCLKmax —4 0 M H z

9 Self-clock mode (ICGOUT) frequency 2

2 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. fSelf fICGDCLKmin fICGDCLKmax MHz 10 Self-clock mode reset (ICGOUT) frequency fSelf_reset 5.5 8 10.5 MHz Loss of reference frequency 3 Low range High range fLOR 5 500 kHz 12 Loss of DCO frequency 4 fLOD 0.5 1.5 MHz Crystal start-up time 5, 6 Low range High range t CSTL t CSTH 430 — ms FLL lock time , 7 Low range High range t Lockl tLockh ms

15 FLL frequency unlock range n

Unlock –4*N 4*N counts

16 FLL frequency lock range nLock –2N 2N counts

17 ICGOUT period jitter, , 8 measured at fICGOUT Max

Long term jitter (averaged over 2 ms interval) CJitter —0 .2 % fICG Internal oscillator deviation from trimmed frequency9 VDD = 2.7 – 5.5 V, (constant temperature) VDD = 5.0 V ±10%, –40° C to 125°C ACCint ±0.5 ±0.5 ±2 ±2 %

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Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency 3 Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. 4 Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range. 5 This parameter is characterized before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications. 7 This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.

9 See Figure 3-9

Average of Percentage Error 3 V 5 V Variable

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 27

3.10 AC Characteristics

This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 10, “Internal Clock Generator (S08ICGV4).”

3.10.1 Control Timing

Figure 3-10. Reset Timing Table 3-12. Control Timing Num C Parameter Symbol Min Typ 1 1 Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated. Max Unit

1 Bus frequency (t cyc = 1/fBus)f Bus dc — 20 MHz

2 Real-time interrupt internal oscillator period tRTI 700 1300 μs

3 External reset pulse width2

(tcyc = 1/fSelf_reset) 2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. textrst 1.5 x tSelf_reset —n s

4 Reset low drive3

3 When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests. trstdrv 34 x tcyc —n s

5 Active background debug mode latch setup time tMSSU 25 — ns

6 Active background debug mode latch hold time tMSH 25 — ns

4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. tILIH, tIHIL 100 1.5 x tcyc ——n s

8 KBIPx pulse width

tILIH, tIHIL 100 1.5 x tcyc ——n s Port rise and fall time (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) 5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C. tRise, tFall — ns textrst RESET PIN

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Figure 3-11. Active Background Debug Mode Latch Timing Figure 3-12. IRQ/KBIPx Timing

3.10.2 Timer/PWM (TPM) Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 3-13. TPM Input Timing Function Symbol Min Max Unit External clock frequency fTPMext dc fBus/4 MHz External clock period tTPMext 4— tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc Input capture pulse width tICPW 1.5 — tcyc BKGD/MS RESET tMSSU tMSH tIHIL IRQ/KBIP7-KBIP4 tILIH IRQ/KBIPx

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3.11 SPI Characteristics

Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system. Table 3-14. SPI Electrical Characteristic Num1 1 Refer to Figure 3-15 through Figure 3-18. C Characteristic2

2 All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI

pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Symbol Min Max Unit Operating frequency3 Master Slave 3 Maximum baud rate must be limited to 5 MHz due to pad input characteristics. fop fop fBus/2048 dc fBus/2 fBus/4 Hz

1 Cycle time

2 Enable lead time

3 Enable lag time

4 Clock (SPSCK) high time

tSCKH 1/2 tSCK – 25 — ns

5 Clock (SPSCK) low time Master

tSCKL 1/2 tSCK – 25 — ns

6 Data setup time (inputs)

tSI(M) tSI(S) ns ns

7 Data hold time (inputs)

tHI(M) tHI(S) ns ns

8 Access time, slave

4 Time to data active from high-impedance state. tA 04 0 n s

9 Disable time, slave5

5 Hold time to high-impedance state. tdis —4 0 n s

10 Data setup time (outputs)

11 Data hold time (outputs)

–10 –10 ns ns

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Figure 3-17. SPI Slave Timing (CPHA = 0) Figure 3-18. SPI Slave Timing (CPHA = 1) SCK (INPUT) SCK (INPUT) MOSI (INPUT) MISO (OUTPUT) SS (INPUT) MSB IN BIT 6 . . . 1 LSB IN MSB OUT SLAVE LSB OUT BIT 6 . . . 1 (CPOL = 0) (CPOL = 1) NOTE: SLAVE SEE NOTE 1. Not defined but normally MSB of character just received 6 7 10 11 SCK (INPUT) SCK (INPUT) MOSI (INPUT) MISO (OUTPUT) MSB IN BIT 6 . . . 1 LSB IN MSB OUT SLAVE LSB OUT BIT 6 . . . 1 SEE (CPOL = 0) (CPOL = 1) SS (INPUT) NOTE: SLAVE NOTE 1. Not defined but normally LSB of character just received 6 78 910 11

Chapter 3 Electrical Characteristics and Timing Specifications MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 33

3.12 FLASH Specifications

This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table 3-15. Flash Characteristics Num C Characteristic Symbol Min Typ 1 1 Typical values are based on characterization data at VDD = 5.0 V, 25°C unless otherwise stated. Max Unit 1P Supply voltage for program/erase Vprog/erase 2.7 5.5 V 2P Supply voltage for read operation VRead 2.7 5.5 V

3 P Internal FCLK frequency2

2 The frequency of this clock is controlled by a software setting. fFCLK 150 200 kHz 4P Internal FCLK period (1/FCLK) tFcyc 56 .67 μs 5P Byte program time (random location)(2) tprog 9 tFcyc 6C Byte program time (burst mode)(2) tBurst 4 tFcyc 7P Page erase time3 3 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. tPage 4000 tFcyc 8P Mass erase time(2) tMass 20,000 tFcyc Program/erase endurance4 TL to TH = –40°C to + 125°C T = 25°C 4 Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 10,000 100,000 cycles

10 C Data retention5

5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory. tD_ret 15 100 — years

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3.13 EMC Performance

Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.

3.13.1 Radiated Emissions

Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device. The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 3-16. Radiated Emissions Parameter Symbol Conditions Frequency f OSC/fBUS Level1 (Max) 1 Data based on laboratory test results. Unit Radiated emissions, electric field and magnetic field VRE_TEM VDD = 5.0 V TA = +25oC package type

80 LQFP

0.15 – 50 MHz 32kHz crystal 20MHz Bus 30 dBμV 50 – 150 MHz 32 150 – 500 MHz 19 500 – 1000 MHz 7 IEC Level I2 2 IEC and SAE Level Maximums: I=36 dBuV. SAE Level I2 —

Chapter 4 Ordering Information and Mechanical Drawings MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 35 Chapter 4 Ordering Information and Mechanical Drawings

4.1 Ordering Information

This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering system.

4.2 Orderable Part Numbering System

4.3 Mechanical Drawings

Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either:

Click on the appropriate link in Table 4-2, or
Open a browser to the Freescale ® website (http://www.freescale.com), and enter the appropriate document number (from Table 4-2) in the “Enter Keyword” search box at the top of the page. Table 4-1. Device Numbering System Device Number1 1 See Table 1-1 for a complete description of modules included on each device. Memory Available Packages2 2 See Table 4-2 for package information. FLASH RAM Type MC9S08AC128 128K 8K 80 LQFP , 64 QFP , 44-LQFP MC9S08AC96 96K 6K 80 LQFP , 64 QFP , 44-LQFP Table 4-2. Package Information Pin Count Type Designator Document No.

80 LQFP LK 98ASS23237W

64 QFP FU 98ASB42844B

44 LQFP FG 98ASS23225W

(C = –40°C to 85°C) (M = –40°C to 125°C) (MC = Fully Qualified) (9 = FLASH-based) MC 9 S08 AC C XX E Approximate memory size (in KB) (See Table 4-2) 128

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Chapter 5 Revision History MC9S08AC128 MCU Series Data Sheet, Rev. 2 Freescale Semiconductor 37 Chapter 5

Revision History

To provide the most up-to-date information, the version of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date Description of Changes Initial release of a separate data sheet and reference manual. Removed PTH7, clarified SPI as one full and one master-only, added missing RoHS logo, updated back cover addresses, and incorporated general release edits and updates. Added some finalized electrical characteristics. Added the parameter “Bandgap Voltage Reference” in Table 3-6 Updated Section 3.13, “EMC Performance” and corrected Table 3-16. Updated disclaimer page.

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