MC9RS08LE4 FREESCALE | Alldatasheet
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Data Sheet: Technical Data Document Number: MC9RS08LE4 Rev. 2, 11/2008 © Freescale Semiconductor, Inc., 2008. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MC9RS08LE4 Features:
- 8-Bit RS08 Central Processor Unit (CPU) – Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature range of –40°C to 85°C – Subset of HC08 instruction set with added BGND instructions
- O n - C h i p M e m o r y – 4 KB flash memory read/program/erase over full operating voltage and temperature – 256-byte random-access memory (RAM) – Security circuitry to prevent unauthorized access to flash memory contents
- Power-Saving Modes – Wait and stop
- Clock Source Options – Oscillator (XOSC) — Loop- control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 1 MHz to 20 MHz – Internal Clock Source (ICS ) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies up to 10 MHz
- System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-v oltage detection with reset or interrupt – Selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset – Flash memory block protection
- Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging
- Peripherals – LCD — Up to 8 × 14 or 4 × 18 segments; compatible with 5 V or 3 V LCD glass displays using on-chip resistor bias network; functional in wait, stop modes for very low power LCD operation; frontplane and backplane pins multiplexed with GPIO functions; selectable frontplane and backplane configurations – ADC — 8-channel, 10-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop; fully functional from 2.7 V to 5.5 V . – TPM — Two 2-channel 16-bit timer/pulse-width modulator (TPM) modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – SCI — One serial communicat ions interface module with optional 13-bit break; LIN extensions – KBI — 8-pin keyborad interrupt module
- Input/Output – 26 GPIOs including 1 output-only pin and 1 input-only pin – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins
- Package Options – 28-pin SOIC MC9RS08LE4
28 W-SOIC
MC9RS08LE4 MCU Data Sheet, Rev. 2 Freescale Semiconductor2 Table of Contents
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Date Description of Changes 1 10/6/2008 Initial public release. 2 11/3/2008 In Table 8, updated the WIDD, added the maximum of RIDD and SIDD at 5 V and deleted RTI adder from stop with 32.768 kHz crystal external clock source reference enabled. Added maximum of I OLT in Table 7. Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9RS08LE4RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
1 MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9RS08LE4 MCU. Figure 1. MC9RS08LE4 Block Diagram
2 Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08LE4.
20 MHz INTERNAL CLOCK
1 MHz to 20 MHz
256 BYTES
- PTB0/TCLK/RESET/VPP is an input-only pin when used as port pin
- PTB1/BKGD/MS is an output-only pin
MC9RS08LE4 MCU Data Sheet, Rev. 2 Freescale Semiconductor4 Table 2-1. Pin Availability by Package Pin-Count Pin Number <-- Lowest Priority --> Highest
28 Port Pin Alt 1 Alt 2 Alt 3
1 PTD3 KBIP7 LCD3
2 PTD2 KBIP6 LCD2
3 PTD1 KBIP5 LCD1
4 PTD0 KBIP4 LCD0
9 PTB0 TCLK RESET
10 PTB1 BKGD MS
11 PTB2 ADP0 LCD21
12 PTB3 ADP1 LCD20
13 PTB4 ADP2 LCD19
14 PTB5 ADP3 LCD18
15 PTB6 TPM1CH0 LCD17
16 PTB7 TPM1CH1 LCD16
17 PTA0 RxD LCD15
18 PTA1 TxD LCD14
19 PTA2 TPM2CH1 LCD13
20 PTA3 TPM2CH0 LCD12
21 PTA4 KBIP0 LCD11
22 PTA5 KBIP1 LCD10
23 PTA6 KBIP2 LCD9
24 PTA7 KBIP3 LCD8
25 PTD7 ADP7 LCD7
26 PTD6 ADP6 LCD6
27 PTD5 ADP5 LCD5
28 PTD4 ADP4 LCD4
Figure 2. MC9RS08LE4 in 28-Pin SOIC Package
3 Electrical Characteristics
3.1 Introduction
3.2 Parameter Classification
Table 2. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. sample size across process variations. D Those parameters are derived mainly from simulations.
3.3 Absolute Maximum Ratings
damage to the device. For functional operating conditions, refer to the remaining tables in this chapter. pull-up resistor associated with the pin is enabled.
3.4 Thermal Characteristics
Table 3. Absolute Maximum Ratings if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
solving equations 1 and 2 iteratively for any value of TA.
3.5 ESD Protection and Latch-Up Immunity
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge. of static without suffering any permanent damage. model (HBM), the machine model (MM) and the charge device model (CDM). Table 4. Thermal Characteristics
3.6 DC Characteristics
supply current in various operating modes. Table 5. ESD and Latch-up Test Conditions Table 6. ESD and Latch-Up Protection Characteristics
1 Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
1 Human body model (HBM) V HBM ±2000 — V
2 Machine model (MM) V MM ±200 — V
3 Charge device model (CDM) V CDM ±500 — V
2 These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of ±100 mA. 3 This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to ±75 mA. Table 7. DC Characteristics (Temperature Range = –40 to 85°C Ambient)
10 P Internal pullup/pulldown resistors2(all port pins) RPU 20 45 65 kΩ
12 C Maximum total I
14 C Maximum total IOL for all port pins IOLT —— 1 0 0 m A
16 C Input capacitance (all non-supply pins) CIn —— 7 p F
1 This parameter is characterized and not tested on each device. 2 Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown. resistance values for positive and negative clamp voltages, then use the larger of the two values. resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 This parameter is characterized and not tested on each device. Table 7. DC Characteristics (Temperature Range = –40 to 85°C Ambient) (continued)
3.7 Supply Current Characteristics
Table 8. Supply Current Characteristics Num C Parameter Symbol Bus Freq.
Figure 11. Typical RIDD vs. VDD (FEI, BusFreq. = 10 MHz)
2 Does not include any dc loads on port pins
3 Required asynchronous ADC clock and LVD to be enabled. 4 Most customers are expecteed to find that auto-wakeup from stop can be used instead of the higher current wait mode. Table 8. Supply Current Characteristics (continued) Num C Parameter Symbol Bus Freq.
3.8 External Oscillator (XOSC) Characteristics
Refer to Figure 12 for crystal or resonator circuit. Figure 12. Typical Crystal or Resonator Circuit Table 9. External Oscillator Specifications (Temperature Range = –40 to 85°C Ambient) 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
2 D Load capacitors C1
2 See crystal or resonator manufacturer’s recommendation.
4 MHz
1 MHz
3 This parameter is characterized and not tested on each device. 4 Proper PC board layout procedures must be followed to achieve specifications.
3.9 Internal Clock Source (ICS) Characteristics
3.10 AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) 1 Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
5 C DCO output frequency range — trimmed f dco_t 16 16 20 MHz
8 C FLL acquisition time 3,2
the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Table 11. Control Timing
1 D Bus frequency (t cyc = 1/fBus)f Bus 0— 1 0 M H z
2 D Real time interrupt internal oscillator period t RTI 700 1000 1300 μs
3 D External RESET pulse width1
5 D KBI pulse width in stop 1 tKBIPWS 100 — — ns
6 C Port rise and fall time (load = 50 pF) 3
Figure 13. Reset Timing Figure 14. KBI Pulse Width
3.10.2 TPM Module Timing
Figure 15. Timer External Clock or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 3 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C. Table 12. TPM/MTIM Input Timing
1 D External clock frequency f TCLK 0f Bus1/4 MHz
2 D External clock period t TCLK 4— t CYC
Figure 16. Timer Input Capture Pulse
3.11 ADC Characteristics
Figure 17. 5 Volt 10-bit ADC Operating Conditions for reference only and are not tested in production.
Figure 18. ADC Input Impedance Equivalency Diagram Table 13. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
3.12 Flash Specifications
memory. For detailed information about program/erase operations, see the reference manual.
10 P Differential
11 C Integral
12 P Zero-scale error
13 P Full-scale error
14 D Quantization
reference only and are not tested in production. 3 Based on input pad leakage current. Refer to pad electrical. Table 14. Flash Characteristics Table 13. 10-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Figure 19. Example VPP Filtering
5 P Byte program time t prog 20 — 40 μs
6 P Mass erase time t me 500 — — ms
7 C Cumulative program HV time 2 thv —— 8 m s
9 D HVEN to program setup time t pgs 10 — — μs
10 D PGM/MASS to HVEN setup time t nvs 5— — μs
11 D HVEN hold time for PGM t nvh 5— — μs
12 D HVEN hold time for MASS t nvh1 100 — — μs
13 D V PP to PGM/MASS setup time t vps 20 — — ns
14 D HVEN to V PP hold time t vph 20 — — ns
15 D V PP rise time3 tvrs 200 — — ns
16 D Recovery time t rcv 1— — μs
17 D Program/erase endurance
18 C Data retention t D_ret 100 — — years
1 Typicals are measured at 25 °C. programmed more than twice before next erase. VPP filter is shown in Figure 19. Table 14. Flash Characteristics (continued)
Figure 20. Flash Program Timing Figure 21. Flash Mass Erase Timing
4 Ordering Information
1 Next Data applies if programming multiple bytes in a single row, refer to MC9RS08LE4 Reference Manual. 2 VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
1 VDD must be at a valid operating voltage before voltage is applied or removed from
5 Mechanical Drawings
This following pages contain mechanical specifications for MC9RS08LE4 package options.
- 28-pin SOIC (small outli ne integrated circuit)
Table 15. Device Numbering System Flash RAM Type Designator Document No.
9 RS08 LE XX
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