MC9328MXL_06 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2004, 2005, 2006. All rights reserved. Freescale Semiconductor Data Sheet: Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC9328MXL Rev. 8, 12/2006 MC9328MXL
Package Information
(MAPBGA–225)
Ordering Information
1 Introduction
The i.MX Family of applications processors provides a leap in performance with an ARM9™ microprocessor core and highly integrated system functions. The i.MX family specifically addresses the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The MC9328MXL (i.MXL) processor features the advanced and power-efficient ARM920T™ core that operates at speeds up to 200 MHz. Integrated modules, which include a USB device, an LCD controller, and an MMC/SD host controller, support a suite of peripherals to enhance portable products seeking to provide a rich multimedia experience. It is packaged in either a 256-contact Mold Array Process-Ball Grid Array (MAPBGA) or 225-contact MAPBGA package. Figure 1 shows the functional block diagram of the i.MXL processor.
Contents
4 Functional Description and Application
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Figure 1. i.MXL Functional Block Diagram
1.1 Features
- ARM920T™ Microprocessor Core
- AHB to IP Bus Interfaces (AIPIs)
- External Interface Module (EIM)
- SDRAM Controller (SDRAMC)
- DPLL Clock and Power Control Module
- Two Universal Asynchrono us Receiver/Transmitters (UART 1 and UART 2)
- Serial Peripheral Interface (SPI)
- Two General-Purpose 32-bit Counters/Timers
- Watchdog Timer
- Real-Time Clock/Sampling Timer (RTC)
- LCD Controller (LCDC)
- Pulse-Width Modulation (PWM) Module
- Universal Serial Bus (USB) Device
- Multimedia Card and Secure Digita l (MMC/SD) Host Controller Module
- Memory Stick® Host Controller (MSHC)
- Direct Memory Access Controller (DMAC)
- Synchronous Serial Interface and an Inter-IC Sound (SSI/I 2S) Module
- I n t e r - I C ( I2C) Bus Module Watchdog GPIO LCD Controller JTAG/ICE CGM Timer 1 & 2 PWM Standard Bootstrap Connectivity System Control I2C MMC/SD SPI 1 and UART 1 UART 2 USB Device Memory Stick® Human Interface Video Port Multimedia Multimedia Power RTC BusDMAC InterruptVMMU CPU Complex MC9328MXL I Cache AIPI 1 AIPI 2 D Cache EIM & ARM9TDMI™ System I/OControl (PLLx2) Controller Control(11 Chnl) SDRAMC Accelerator SPI 2 Host Controller SSI/I2S
- V i d e o P o r t
- General-Purpose I/O (GPIO) Ports
- Bootstrap Mode
- Multimedia Accelerator (MMA)
- Power Management Features
- Operating V oltage Range: 1.7 V to 1.9 V core, 1.7 V to 3.3 V I/O
- 256-pin MAPBGA Package
- 225-contact MAPBGA Package
1.2 Target Applications
digital MP3 audio players, handheld computers, and messaging applications.
1.3 Ordering Information
Table 1 provides ordering information.
1.4 Conventions
- OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
- Logic level one is a voltage that corresponds to Boolean true (1) state.
- Logic level zero is a voltage that corresponds to Boolean false (0) state.
- T o set a bit or bits means to establish logic level one.
- T o clear a bit or bits means to establish logic level zero.
- A signal is an electronic construct whose state conveys or changes in state convey information.
Table 1. i.MXL Ordering Information
150 MHz 0 OC to 70OC Pb-free MC9328MXLVM15(R2)
150 MHz 0°C to 70°C Pb-free MC9328MXLVP15(R2)
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- A pin is an external physical connection. The same pin can be used to connect a number of signals.
- Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. — Active high signals change from logic level zero to logic level one.
- Negated means that an asserted discrete signal changes logic state. — Active low signals change from logic level zero to logic level one. — Active high signals change from logic level one to logic level zero.
- LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out.
- Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
2 Signals and Connections
are grouped by the internal module that they are connected to. Table 2. i.MXL Signal Descriptions EB0 MSB Byte Strobe—Active low external enable byte signal that controls D [31:24]. EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16]. EB2 Byte Strobe—Active low external enable byte signal that controls D [15:8]. EB3 LSB Byte Strobe—Active low external enable byte signal that controls D [7:0]. OE Memory Output Enable—Active low ou tput enables external data bus. Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. on-going burst sequence and initiate a new (long first access) burst sequence. BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode. terminated by the external DTACK signal after 1022 clock counts have elapsed.
reset is determined by the settings of these pins. are logically equivalent to core address p_addr [25:21] in SDRAM cycles. signals are logically equivalent to core address p_addr [12:9] in SDRAM cycles. by programming the system control register. chip-select by properly configuring BOOT [3:0] input pins. CLKO Clock Out signal selected from internal clock signals. modules (except the reset module and the clock control module) are reset. following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. generated by an external RC circuit designed to detect a power-up event. Table 2. i.MXL Signal Descriptions (Continued)
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TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. TDO Serial Output for test instructions and data. Changes on the falling edge of TCK. TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK. TCK Test Clock to synchronize test logic and control register access through the JTAG port. DMA_REQ DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY. change state after power-on reset negates or during chip operation. ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. driver (dedicated signal SPS for Sharp panel HR-TFT). ACD/OE Alternate crystal direction/output enable. CONTRAST This signal is used to control the LCD bias voltage as contrast control. SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal). PS Control signal output for source driver (Sharp panel dedicated signal).
REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. the MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. MC9328MXL Reference Manual for information about how to bring this signal to the assigned pin. enable register, a 4.7K–69K external pull up resistor must be added.
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register, a 50K–69K external pull up resistor must be added. purposes, not for use in application mode.
2.1 I/O Pads Power Supply and Signal Multiplexing Scheme
configuring the appropriate GPIO registers when those pins are multiplexed to provide different functions. Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme
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Table 3. MC9328MXLMC9328MXS Signal Multiplexing Scheme (Continued)
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1 Pull down this input with 1KΩ resistor to GND. 2 External circuit required to drive this input. 3 Tie this input high (to AVDD) or pull down with 1KΩ resistor to GND. 4 Pull up this output with a resistor to NVDD2.
Electrical Characteristics
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 17
3 Electrical Characteristics
This section contains the electrical specifications and timing diagrams for the i.MXL processor.
3.1 Maximum Ratings
Table 4 provides information on maximum ratings which are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits listed in Recommended Operating Range Table 5 on page 18 or the DC Characteristics table.
3.2 Recommended Operating Range
Table 5 provides the recommended operating ranges for the supply voltages and temperatures. The i.MXL processor has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because A VDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the A VDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4. Table 4. Maximum Ratings core-that is, 7x GPIO, 15x Data bus, and 8x Address bus. each toggle GPIO consuming 4mA.
MC9328MXL Technical Data, Rev. 8
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3.3 Power Sequence Requirements
For required power-up and power-down sequencing, please refer to the “Power-Up Sequence” section of application note AN2537 on the i.MX applications processor website.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the i.MXL processor. Table 5. Recommended Operating Range
1 Standby current
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 19
3.5 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading. VIH Input high voltage 0.7V DD –V d d + 0 . 2 V VIL Input low voltage – – 0.4 V VOH Output high voltage (IOH = 2.0 mA) 0.7V DD –V d d V VOL Output low voltage (IOL = -2.5 mA) – – 0.4 V IIL Input low leakage current (VIN = GND, no pull-up or pull-down) ––± 1 μA IIH Input high leakage current (VIN =V DD, no pull-up or pull-down) ––± 1 μA IOH Output high current (VOH =0 . 8 VDD, VDD =1 . 8 V ) 4.0 – – mA IOL Output low current (VOL =0 . 4 V , VDD =1 . 8 V ) -4.0 – – mA IOZ Output leakage current (Vout =V DD, output is high impedance) ––± 5 μA Ci Input capacitance – – 5 pF Co Output capacitance – – 5 pF Table 7. Tristate Signal Timing Table 8. 32k/16M Oscillator Signal Timing 1 The 16 MHz oscillator is not recommended for use in new designs. Table 6. Maximum and Minimum DC Characteristics (Continued)
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4 Functional Description and Application Information
4.1 Embedded Trace Macrocell
- 32-bit data field
- 7-bit address field
- A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used in Figure 2.
Figure 2. Trace Port Timing Diagram Table 9. Trace Port Timing Diagram Parameter Table
1 CLK frequency 0 85 0 100 MHz
4.2 DPLL Timing Specifications
pre-divider and Tdck is the output double clock period. Table 10. DPLL Specifications Table 9. Trace Port Timing Diagram Parameter Table (Continued)
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4.3 Reset Module
Figure 3. Timing Relationship with POR Figure 4. Timing Relationship with RESET_IN
4.4 External Interface Module
EIM is shown in Figure 5, and Table 12 defines the parameters of signals. Table 11. Reset Module Timing Parameter Table
1 Width of input POWER_ON_RESET note1
for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals. Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal. calculating timing for the start-up process.
2 Width of internal POWER_ON_RESET
5 Width of external hard-reset RESET_IN 4 – 4 – Cycles of
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Figure 5. EIM Bus Timing Diagram Table 12. EIM Bus Timing Parameter Table
4.4.1 DTACK Signal Description
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2 DTACK Signal Timing
of measure for this figure are found in the associated tables.
1 Clock refers to the system clock signal, HCLK, generated from the System DPLL
Table 12. EIM Bus Timing Parameter Table (Continued)
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4.4.2.1 WAIT Read Cycle without DMA
Figure 6. WAIT Read Cycle without DMA Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
4 Wait asserted after OE asserted – 1020T ns
7 Data ready after wait asserted 0 T ns
10 Become low after CS5 asserted 0 1019T ns
11 Wait pulse width 1T 1020T ns
- T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
EBC bit in CS5L register is clear.
- Address becomes valid and CS asserts at the start of read access cycle.
- The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.2 WAIT Read Cycle DMA Enabled
Figure 7. DTACK WAIT Read Cycle DMA Enabled Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
5 Wait asserted after CS5 asserted – 1020T ns
8 Data ready after wait is asserted – T ns
11 Wait becomes low after CS5 asserted 0 1019T ns
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4.4.2.3 WAIT Write Cycle without DMA
Figure 8. WAIT Write Cycle without DMA
12 Wait pulse width 1T 1020T ns
- T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
- OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
- Address becomes valid and CS asserts at the start of read access cycle.
- The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
6 Wait asserted after CS5 asserted – 1020T ns
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
4.4.2.4 WAIT Write Cycle DMA Enabled
Figure 9. WAIT Write Cycle DMA Enabled
9 Data ready after CS5 is asserted – T ns
- T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
- CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
- Address becomes valid and RW asserts at the start of write access cycle.
- The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
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4.4.3 EIM External Bus Timing
in Figure 5, and Table 12 defines the parameters of signals. Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
1 C S 5 assertion time See note 2 – ns
10 CS deactive to next CS active T – ns
12 Wait becomes low after CS5 asserted 0 1019T ns
13 Wait pulse width 1T 1020T ns
- T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
- CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
- Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Figure 10. WSC = 1, A.HALF/E.HALF
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Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
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Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
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Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
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Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
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Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
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Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
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Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
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Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
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Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
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Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
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Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
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4.4.4 Non-TFT Panel Timing
Figure 33. Non-TFT Panel Timing
4.5 SPI Timing Diagrams
different triggering mechanisms. Table 17. Non TFT Panel Timing Diagram 1 Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. 2 Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong. these 3 signals are active high. 4 Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). 5 Ts is the shift clock period. Ts = Tpix * (panel data bus width).
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Figure 39. SPI SCLK Timing Diagram
4.6 LCD Controller
Figure 40. SCLK to LD Timing Diagram Table 18. Timing Parameter Table for Figure 34 through Figure 38
1 SPI_RDY to SS output low 2T1
1 T = CSPI system clock period (PERCLK2).
3 Last SCLK edge to SS output high 2 Tsclk – ns
3 WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register. Table 19. Timing Parameter Table for SPI SCLK
8 SCLK frequency 0 10 MHz
9 SCLK pulse width 100 – ns
Figure 41. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table 20. LCDC SCLK Timing Parameter Table
1 SCLK to LD valid – 2 ns
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
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4.7 Multimedia Card/Secure Digital Host Controller
MMC/SD module (inner system) and the application (user programming). Figure 42. Chip-Select Read Cycle Timing Diagram
22 T s
11 T s
- Ts is the SCLK period which equals LCDC_C LK / (PCD + 1). Normally LCDC_CLK = 15ns.
- VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals are active low.
- The polarity of SCLK and LD[ 15:0] can also be programmed.
- SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 41, SCLK is always active.
- For T9 non-display region, VSYN is non-act ive. It is used as an reference.
- XMAX is defined in pixels.
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
4.7.1 Command Response Timing on MMC/SD Bus
Figure 47 are defined in Table 23. Table 22. SDHC Bus Timing Parameter Table
1 CLK frequency at Data transfer Mode
1 CL ≤ 100 pF / 250 pF (10/30 cards)
2 CLK frequency at Identification Mode 2
2 CL ≤ 250 pF (21 cards)
3 CL ≤ 25 pF (1 card)
7 Output delay time 3 0 16 0 14 ns
Table 23. State Signal Parameters for Figure 43 through Figure 47
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Figure 43. Timing Diagrams at Identification Mode responding card. The other two diagrams show the separating periods NRC and NCC. Figure 44. Timing Diagrams at Data Transfer Mode data stops two clock cycles after the end bit of the stop command.
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Figure 46. Timing Diagrams at Data Write different scenarios on the bus.
Figure 47. Stop Transmission During Different Scenarios Table 24. Timing Values for Figure 43 through Figure 47 Stop transmission received after last data block. Card becomes busy programming. Stop transmission received after last data block. Card becomes busy programming.
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4.7.2 SDIO-IRQ and ReadWait Service Handling
continues until the source is removed (SD_DAT[1] returns to its high level). Figure 48. SDIO IRQ Timing Diagram Table 24. Timing Values for Figure 43 through Figure 47 (Continued)
Figure 49. SDIO ReadWait Timing Diagram
4.8 Memory Stick Host Controller
either four-state or two-state access mode. completed within one packet length (in four-state access mode). and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
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Figure 50. MSHC Signal Timing Diagram Table 25. MSHC Signal Timing Parameter Table
1 MS_SCLKI frequency – 25 MHz
2 MS_SCLKI high pulse width 20 – ns
3 MS_SCLKI low pulse width 20 – ns
4 MS_SCLKI rise time – 3 ns
5 MS_SCLKI fall time – 3 ns
6 MS_SCLKO frequency
7 MS_SCLKO high pulse width 1 20 – ns
8 MS_SCLKO low pulse width 1 15 – ns
9 MS_SCLKO rise time 1 –5 n s
10 MS_SCLKO fall time 1 –5 n s
11 MS_BS delay time 1 –3 n s
4.9 Pulse-Width Modulator
Figure 51 and the parameters are listed in Table 26. Figure 51. PWM Output Timing Diagram
12 MS_SDIO output delay time 1,2 –3 n s
13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0) 3 18 – ns
14 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0) 3 0– n s
15 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1) 4 23 – ns
16 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1) 4 0– n s
1 Loading capacitor condition is less than or equal to 30pF . 3 If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge. 4 If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge. Table 26. PWM Output Timing Parameter Table
1 System CLK frequency 1 08 70 1 0 0 M H z
Table 25. MSHC Signal Timing Parameter Table (Continued)
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4.10 SDRAM Controller
random access memory) Controller. Figure 52. SDRAM Read Cycle Timing Diagram
1 CL of PWMO = 30 pF
Table 26. PWM Output Timing Parameter Table (Continued) Note: CKE is high during the read/write cycle.
Table 27. SDRAM Read Timing Parameter Table
2 SDRAM clock low-level width
5 SDRAM access time (CL = 1) – 22 – 22 ns
7 Data out high-impedance time (CL = 1) – 22 – 22 ns
8 Active to read/write command period (RC = 1) t
1 tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
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Figure 53. SDRAM Write Cycle Timing Diagram Table 28. SDRAM Write Timing Parameter Table
2 SDRAM clock low-level width 6–4– n s
6 Precharge cycle period
1 Precharge cycle timing is included in the write timing diagram. 2 tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
7 Active to read/write command delay t RCD2 –t RCD2 –n s
Figure 54. SDRAM Refresh Timing Diagram Table 29. SDRAM Refresh Timing Parameter Table
6 Precharge cycle period t
1 tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
7 Auto precharge command period t RC1 –t RC1 –n s
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Figure 55. SDRAM Self-Refresh Cycle Timing Diagram
4.11 USB Device Port
covers the transfer modes and how they work from the ground up. bandwidth at all times, there is no end-of-transfer.
Figure 56. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 30. USB Device Timing Parameters for Data Transfer to USB Transceiver (TX)
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Figure 57. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
4.12 I 2C Module
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 58. Definition of Bus Timing for I2C Table 31. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
4.13 Synchronous Serial Interface
mode, the transmitter and receiver each have their own clock and frame synchronization signals. are shown in Figure 60 through Figure 62. communicate with a wide variety of devices. Figure 59. SSI Transmitter Internal Clock Timing Diagram Table 32. I2C Bus Timing Parameter Table
1 Hold time (repeated) START condition 182 – 160 – ns
2 Data hold time 01 7 101 5 0 n s
4 HIGH period of the SCL clock 80 – 120 – ns
5 LOW period of the SCL clock 480 – 320 – ns
Note: SRXD input in synchronous mode only.
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Figure 60. SSI Receiver Internal Clock Timing Diagram Figure 61. SSI Transmitter External Clock Timing Diagram
Figure 62. SSI Receiver External Clock Timing Diagram Table 33. SSI (Port C Primary Function) Timing Parameter Table
14 SRXD hold time after SRCK low 0 – 0 – ns
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30 SRXD hole time after SRCK low 0 – 0 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. 3 bl = bit length; wl = word length. Table 33. SSI (Port C Primary Function) Timing Parameter Table (Continued)
Table 34. SSI (Port B Alternate Function) Timing Parameter Table
18 STCK high to STFS (bl) high
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4.14 CMOS Sensor Interface
FIFO, and a 16 × 32 statistic data FIFO.
4.14.1 Gated Clock Mode
data in negative edge. The parameters for the timing diagrams are listed in Table 35.
30 SRXD hold time after SRCK low 0 – 0 – ns
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. 3 bl = bit length; wl = word length. Table 34. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
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For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
4.14.2 Non-Gated Clock Mode
data in negative edge. The parameters for the timing diagrams are listed in Table 36. Figure 65. Sensor Output Data on Pixel Clock Falling Edge
Figure 66. Sensor Output Data on Pixel Clock Rising Edge For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. Table 36. Non-Gated Clock Mode Parameters
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5 Pin-Out and Package Information
Multiplexing Table 3 on page 9. Table 37. i.MXL 256 MAPBGA Pin Assignments 1 This signal is not used and should be floated in an actual application.
Signal Multiplexing Table 3 on page 9. Table 38. i.MXL 225 MAPBGA Pin Assignments
1 Burst Clock
2 This signal is not used and should be floated in an actual application.
86 Freescale Semiconductor
5.1 MAPBGA 256 Package Dimensions
Figure 67 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, with an 0.8 mm pad pitch. The device designator for the MAPBGA package is VH. Figure 67. i.MXL 256 MAPBGA Mechanical Drawing
- ALL DIMENSIONS ARE IN MILLIMETERS.
2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
- DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
5.2 MAPBGA 225 Package Dimensions
Figure 68 illustrates the 225 MAPBGA 13 mm × 13 mm package. Figure 68. i.MXL 225 MAPBGA Mechanical Drawing
- ALL DIMENSIONS ARE IN MILLIMETERS.
2.DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
- DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER
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6 Product Documentation
6.1 Revision History
and not stylistic or grammatical changes.
6.2 Reference Documents
Table 39. i.MXL Data Sheet Revision History Rev. 8 Added the DMA_REQ signal to table. Table 3 on page 9 Added Signal Multiplex table.
MC9328MXL Technical Data, Rev. 8 Freescale Semiconductor 89
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